the performance is just too close considering one has double the cache!
the only explanation i can fathom is lower latency L2 cache on the allendales
or i could be totally wrong....does anyone know?
the performance is just too close considering one has double the cache!
the only explanation i can fathom is lower latency L2 cache on the allendales
or i could be totally wrong....does anyone know?
DFI P965-S/core 2 quad q6600@3.2ghz/4gb gskill ddr2 @ 800mhz cas 4/xfx gtx 260/ silverstone op650/thermaltake xaser 3 case/razer lachesis
i test a abit with pi 1m, super pi 1m reflect cache , cache doesn't affect 32m
3.6G 2M VS 3.2G 4M
i think per clock/performance , L2 4m 20% faster than 2m
super pi 32m and cpumark99 doesn't reflect cache issue
E6400@3.2G (8*400) 32M & cpumark99
X6800@3.2G(8*400) 32M & cpumark99
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i read a review which showed an underclock 6800 at allendale speeds and then running benches between that and an actual Allendale cpu..there were only, the most, a 5-6% difference in bench performance and some were only 1-2%
really, can u show the link?Originally Posted by Ace-a-Rue
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yea, the conclusion they got was that there was barely any difference
thats what started me thinking
cause the situation now seems to parrallel when intel released the 2mb prescott and performed almost the same as the 1mb prescott
DFI P965-S/core 2 quad q6600@3.2ghz/4gb gskill ddr2 @ 800mhz cas 4/xfx gtx 260/ silverstone op650/thermaltake xaser 3 case/razer lachesis
unfortunately, i did not bookmark the review....sorry!Originally Posted by hicookie
but, it is clear to me that L2 cache is important but the jump from 2 Mb to 4 Mb is probably not as significant as it looks on paper or feels in our mind.![]()
Have any websites looked at how the cache plays a role as the frequency increases? I'd like to see an X6800 with a 7x multiplier in comparison to a 6300 from stock to 2.8Ghz.
Also, does anyone know the associativity of the cache on the 2mb vs. 4mb? Is it only 4-way on 2mb or is it 8-way for both?
look at the link plaicd posted lol
yea, the difference isnt as big as i think it should be, which leads me to believe the l2 cache on the allendale has a slightly lower latency than that of the conroe...it would be interesting to find out if this was true
DFI P965-S/core 2 quad q6600@3.2ghz/4gb gskill ddr2 @ 800mhz cas 4/xfx gtx 260/ silverstone op650/thermaltake xaser 3 case/razer lachesis
I looked at the techreport article earlier, but all they have is the overclocking page which does not give you any idea of how the cache size matters at higher clocks. What i'm saying is take an X6800, set the multiplier at 7. Then increase the fsb in increments along with an E6300 all the way upto a high clock such as 2.8GHz. Then compare how the cache influences the performance in various tasks. I believe multithreaded performance for encoding would be most interesting. So a line graph with performance deltas between the two processors. I'll look into other reasons for possible latency improvements on the 2mb. I believe that these are the same physical cores as the conroes with part of the cache disabled. The E4000 series will have a smaller reduced core. Even then I dont know if thats true because economically its cheaper to produce unused silicon and disable it than to make a separate mask and production process.Originally Posted by grimREEFER
allendale L1 and L2 is 8-way.Originally Posted by aashburns
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I did a thread on this. Apparently for 3D graphics Intel did not short change us L2 cache on the allendales (unlike my celeron where its L2 deficient)
As far as other applications go Anandtech reports anywhere from 3-10% improvement.
However I really want to know how 4 mb L2 cache scales in the high 3.5+ GHz clock speeds? Does it make more difference or less under those conditions?
if the clocks speeds are equal on both 2mb and 4mb the difference is still going to be the same as quoted above. if your running something like superpi for caculations all day long get the 4mb by all means.Originally Posted by Phosphate
Intel Pentium G3258 | ASRock Z97M OC Formula | Samsung 2x4GB DDR3-1600 | Galaxy GTX660 GC | Samsung PM840 Pro 128GB, PM830 250GB FDE |
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Since Conroe is 16-way and if Allendale is 8-way, then the associativity of the cache is lower. Hence, there will be a slight performance hit from an increase in the rate of cache misses. I can't think of any reason why the allendale cache would have less latency is this case since it is the same die as conroe.Originally Posted by Evilsizer
I suppose this depends on what you are doing. Remember that Memory Bandwidth does not increase proportionaly with the FSB (e.g. C2D can double its speed with careful overclocking, but memory cannot). Applications that frequently access more than 2MB data will definitely benefit from the larger cache. Not to mention at 3.5GHz the number of CPU cyles the C2D waits for memory (latency) is almost twice as much as a stock E6300. So the effectiveness of prefetchers is reduced as clock speeds increase. My guess is that Intel will include an on-die memory controller once the clock speeds reach a level at where prefetchers cannot hide the horrible latency of memory.Originally Posted by Evilsizer
Last edited by aashburns; 08-10-2006 at 11:52 PM.
you have to realize that fullspeed cache is a lot easier to do without upping the latency on a lower clocked system than it is on a higherclocked netburst system. Atleast that is my guesse.
Originally Posted by Ace-a-Rue
i found the answer and i posted it here:Originally Posted by hicookie
http://www.xtremesystems.org/forums/...03#post1645603
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