A64Info - New CPU ID and memory tweaking tool! - feedback welcome...

[lukija]

Although...i think i found a bug (or a misunderstanding).

When i clock down the multi (with rmclock, Cool'n'Quiet etc.), say my default is 11x and i clock down to 4xHTT...then A64info says that i have a mem-divider on and also says my memory speed is down to 183.

I get it. Take a look at this post:

http://www.xtremesystems.org/forums/...62&postcount=7

Smallest possible memory divider is 5, According to Oskar Wu. So, your CPU is running at 4 x 230 = 920MHz. Memclk is 200MHz, and memory divider should be 4, but 4 is less than 5, so divider is 5. Memory speed is 920 / 5 = 184 MHz. Of course , this is theory. A64Info is calculating memory speed with respect to HTT, Multi, Memclk, ODC using known rules. It would be nice if A64 had some register which contains actual divider, but AFAIK there isn't one.

So..going thru the AMD bios/kernel white papers (i love them)...i see that certain registers are not even implemented in winchester (eg. Dram data strenght- they just came with revision E)

Its right i can not set them with A64info, but it would be nice if those would be grayed out so you see which ones are available for what CPU revision.
Just a thought.

You are 100% percent right. Since A64Info is still under development, I'm focusing on the most importaint things. Polishing will be done later, I still have to add nf4 support, multiplier change and other stuff. I think this specific parameters have no effect on older cores. I tried on my Winchester to set 233 memlck ( which is E rev specific) and it just ignored settings. I guess it is the same story with other parameters. Please, try to set them, see if values change.

[RaMmElEe]

I still have to add nf4 support, multiplier change and other stuff.

Great news, with A64info + nF4clock + multiplier change & if voltage change as CrystalCPUID did but all the way up to 1.6v. Why we boot into bios then. Looking forward to see your new version. Great job lukija.

[flexy]

I get it. Take a look at this post:

http://www.xtremesystems.org/forums/...62&postcount=7

Smallest possible memory divider is 5, According to Oskar Wu. So, your CPU is running at 4 x 230 = 920MHz. Memclk is 200MHz, and memory divider should be 4, but 4 is less than 5, so divider is 5. Memory speed is 920 / 5 = 184 MHz. Of course , this is theory. A64Info is calculating memory speed with respect to HTT, Multi, Memclk, ODC

hi
What i want to say is....i SHOULD still have my original "divider" which i have in bios...1:1, MEMCLK=200, HTT=230

When i use rightmark rmclock it can set multi to anything from 4x to 11x depending on load under XP, clocking the CPU up or down...but i dont THINK it would activate a divider. But A64info says i have a divider set (which i did not) and also the "real" memspeed should still be 230. (memclk=200 in bios, ok I think that you with A64info read the multi and calculate and show the theoretical calculated divider/memspeed...but in reality its just not set.

I still have to double-check and ask the author of rmclock...or check some white papers..but i really dont KNOW whether A64 sets the real memspeed always depending on multi or only ONCE in bios.

[lukija]

hi
What i want to say is....i SHOULD still have my original "divider" which i have in bios...1:1, MEMCLK=200, HTT=230

When i use rightmark rmclock it can set multi to anything from 4x to 11x depending on load under XP, clocking the CPU up or down...but i dont THINK it would activate a divider. But A64info says i have a divider set (which i did not) and also the "real" memspeed should still be 230. (memclk=200 in bios, ok I think that you with A64info read the multi and calculate and show the theoretical calculated divider/memspeed...but in reality its just not set.

Please send me a screenshot of CPU and DRAM tab. I tried on my rig 4x multi and memclk=200, A64Info reported memory divider as 5 , also CPU-Z reported the same.

[flexy]

You are 100% percent right. Since A64Info is still under development, I'm focusing on the most importaint things. Polishing will be done later, I still have to add nf4 support, multiplier change and other stuff. I think this specific parameters have no effect on older cores. I tried on my Winchester to set 233 memlck ( which is E rev specific) and it just ignored settings. I guess it is the same story with other parameters. Please, try to set them, see if values change.

its very interesting..because also bios-developers and even oscar probably dont know everything. Right now i INLYgo after the AMD bios/kernel white papers.

Fro example: In dfi lanparty bios there was ALWAYS a setting for DRM drive strength eg. Level 1 - 7 and people said there are SEVERAL levels of "weak"...eg. level 1, level 3, level 5 would all be different....and also the dram data strength you could set even LONG before Winchester Rev E.

In reality (see A64 registers) there seems to be only ONE bit for "Dram drive strength" (Weak or normal)....and data drive strength is only there since Rev E. I was messing around with those settings for months to get my system stable....with settings which did not even exist but you could change in bios

[lukija]

its very interesting..because also bios-developers and even oscar probably dont know everything. Right now i INLYgo after the AMD bios/kernel white papers.

Well, AMD does not mention:

- 180/150/140/120 memclk dividers (217/233/250 also!)
- half multis
- 20 missing tref values (only 12 are documented)

I'm trying to take the best from all sides and compile it. Same goes for core detection - my opteron is JH9-E6. Ok, I know about E6, and I know for JH, but whut is 9 standing for?

[ludeboy12]

not showing everything correctly here.......still a great lil proggy though.

[lukija]

not showing everything correctly here.......still a great lil proggy though.

Sorry, no AM2 support yet. I can add core regonition but DRAM settings are a way different.

[Plywood99]

its very interesting..because also bios-developers and even oscar probably dont know everything. Right now i INLYgo after the AMD bios/kernel white papers.

Fro example: In dfi lanparty bios there was ALWAYS a setting for DRM drive strength eg. Level 1 - 7 and people said there are SEVERAL levels of "weak"...eg. level 1, level 3, level 5 would all be different....and also the dram data strength you could set even LONG before Winchester Rev E.

In reality (see A64 registers) there seems to be only ONE bit for "Dram drive strength" (Weak or normal)....and data drive strength is only there since Rev E. I was messing around with those settings for months to get my system stable....with settings which did not even exist but you could change in bios

IIRC the different drive strengths on DFI mobos is a result of the mobo itself and not the cpu. Something to do with the way Oscar laid out the circuitry for the ram slots...

[flexy]

[QUOTE=lukija]It would be nice if A64 had some register which contains actual divider, but AFAIK there isn't one.

Is there a register (or some other good way) to read the actual/real memory speed ?

[lukija]

Is there a register (or some other good way) to read the actual/real memory speed ?

I was asking the same.