AMD embraces AVX making a new superset with SSE5(256bit support)

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05-01-2009, 08:00 PM
informal

AMD embraces AVX making a new superset with SSE5(256bit support)

Original find here.

Link to pdf:
http://support.amd.com/us/Processor_TechDocs/43479.pdf

This is BIG news.AMD is playing it safe this time and it seems that on paper Bulldozer will have one of the Sandy Bridge's main innovation(new 256bit wide instruction set).

edit: it looks like 4 operand instruction support is also there,so another (previously AVX exclusive) advantage of SB is matched by this.<-after edit2: this is an error on my part,SandyB won't support FMA4 nor FMA3(IvyBridge will).Look at edit 2.

edit 2:

To recap,after seeing additional info directly from AMD's devcentral(engineering dept blog) we now know what kind of capabilities wrt instruction set compatibility will be in Bulldozer cores and some info on Sandy Bridge uarch due out in 2010(SandyB won't support FMA at all):

1)As AMD's senior fellow stated in his blog Bulldozer will support: intel AVX version 5(meaning full avx spec support with 256b wide vectors),intel FMA version 3 and new extension set called XOP,CVT16,FMA4(former SSE5 instructions with new VEX decoding that were not covered with AVX v5 but could still be very convenient for HPC computing etc.).
2)While supporting AVX,intel's next tick (Sandy Bridge) won't have FMA support in any form. The FMA3 is reserved and planned for tock,a successor to SandyBridge cores(2011 planned). Sandy Bridge will support 256b wide vectors among other stuff AVX will bring ,but won't have FMA.
05-01-2009, 08:18 PM
Mechromancer

Holy crap! Bulldozer will be the best of both worlds. This is big news informal. Good find brother.

...I'm in shock I think....yea....

EDIT: The PDF doesn't specifically say AMD is adding Intel's AVX, but it is adding AVX-like instructions and capabilities. How about some of you engineers take a look and let us know what it all means.
05-01-2009, 08:25 PM
Glow9

In english?
05-01-2009, 08:42 PM
informal

It basically ads almost all AVX instructions except the SSE4.2(iirc 7 instructions) which is in i7.Big additions are FMA instructions. What AMD did with K8->K10 in terms of SSE throughput,they will do with new uarch. which will have 256b wide support for media instructions.
05-01-2009, 08:49 PM
roofsniper

Quote:

Originally Posted by Glow9

In english?

it means amd is not being retarded and going with an instruction set half the speed of their competitor.
05-01-2009, 08:56 PM
lockee

Quote:

Originally Posted by Glow9

In english?

The same guy who found the pdf had this to say.

Quote:

Basically, this instruction set extension allow AMD to "patch" the only two deficiencies of SSE5 (compared to AVX): 256-bit vectors and 4-operand instructions, while preserving all SSE5's (many) strengths.

In fact, looking at the instruction encoding, AMD did not intend or attempt to follow AVX. For example, AVX's 2-byte prefix format was not used, while AVX's 3-byte prefix format was used to allow access to the 4th operand and the 256-bit YMM registers.

This is IMHO an aggressive move. It is a confidence call from AMD, saying whatever we're going to do in our next generation will be better than yours (Intel's).
05-01-2009, 11:28 PM
Shintai

Its SSE5 thats AMDs own invention. In short its another 3DNow!, SSE4A. Good luck! :p:

AVX and SSE5 is fully incompatible so to say.

Nothing new really, nothing surprising.

http://en.wikipedia.org/wiki/Advanced_Vector_Extensions
http://softwarecommunity.intel.com/i...e-31943302.pdf
http://en.wikipedia.org/wiki/SSE5

SSE5 is more a SSE4 competitor than AVX.
05-01-2009, 11:31 PM
Glow9

Quote:

Originally Posted by lockee

The same guy who found the pdf had this to say.

Okay so to try and understand since I have no clue (note I'm being honest). The guy above said "instruction set half the speed of their competitor." So are you saying they have confidence because they are confident enough with their architecture that they can run it with something half the speed as Intel? I guess I don't follow that.
05-01-2009, 11:33 PM
informal

Quote:

Originally Posted by Shintai

Its SSE5 thats AMDs own invention. In short its anotehr 3DNow!, SSE4A. Good luck! :p:

AVX and SSE5 is fully incompatible to to say.

Nothing new really, nothing surprising.

*New* SSE5,the one AMD presents in the tech doc. is a superset of AVX.Whether it is supported or not is up to OS and compiler support. Remember AMD64 and EMT64 hw realizations(same but not the same on hw level-still compatible)? The fact is that AMD just matched AVX in performance by adding 4 operand instructions and 256b vectors...

Quote:

Originally Posted by Glow9

Okay so to try and understand since I have no clue (note I'm being honest). The guy above said "instruction set half the speed of their competitor." So are you saying they have confidence because they are confident enough with their architecture that they can run it with something half the speed as Intel? I guess I don't follow that.

He was referring to (now old) specification for 128bit media instructions/2 operand instr. support in Bulldozer versus the now released spec. of 256bit vector and 4 operand support-and this is a big difference.

PS: SSE5 notation is gone(as it seems) and AMD now calls this superset : 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions
05-01-2009, 11:47 PM
Shintai

Quote:

Originally Posted by informal

*New* SSE5,the one AMD presents in the tech doc. is a superset of AVX.Whether it is supported or not is up to OS and compiler support. Remember AMD64 and EMT64 hw realizations(same but not the same on hw level-still compatible)? The fact is that AMD just matched AVX in performance by adding 4 operand instructions and 256b vectors...

He was referring to (now old) specification for 128bit media instructions/2 operand instr. support in Bulldozer versus the now released spec. of 256bit vector and 4 operand support-and this is a big difference.

PS: SSE5 notation is gone(as it seems) and AMD now calls this superset : 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions

Its very very far from AVX. And calling it a superset means it should contain all AVX. And since it contains close to nothing or actually nothing..then no.

I dont think you actually understand this. Read the paper I linked.

Something compiled for AVX and something compiled for SSE5 is 100% incompatible. SSE5 is more a catchup to SSE4 and then add a few new things that will yet again prove useless in the long run. Not because it cant be used. But simply because of lack of support like always.

AMD64 and EMT64 wasnt even fully compatible. Plus I think you fail the concept of how the technology move. You dont add it overnight or even before. Look on all the previous times. Its always a catchup scenario. And this wont change anything.
05-02-2009, 12:06 AM
informal

Quote:

Originally Posted by Shintai

Its very very far from AVX. And calling it a superset means it should contain all AVX. And since it contains close to nothing or actually nothing..then no.

I dont think you actually understand this. Read the paper I linked.

Something compiled for AVX and something compiled for SSE5 is 100% incompatible. SSE5 is more a catchup to SSE4 and then add a few new things that will yet again prove useless in the long run. Not because it cant be used. But simply because of lack of support like always.

AMD64 and EMT64 wasnt even fully compatible. Plus I think you fail the concept of how the technology move. You dont add it overnight or even before. Look on all the previous times. Its always a catchup scenario. And this wont change anything.

I said that compiler support needs to be there,just as it needs to be there for AVX in order to be fully utilized(as intel designed it to). That's why AMD intros the tech doc. ~2 years before Interlagos hits the market,in order to get the necessary info out for developers and partners(an M$ is a partner and an important one). Did you forget AMD64 and who adopted who's implementation ?;)

BTW,original SSE5 was introduced approx. 2 years ago and in those days Interlagos(or whatever market name BD core had) was scheduled for 2009 release. We now know AMD postponed bulldozer and redesign it a bit,and we now know why they did it and what parts they redesigned(256bit support,4 operand instr.,new AVX like instructions).
Even original SSE5 with those specs promised some hefty perf. improvements versus the previous implementation,so AMD hardware will run even better with the extended instruction set when software gets coded properly for it.PGI and GCC were on board back in the 2007 with original SSE5,you can bet they will be in time Interlagos hits.

The important thing is AMD improved and matched AVX on hardware level and there are 2 years to get the developer and compiler support for it.Also it will be backwards compatible to all pre-SSE4 optimized software(which is a large majority)
05-02-2009, 12:07 AM
Macadamia

Yeah shintai, because AMD will probably be faster this round with compliant hardware. Look who's actually playing catchup.

All Intel did was just release specs to give devs an idea how it will be coded before they do it on AMD CPUs. Ooooh satisfaction.
05-02-2009, 12:13 AM
Shintai

Quote:

Originally Posted by informal

I said that compiler support needs to be there,just as it needs to be there for AVX in order to be fully utilized(as intel designed it to). That's why AMD intros the tech doc. ~2 years before Interlagos hits the market,in order to get the necessary info out for developers and partners(an M$ is a partner and an important one). Did you forget AMD64 and who adopted who's implementation ?;)

BTW,original SSE5 was introduced approx. 2 years ago and in those days Interlagos(or whatever market name BD core had) was scheduled for 2009 release. We now know AMD postponed bulldozer and redesign it a bit,and we now know why they did it and what parts they redesigned(256bit support,4 operand instr.,new AVX like instructions).
Even original SSE5 with those specs promised some hefty perf. improvements versus the previous implementation,so AMD hardware will run even better with the extended instruction set when software gets coded properly for it.PGI and GCC were on board back in the 2007 with original SSE5,you can bet they will be in time Interlagos hits.

The important thing is AMD improved and matched AVX on hardware level and there are 2 years to get the developer and compiler support for it.Also it will be backwards compatible to all pre-SSE4 optimized software(which is a large majority)

SSE5 aint AVX. And AMD64 was a whole other ballgame. AMD only won because MS said F U to Intel.

Everyone and their mother uses Intel compilers. They dont use MS or AMD compilers since they are slower. And again. SSE5 got nothing to do with AVX and its not a superset. Lookup that word please.

AMD dont even have full SSE4.x support yet.

And in best case, SSE5 is a dumped down version of SSE4 with some 256bit mix.

Please read Intels AVX paper. It will save alot of posting.

SSE4A ended as what today? Wasted transistors and designtime?

SSE5 is about 170 instructions with what, 50 as 256bit? AVX is close to 400, with ~half of them being 256bit.

And you claim SSE5 is a superset of AVX? Oh thats hilarious!

SSE5 is mostly Intels SSE4 with alittle 256bit mixed in. You could say its like SSE3+SSE4A when Intel had SSE3+SSE4.1
05-02-2009, 12:17 AM
eleeter

Quote:

Originally Posted by Shintai

AMD only won because MS said F U to Intel.

That is not the whole story. AMD brought x86 into the 64bit realm while Intel was trying to say Eff you to all of us and shove Itanium into the market, and all the while telling us "64bit computing is not needed on the desktop"
05-02-2009, 12:19 AM
eleeter

Quote:

Originally Posted by Shintai

Oh thats hilarious!

Your posts certainly are, in a tragic sort of way. :ROTF:
05-02-2009, 12:29 AM
Cooper

Please keep it peacfull. Attack the arguments not the persons.
05-02-2009, 12:31 AM
informal

Shintai ,there are about ~100 or less new instructions in AVX(new as not being previously supported by intel hw). The rest ,more than 300 legacy SSE instr. are updated for better performance on future hw(and less than 100 from those 300 are widened to 256bits to support those fp vector instructions).

BTW,SSE4a is 4(in words:four) instructions so the die space that was "wasted" is really huge(I can see AMD pulling their hair over this "wasted" space :rolleyes:). Two of those four(LZCNT and POPCNT) doesn't even need to be included in a SSE4 in order to be available and used.
05-02-2009, 12:32 AM
Macadamia

So tell me Shintai, please tell us where is the fused multiply add acceleration in Sandy Bridge or AVX?

We're absolutely begging to know, just like the 2010 DX11 GPUs.

Running through SSE5's rectification, it looks like it has everything AVX touted, with extra few features that SSE5 had from the start.
05-02-2009, 12:35 AM
Shintai

Quote:

Originally Posted by informal

Shintai ,there are about ~100 or less new instructions in AVX(new as not being previously supported by intel hw). The rest ,more than 300 legacy SSE instr. are updated for better performance on future hw(and less than 100 from those 300 are widened to 256bits to support those fp vector instructions).

And there is 46 in SSE5. :p:

Quote:

Originally Posted by Macadamia

So tell me Shintai, please tell us where is the fused multiply add acceleration in Sandy Bridge or AVX?

We're absolutely begging to know, just like the 2010 DX11 GPUs.

Running through SSE5's rectification, it looks like it has everything AVX touted, with extra few features that SSE5 had from the start.

Would be easier if you checked my links....
05-02-2009, 12:46 AM
Macadamia

Wow, counting instruction numbers?

I bet most of them are useless compared to a non emulated implementation of FMA (which is what AMD likely has). Which will blow the panties away from any previous FPU.

And please tell all 3 of those developers that their SSE4.1/2 support is really appreciated (Cinebench x64 has K10.5 paring Core, people are avoiding DivX like the plague because x264 has it beat on all fronts, and probably some other noname is wasting their time on this instead kind of really limited support)
05-02-2009, 12:47 AM
informal

Shintai,actually in the pdf link there are 75 new instructions in new SSE extension set by AMD,not 46(your wiki source?).
05-02-2009, 12:58 AM
Shintai

Quote:

Originally Posted by informal

Shintai,actually in the pdf link there are 75 new instructions in new SSE extension set by AMD,not 46(your wiki source?).

You do know some of those are what you call "converted" SSE4? Not AVX style. In that case Intels AVX is ~200....

Where is this superset of AVX? Superset requires SSE5 amount > AVX amount.

SSE5 is more somthing halfway between SSE4 and AVX.

Quote:

Originally Posted by Macadamia

Wow, counting instruction numbers?

I bet most of them are useless compared to a non emulated implementation of FMA (which is what AMD likely has). Which will blow the panties away from any previous FPU.

Last FPU was x87. We only use SIMD in 64bit(Windows).
05-02-2009, 01:15 AM
informal

Having more instructions doesn't mean much if most of them won't be used much(if at all) .AMD weighted in and decided to incorporate some of AVX instructions (probably the most important ones). The big news in spec. is the FMA addition + 4 operand instructions with 256bit vector support .
The AVX will also mean jack(pardon my french :) ) if it is not coded for. We have even SSSE3(16 new instr.) for 3 years now and SSE4.1(47) for 2 years and both of spec. documents much earlier than that and how many applications actually use any of those? :p:

As for the FPU comment,I believe Macadamia was referring to SIMD.
05-02-2009, 01:24 AM
Shintai

Quote:

Originally Posted by informal

Having more instructions doesn't mean much if most of them won't be used much(if at all) .AMD weighted in and decided to incorporate some of AVX instructions (probably the most important ones). The big news in spec. is the FMA addition + 4 operand instructions with 256bit vector support .
The AVX will also mean jack(pardon my french :) ) if it is not coded for. We have even SSSE3(16 new instr.) for 3 years now and SSE4.1(47) for 2 years and both of spec. documents much earlier than that and how many applications actually use any of those? :p:

As for the FPU comment,I believe Macadamia was referring to SIMD.

So now having it doesnt matter now? How is it big news then?

Plus what happens when you compile and use say SSSE3. But lack one instruction because you didnt fully support it in your CPU? Thats right, it doesnt run in that mode. It changes to a former more legacy mode.
If you didnt have full SSE2 support you couldnt run 64bit Windows either.

Alot of applications uses the newest instructions. Just because Crysis or some other popular title doesnt use it. Doesnt mean its not used at all in large amounts. And you will never see it really unless you bench it. Because then you just run it with SSE3 etc instead or so.
05-02-2009, 01:29 AM
informal

What is important is performance. You can have hw support and coded app that can make use of SSSE3(hypothetical ex.) and it makes 3-5% difference... Let's wait and see what comes out from all of this in 2 years.By that time both designs will be well studied and probably we will have hardware on the shelves from both companies.
05-02-2009, 02:00 AM
Smartidiot89

Because AMDs engineerers are stupid and have no clue what so ever what they are doing :rolleyes:
05-02-2009, 03:12 AM
generics_user

great news, hopefullythey'll make it to the market on time

@shintai: please stop your pointless holy crusade against amd and make some useful posts, it's really annoying to have that much space on my screen wasted due to useless destructive posts...
05-02-2009, 08:46 AM
Glow9

So does this mean they will finally be able to be faster than high end Intel Quad core 775's?
05-02-2009, 09:04 AM
Helmore

Not necessarily, although it would be shameful if they weren't by then.
05-02-2009, 09:22 AM
Anemone

Well AMD going out on their own and saying "we're 10% of the market but we're going to do our own instruction set" is just as ridiculous now as it was years ago with 3Dnow. 64 bit was a whole different ballgame and it wasn't till Intel joined that party that you really began to see mainstream 64 bit software. Even now, years later, the move forward is slow on the software side, and 3Dnow is forgotten tech, while SSE is everyday stuff.

It's ok to venture out and do it all by yourself. Just do it in a place that is truly market changing, not on these crazy little spats about extended instructions.
05-02-2009, 09:57 AM
Glow9

Another question are these going to be AM3's or new socket?
05-02-2009, 09:58 AM
ILikeCosmosS

i heard magny four cores was on the g34 socket and it should be a new socket
05-02-2009, 10:18 AM
roofsniper

the new socket. who knows what else will be on am3. maybe the desktop version of instanbul but besides that most of amd's new designs are on the new socket.
05-02-2009, 11:12 AM
Shadowmage

Quote:

Originally Posted by Glow9

So does this mean they will finally be able to be faster than high end Intel Quad core 775's?

According to an AMD engineer that I know, AMD doesn't have a chance to compete with Intel in absolute performance until Bulldozer.
05-02-2009, 11:41 AM
AKM

Quote:

Originally Posted by Shadowmage

According to an AMD engineer that I know, AMD doesn't have a chance to compete with Intel in absolute performance until Bulldozer.

I don't think you need an AMD engineer to tell you that lol
05-02-2009, 11:41 AM
gOJDO

LOL, AMD fans never lose hope...

Do you guys have any clue how these new SSE7, AVY or whatever will improve performance of current and future software?
05-02-2009, 11:50 AM
roofsniper

Quote:

Originally Posted by Shadowmage

According to an AMD engineer that I know, AMD doesn't have a chance to compete with Intel in absolute performance until Bulldozer.

says who? istanbul is coming in a month and it will be a 6 core cpu plus they will make a mcm chip that will be 12 cores just like core 2 is so you could have up to 48 cores on one system. to me i think that alone will compete fairly just because of the abundance of cores. also amd is doing fine on the server side right now they have been doing better than intel there for years.
05-02-2009, 01:32 PM
STaRGaZeR

Quote:

Originally Posted by AKM

I don't think you need an AMD engineer to tell you that lol

LOL indeed.
05-02-2009, 02:50 PM
madcho

Quote:

Originally Posted by roofsniper

says who? istanbul is coming in a month and it will be a 6 core cpu plus they will make a mcm chip that will be 12 cores just like core 2 is so you could have up to 48 cores on one system. to me i think that alone will compete fairly just because of the abundance of cores. also amd is doing fine on the server side right now they have been doing better than intel there for years.

You're right amd is far better on server market.

intel don't have anything good in 4P
05-02-2009, 06:21 PM
Chad Boga

Quote:

Originally Posted by roofsniper

says who? istanbul is coming in a month and it will be a 6 core cpu plus they will make a mcm chip that will be 12 cores just like core 2 is so you could have up to 48 cores on one system. to me i think that alone will compete fairly just because of the abundance of cores.

That will help in the server market but will do nothing for 99% of desktop users.

Quote:

also amd is doing fine on the server side right now they have been doing better than intel there for years.

Another outright distortion.

No professional analyst/observer of the server market(i.e. IDC, Mercury etc) gives AMD a larger share of the server market than Intel.

What you have done at best, is redefine the term "server market" to that tiny niche where AMD does better, but that is not how it works in the real world where terminology is universally accepted so that meaningful Apples to Apples comparions can take place, rather than fanboy worship.
05-02-2009, 07:02 PM
Glow9

Quote:

Originally Posted by Shadowmage

According to an AMD engineer that I know, AMD doesn't have a chance to compete with Intel in absolute performance until Bulldozer.

And thats why I ask cause I'm not gonna hop to AM3 if its gonna go nowhere when I can just pop in a e8400 to tide me over
05-02-2009, 07:40 PM
Macadamia

Quote:

Originally Posted by Chad Boga

That will help in the server market but will do nothing for 99% of desktop users.

That's a really fitting description for Nehalem too. :yepp:
05-02-2009, 08:25 PM
Chad Boga

Quote:

Originally Posted by Macadamia

That's a really fitting description for Nehalem too. :yepp:

No, but it does apply to the 6 core Westmere that is getting here before the higher clocked Westmere Quad.
05-02-2009, 10:49 PM
informal

Agner Fog's comment on this from Ace's hw:

Quote:

Originally Posted by Agner

Thanks for posting the reference to the new AMD manual, indicating that AMD have changed their SSE5 codes for the sake of compatibility with Intel AVX and FMA.

The present situation shows once again that such a committee is desperately needed. Unfortunately this is not gonna happen unless somebody can legally force Intel and AMD to cooperate rather than keeping secrets to each other.

If Intel and AMD had communicated better we wouldn't have this mess now.

The new instruction space that has been opened with Intel's introduction of the VEX coding scheme is HUGE. It has room for all kinds of extensions and new instuctions for many years to come without making instruction codes longer. It would be absolutely no problem to reserve a small part of this new instruction space to AMD so that they could invent new instructions without risking that Intel has something else in their pipeline that happens to use the same code for something else. However, the new spec. of AMD instructions indicates that it has been impossible for AMD to get such an agreement with Intel. Rather than coding their new instructions according to the VEX scheme, they have invented yet another prefix called XOP. The AMD XOP prefix (8F) works in exactly the same way as Intel's VEX prefix (C4). This makes instruction decoding easier than if AMD had sticked to their SSE5 coding scheme. If some of the new instructions invented by AMD happen to be so popular that Intel have to copy them, then Intel can just treat 8F and C4 as equivalent, and the new instruction fits into the VEX scheme. The codes do not overlap, even if 8F and C4 are treated as equivalent. (8F would overlap with POP instructions if used instead of C4 on some Intel instructions).

The blame here is really on Intel. They have changed their specifications for FMA instructions without informing AMD in time. They must have known that AMD had plans about changing their coding scheme to make it compatible with Intel's because there have been patent-clearing negotiations between the two companies about this issue.

Intel should also be blamed for refusing to assign part of the opcode space to AMD, thereby forcing them to invent yet another prefix.

It seems that AMD are the nice guys in this case. They have made great sacrifices by dropping their SSE5/DREX coding scheme and replacing it with Intel's scheme for the sake of compatibility. And then Intel have blown it all by changing their specs once again. Arghhhhh!!!!!!

How long shall we live with this race between Intel and AMD on inventing new instructions and the resulting problems of incompatibility, a bloating and complicated opcode map, and instructions that are rarely used becaused the competitor has invented something better? These obsolete instructions will have to be supported in all future for the sake of compatibility with legacy software.
05-02-2009, 10:57 PM
Brother Esau

I see the Intel Fan Club is in the House and crapping on yet another AMD thread.

When is this crap going to end? Its the same people over and over who could care less of AMD and their Products but yet they continue to come into AMD threads and ruin it every time.

HEY MODS!!! When or should I say Are You going to do anything about this?
05-02-2009, 11:34 PM
GAR

I am hoping amd can make a comeback for the sake of fast cpu's.
05-03-2009, 12:47 AM
ajaidev

[QUOTE=Shintai;3766463]So now having it doesnt matter now How is it big news then

Plus what happens when you compile and use say SSSE3. But lack one instruction because you didnt fully support it in your CPU Thats right, it doesnt run in that mode. It changes to a former more legacy mode.
If you didnt have full SSE2 support you couldnt run 64bit Windows either.

Alot of applications uses the newest instructions. Just because Crysis or some other popular title doesnt use it. Doesnt mean its not used at all in large amounts. And you will never see it really unless you bench it. Because then you just run it with SSE3 etc instead or so.[QUOTE]

I know that AVX is really easy to get along with. You can convert SSE4 Ins. to AVX in a few days instead of a full rewrite but the thing is AVX will be not supported by majority of processors in 2010 Eg Few people have i7 platform in 09. Yes the app will try and use a lower instruction set such as SSE4 but then again AVX is not entirely compatible with SSE4 so you have to double write coding which willadd to the weight of the application,complexity, etc.

In english-

AVX can do C = A+B and D = A+B+C but only if your processor supports AVX otherwise you will have to write more instructions instead like A = A+B ALSO C = A+C... The break down can also be done by the software itself which is slower because it happens in real time.
05-03-2009, 02:34 AM
Chad Boga

Quote:

Originally Posted by informal

Agner Fog's comment on this from Ace's hw:

Paul DeMone's apt response to Agner

Quote:

It is up to the parasite to adapt to changes in its host, not the other
way around.

AMD is free to extend x86 as it wishes, or even better, create an all
new ISA on its own. If it wants a free ride by slip streaming behind
Intel then it has no choice but to follow closely behind. Intel has no
legal or moral obligation at all to assist AMD in competing with it and
IMO anyone who thinks otherwise is a sad product of a society gone
mad with entitlement mentality.
05-03-2009, 03:32 AM
Hornet331

Quote:

Originally Posted by Brother Esau

I see the Intel Fan Club is in the House and crapping on yet another AMD thread.

When is this crap going to end? Its the same people over and over who could care less of AMD and their Products but yet they continue to come into AMD threads and ruin it every time.

HEY MODS!!! When or should I say Are You going to do anything about this?

How is that and amd thread when the titel mentions both?... oh well, seems I forgot the amd fanboy rule #1: AMD in the title means amd exclusiv, even mentioning the name intel is thread crapping...

When you call for mods, how about changing the thread title itself, it's an invitation for flaming... informal could easily have chosen another thread title, but it wouldn't have caused that much of a stir up... :rolleyes: (talk about double standards)
05-03-2009, 03:54 AM
informal

Quote:

Originally Posted by Chad Boga

Paul DeMone's apt response to Agner

Professor Fog is much more into instruction set analysis than Paul ever was or will be. Anyway,Paul will do anything to bash AMD,it is the thing he does.
The fact is the very second AMD made adjustments to SSE5 and made it compatible to AVX back in January,intel changed the spec again and made it incompatible again. This is imo a clear sign of weakness on intel's part since they know that initial avx with no FMA instruction in 1st iteration of SB will be no match for new avx-like AMD instruction set in BD cores in 2011.SO they made it incompatible again by changing the spec on the fly after AMD posted their revised specification.

In the end MS will probably have a say in this matter too.Will be interesting to see how this one turns out.
05-03-2009, 04:01 AM
Chad Boga

Quote:

Originally Posted by informal

Professor Fog is much more into instruction set analysis than Paul ever was or will be.

It is not about analysing instruction sets, it is the ludicrous belief that Intel is honour bound to help out AMD and when they don't(surprise surprise), the irrational come out to criticise them.

Quote:

In the end MS will probably have a say in this matter too.Will be interesting to see how this one turns out.

If they are now both on the same page, what is there to see?

If they are different, then it most likely would be a rerun of SSE vs 3DNow.
05-03-2009, 04:13 AM
informal

Why did you skip the crucial part of the post:

Quote:

The fact is the very second AMD made adjustments to SSE5 and made it compatible to AVX back in January,intel changed the spec again and made it incompatible again. This is imo a clear sign of weakness on intel's part since they know that initial avx with no FMA instruction in 1st iteration of SB will be no match for new avx-like AMD instruction set in BD cores in 2011.SO they made it incompatible again by changing the spec on the fly after AMD posted their revised specification

AMD did follow intel and changed the way decoding was done in the revised spec and (surprise surprise :rolleyes: ) intel changes their avx specification again...Mr Fog just wants the mess with instruction set extensions to be over and a standardization body to be formed.

As for MS,Hans posted that he hopes AMD is just a first to post a MS "inspired" AVX/SSE5 common instr. set extension.
05-03-2009, 04:44 AM
Chad Boga

Quote:

Originally Posted by informal

Why did you skip the crucial part of the post:

Because it wasn't crucial and was irrelevant to rational thought.

Quote:

AMD did follow intel and changed the way decoding was done in the revised spec and (surprise surprise :rolleyes: ) intel changes their avx specification again...Mr Fog just wants the mess with instruction set extensions to be over and a standardization body to be formed.

Well Mr.Fog is just going to have to accept that Intel has the right to improve their product line and that they are not under an obligation to give a helping hand to their rival.

You should accept that too.

Quote:

As for MS,Hans posted that he hopes AMD is just a first to post a MS "inspired" AVX/SSE5 common instr. set extension.

I hope he is right, I just doubt that he is.
05-03-2009, 04:54 AM
Shintai

MS got nothing to say with AVX. And the reason is 95% of all companies, including Microsoft uses Intel compilers.
05-03-2009, 06:48 AM
Vozer

Thou shalt NOT talk about Intel. :censored: :p:
05-03-2009, 09:47 AM
informal

Quote:

Originally Posted by Chad Boga

Because it wasn't crucial and was irrelevant to rational thought.

Lol "wasn't crucial and was irrelevant to rational thought"? :p: What kind of an answer is that??

Maybe irrelevant to you or intel fans,but to anyone objective enough it's clear what intel did and it's lame .They can keep revising the spec anytime AMD matches or exceeds them in engineering with much less resources,but hey it's the world we live in :shrug:
05-03-2009, 10:28 AM
ajaidev

Quote:

Originally Posted by Shintai

MS got nothing to say with AVX. And the reason is 95% of all companies, including Microsoft uses Intel compilers.

Not true at least the MS part. MS use both intel and amd for 32bit and only amd for 64bit. This was after AMD sued INTEL back in 05. The compilers are checked and bisected by both Intel and Amd to make sure that everything is in order.

http://www.betanews.com/article/Suit...AMD/1121274628

http://techreport.com/discussions.x/8547
05-03-2009, 10:35 AM
STaRGaZeR

Shintai is a true guru of compilers, 32/64-bit and similar :rolleyes:

Not.
05-03-2009, 11:45 AM
hurleybird

Quote:

Originally Posted by Chad Boga

Well Mr.Fog is just going to have to accept that Intel has the right to improve their product line and that they are not under an obligation to give a helping hand to their rival.

:rolleyes::rofl:

Your comparison is beyond idiotic. How does changing their coding scheme for the sole purpose of keeping it incompatible with AMD's "improve their product line"? How is it that you think the mere act of not doing something hurtful (both to AMD and the market in general) is akin to "giving a helping hand". And you're the one criticizing other's posts of being "irrelevant to rational thought"? I'm sorry for advancing the "argument", but this poor thought and blatant fanboyism really needs to get called out.
05-03-2009, 11:54 AM
Zucker2k

Quote:

Originally Posted by hurleybird

:rolleyes::rofl:

Your comparison is beyond idiotic. How does changing their coding scheme for the sole purpose of keeping it incompatible with AMD's "improve their product line"? How is it that you think the mere act of not doing something hurtful (both to AMD and the market in general) is akin to "giving a helping hand". And you're the one criticizing other's posts of being "irrelevant to rational thought"? I'm sorry for advancing the "argument", but this poor thought and blatant fanboyism really needs to get called out.

I want to see a screenie or it didn't happen. In other words, where's the evidence? I see a lot of people linking to nothing but speculation. Maybe this forum needs a rule that links should also reference facts; that should help with toning down the hostility in here. Too much bs and not enough facts. Unfortunately, the thread itself is based on same - speculation.
05-03-2009, 12:03 PM
informal

Quote:

Originally Posted by Zucker2k

I want to see a screenie or it didn't happen. In other words, where's the evidence? I see a lot of people linking to nothing but speculation. Maybe this forum needs a rule that links should also reference facts; that should help with toning down the hostility in here. Too much bs and not enough facts. Unfortunately, the thread itself is based on same - speculation.

Prof. Agner Fog made a topic at ace's hw which is still active.AMD embraced intel's AVX decoding scheme (at least the one that was valid back in Jan.) and intel recently changed it, again,thus making AMD's now revised SSE5-AVX incompatible- again :rolleyes:

Quote:

Quote:

Originally Posted by Mr. Agner Fog

The blame here is really on Intel. They have changed their specifications for FMA instructions without informing AMD in time. They must have known that AMD had plans about changing their coding scheme to make it compatible with Intel's because there have been patent-clearing negotiations between the two companies about this issue.

It seems that AMD are the nice guys in this case. They have made great sacrifices by dropping their SSE5/DREX coding scheme and replacing it with Intel's scheme for the sake of compatibility. And then Intel have blown it all by changing their specs once again. Arghhhhh!!!!!!
05-03-2009, 12:21 PM
Zucker2k

Quote:

Originally Posted by informal

Prof. Agner Fog made a topic at ace's hw which is still active.AMD embraced intel's AVX decoding scheme (at least the one that was valid back in Jan.) and intel recently changed it, again,thus making AMD's now revised SSE5-AVX incompatible- again :rolleyes:

Quote:

Ok, let's see:

Originally Posted by Mr. Agner Fog
The blame here is really on Intel. They have changed their specifications for FMA instructions without informing AMD in time. They must have known that AMD had plans about changing their coding scheme to make it compatible with Intel's because there have been patent-clearing negotiations between the two companies about this issue.

It seems that AMD are the nice guys in this case. They have made great sacrifices by dropping their SSE5/DREX coding scheme and replacing it with Intel's scheme for the sake of compatibility. And then Intel have blown it all by changing their specs once again. Arghhhhh!!!!!!I haven't even bothered to read the link but those patches of it posted are enough. The last bolded word is indicative of a tortured reaction from a partisan, and not an objective presentation of a formal scholarly paper. The speculative language alone makes that point moot.
05-03-2009, 12:31 PM
informal

Mr. Fog is a well respected member of the community and I may say he is a man that respects intel tremendously.I guess you said he was "a partisan who had a tortured reaction" is because you don't know much (if anything) about him... The fact you are not aware what he did for software community with his great optimization guides ,especially for intel hardware, makes your post a bit less harsh. Next time inform better before talking crap about other people.
05-03-2009, 02:41 PM
Chad Boga

Quote:

Originally Posted by hurleybird

Your comparison is beyond idiotic.

I would say that description better fits your understanding of the issues at hand here.

Quote:

How does changing their coding scheme for the sole purpose of keeping it incompatible with AMD's "improve their product line"? How is it that you think the mere act of not doing something hurtful (both to AMD and the market in general) is akin to "giving a helping hand". And you're the one criticizing other's posts of being "irrelevant to rational thought"? I'm sorry for advancing the "argument", but this poor thought and blatant fanboyism really needs to get called out.

Where is your evidence that Intel only made changes to create incompatibility with and for AMD?

Where is your evidence that the changes Intel made didn't improve the utility of the instructions they are seeking to implement?

Unless you can prove either, the rational default assumption is that Intel made the changes to make their instruction set better.
05-03-2009, 02:51 PM
Chad Boga

Quote:

Originally Posted by informal

Lol "wasn't crucial and was irrelevant to rational thought"? :p: What kind of an answer is that??

Maybe irrelevant to you or intel fans,but to anyone objective enough it's clear what intel did and it's lame .They can keep revising the spec anytime AMD matches or exceeds them in engineering with much less resources,but hey it's the world we live in :shrug:

So despite you having no proof that Intel made the changes just to stuff up AMD, you will pursue that line of "thought" anyway.

Despite having no evidence that the changes that Intel made to their extension are not an improvement to them, you will still spread the "Intel is Satan" FUD.

As Paul DeMone alluded to, entitlement mentality gone mad.
05-03-2009, 03:31 PM
hurleybird

Quote:

Originally Posted by Chad Boga

Unless you can prove either, the rational default assumption is that Intel made the changes to make their instruction set better.

Really? And why would the rational default assumption be to side with Intel? Claiming your opinions are rational without describing your reasoning doesn't make you rational -- quite the opposite in fact. Given the fact that Intel has done this sort of thing before, where their compilers would disable SSE instructions in non-Intel processors regardless of ability (prior history), and that Intel will be lacking FMA instructions in the original AVX implementation (motive), and the timing of the entire fiasco, I don't see why the "default rational assumption" should be that everything is one giant coincidence.
05-03-2009, 06:41 PM
informal

Chad ,Mr Fog writes optimization manuals for intel hardware,I think he knows "a bit better" how things stand in AVX land than you do :rolleyes: . Not only him,but several Ace's members stated the new specification was released just in time to beat AMD's release of their new instruction set extension . And AMD did change their drex decoding scheme just to embrace the previous VEX decoding that was the basis of previous AVX revision.

It amazes me how far will you go in intel's defense. Are you their lawyer, spokesperson or what? :p:

EDIT:
I have found the original and revised AVX specs.
Original is here. It was valid until January 2009. Intel released a new specification 4 months ago(roughly) and here is the new pdf covering the revised AVX instr. set specification. I'm not aware if there are more revisions,maybe there are.

Also note that intel has stated that they won't have FMA(the crucial instruction update) in Sandy Bridge while AMD on the other hand had FMA even in their first SSE5 extension set! This means SB will lack one of the strong features BD will have.
05-03-2009, 08:10 PM
Bo_Fox

All right, at least that is a good thing, as it shows that AMD is serious about keeping up with Intel (if not actually beating Intel)...
05-03-2009, 09:04 PM
kl0012

Quote:

Originally Posted by informal

Chad ,Mr Fog writes optimization manuals for intel hardware,I think he knows "a bit better" how things stand in AVX land than you do :rolleyes: . Not only him,but several Ace's members stated the new specification was released just in time to beat AMD's release of their new instruction set extension . And AMD did change their drex decoding scheme just to embrace the previous VEX decoding that was the basis of previous AVX revision.

It amazes me how far will you go in intel's defense. Are you their lawyer, spokesperson or what? :p:

EDIT:
I have found the original and revised AVX specs.
Original is here. It was valid until January 2009. Intel released a new specification 4 months ago(roughly) and here is the new pdf covering the revised AVX instr. set specification. I'm not aware if there are more revisions,maybe there are.

Also note that intel has stated that they won't have FMA(the crucial instruction update) in Sandy Bridge while AMD on the other hand had FMA even in their first SSE5 extension set! This means SB will lack one of the strong features BD will have.

1. It is really doesn't mather why & when Intel changed his spec for FMA instructions - AMD's decoding scheme is similar but isn't compatable to Intel's decoding scheme. Intel's AVX extends many of SSE2/3/4 instructions to 256bit 3-operands mode and that feature is missing from AMD's new instruction set.

2. Changes made by Intel to FMA instructions (4-operand => 3 operand) nothing more then simplifying CPU hardware. If AMD can implement 4-operand instructions then it is very easy to convert such instructions to 3-operand (it is supported by default).
05-03-2009, 09:36 PM
Chad Boga

Quote:

Originally Posted by informal

Chad ,Mr Fog writes optimization manuals for intel hardware,I think he knows "a bit better" how things stand in AVX land than you do :rolleyes:

He is someone who wants uniformity above all, thus his calls for a committee to oversee future x86 advancements.

Intel is concerned about making their products better and not worried about giving a helping hand to their rival(s).

You guys can hold hands and sing Kumbai Yah all day long, but that is not how the companies competing against each other operate and it is immature and out of touch with reality to not be cognisant of this.

Quote:

Not only him,but several Ace's members stated the new specification was released just in time to beat AMD's release of their new instruction set extension.

Who gives a F#@% what several member's of Ace's stated, what a compelling argument. :ROTF::ROTF::ROTF:

Quote:

Also note that intel has stated that they won't have FMA(the crucial instruction update) in Sandy Bridge while AMD on the other hand had FMA even in their first SSE5 extension set! This means SB will lack one of the strong features BD will have.

So if Intel are simply lacking a feature that AMD have, then the possibility exists that someone could code software that runs on AMD CPU's but not Intel CPU's, whilst all software coded for Intel would run on AMD.

That can only be in AMD's favour.
05-03-2009, 09:42 PM
informal

It's only *one*(FMA) of the features intel will lack. The other is 4 operand(AMD) vs 3 operand(new intel spec,not the old one for mJanuary) instructions and it also brakes the compatibility.

I guess intel can keep on making changes until Ivy Bridge comes :rolleyes: And I doubt AMD will make another change just to follow intel's suit. The point in this whole thing is to have a common instruction set extensions for both vendors so the software(and consumers in the end!) can benefit from it. Just pointlessly adding instructions that nobody will use and making new extension set revisions in order to break compatibility with other vendor is bad for all of us consumers(forget about intel and amd as companies,it is us who will get less value for the money if apps won't work on our new hardware or will work slower than what hardware could actually do).

PS I guess you have no comment on the proof you requested and I delivered(about revised avx spec)? :p:

Quote:

Originally Posted by Chad Boga

So despite you having no proof that Intel made the changes just to stuff up AMD, you will pursue that line of "thought" anyway.

Despite having no evidence that the changes that Intel made to their extension are not an improvement to them, you will still spread the "Intel is Satan" FUD.

As Paul DeMone alluded to, entitlement mentality gone mad.

Something went *mad* alright :p:
05-03-2009, 09:54 PM
Chad Boga

Quote:

Originally Posted by informal

PS I guess you have no comment on the proof you requested and I delivered(about revised avx spec)? :p:

How is that proof that Intel only did it to stuff up AMD and not because it made more sense for their product?

That it stuffs AMD around is no doubt true, but that doesn't prove that is why the changes were made.
05-03-2009, 10:03 PM
informal

And what proof do you have it made more sense for their product?? They already said that FMA won't be in SB,even in the first revision of the AVX they published in 2008.So this means that the original and revised spec wouldn't affect SB design product cycle. The 4/3 operand instruction change bricks the compatibility even though these 2 companies were in continuous talks over patent agreement on avx specification and amd's implementation of it in their revised SSE5.So basically AMD will have to follow intel's suit and change the specs even though AMD has no time to waste since the specs WILL affect BD cores in less then 2 years from now.I guess AMD will not do such a thing since they just can't afford to mess ,again, with SSE extensions so close(relatively speaking)to their next major and probably most important uarchitecture launch.

There is a chance as Hans said,that AMD could be the first to publish the revised and now common extension set,but I wouldn't hold my breath.
05-03-2009, 11:41 PM
gumballguy

Whos up for closing this thread?

I think we can all agree on a couple of basics:
1) By the definition of the word superset, it's not a superset
2) We'd all like AMD's instructions to give a performance boost
3) Intel's timing is questionable, but we're not the jury, and lots of these posts are angry/uninformed/both

That said, close close close!

It seems half my posts these days are begging for thread closure. Maybe we need a new website, www.xtremerant.com ;) j/k
05-04-2009, 12:24 AM
Nedjo

Quote:

Originally Posted by Shintai

MS got nothing to say with AVX. And the reason is 95% of all companies, including Microsoft uses Intel compilers.

absolutely wrong! MS has it's own complier and their compiler +gcc is the most used compliers around, not ICC! That doesn't downplays power of ICC that's extremely efficient complier and extremely optimized for Intel's architecture, and biasedly unoptimized towards AMD's approach to x86 set...
05-04-2009, 12:26 AM
Nedjo

Quote:

Originally Posted by Chad Boga

Paul DeMone's apt response to Agner

pfff Paul DeMone = Shintai^3 :rolleyes:
05-04-2009, 12:28 AM
Shintai

Quote:

Originally Posted by Nedjo

pfff Paul DeMone = Shintai^3 :rolleyes:

Angry fanboy getting personal? The anger is intense in this thread. I guess when you cant get the ball you have to go for the person :rolleyes:
05-04-2009, 12:35 AM
Nedjo

Quote:

Originally Posted by Shintai

Angry fanboy getting personal? The anger is intense in this thread. I guess when you cant get the ball you have to go for the person :rolleyes:

dude why do you find yourself offended by comparison with a guy who's most prominent person in community?
05-04-2009, 12:35 AM
Chad Boga

Quote:

Originally Posted by Nedjo

pfff Paul DeMone = Shintai^3 :rolleyes:

Shintai is pretty knowledgeable, so that sounds about right. :up:
05-04-2009, 12:42 AM
Shintai

Quote:

Originally Posted by Nedjo

absolutely wrong! MS has it's own complier and their compiler +gcc is the most used compliers around, not ICC! That doesn't downplays power of ICC that's extremely efficient complier and extremely optimized for Intel's architecture, and biasedly unoptimized towards AMD's approach to x86 set...

Just a shame that code runs faster also on AMD after using the Intel compiler. And if we exclude the basement people and just check companies. the 95% is pretty spot on. And no, MS does not use its own compiler. MS just sells it with VS and use it for any prototype testing. MS dont like subpair performance on its own products. if it can avoid it ;)
05-04-2009, 12:53 AM
Nedjo

Quote:

Originally Posted by Shintai

Just a shame that code runs faster also on AMD after using the Intel compiler. And if we exclude the basement people and just check companies. the 95% is pretty spot on. And no, MS does not use its own compiler. MS just sells it with VS and use it for any prototype testing. MS dont like subpair performance on its own products. if it can avoid it ;)

I guess there are no reason for so many games and apps/drivers to deploy with VC++ 2005/2008 runtime...
05-04-2009, 12:54 AM
gOJDO

Quote:

Originally Posted by Nedjo

absolutely wrong! MS has it's own complier and their compiler +gcc is the most used compliers around, not ICC!

Can you support this claim with some statistics data?

Quote:

That doesn't downplays power of ICC that's extremely efficient complier and extremely optimized for Intel's architecture, and biasedly unoptimized towards AMD's approach to x86 set...

I call BS on the bolded part. ICC is faster than MSC even with AMD CPUs.
05-04-2009, 12:59 AM
Shintai

Quote:

Originally Posted by Nedjo

I guess there are no reason for so many games and apps/drivers to deploy with VC++ 2005/2008 runtime...

Are you claiming the runtime DLLs is a MS compiler requirement? Do you know what a compiler even is?
05-04-2009, 02:15 AM
STaRGaZeR

Quote:

Originally Posted by Shintai

Do you know what a compiler even is?

Dunno about him, but you sure don't :ROTF:
05-04-2009, 02:29 AM
Shintai

Quote:

Originally Posted by STaRGaZeR

Dunno about him, but you sure don't :ROTF:

Next you gonna claim that a function API library dependency is the same as a compiler. :ROTF:

You are always ready to make a joke :D
05-04-2009, 03:25 AM
Hornet331

Quote:

Originally Posted by informal

EDIT:
I have found the original and revised AVX specs.
Original is here. It was valid until January 2009. Intel released a new specification 4 months ago(roughly) and here is the new pdf covering the revised AVX instr. set specification. I'm not aware if there are more revisions,maybe there are.

wow.. just wow, im really baffled. So you claim intel intel just released the next revision of AVX to hamper AMD?

With your own links you have proven, that AVX is far from finished if they already have gone throught 2 (ore more) revisions in less then 1 year, and im sure there are going to be a few more before we finally see it in hardware.

AMD should stop weeping and show some guts again, as they did with AMD64. :yepp:
If amd already has a instruction set ready with FMA, they should release it, cause 2 years is a long time to catch up for intel, might be even eough to pull another AMD64 and intel has to adapet amds solution.
05-04-2009, 05:28 AM
BrowncoatGR

Quote:

Originally Posted by Hornet331

snip

With sandy bridge due in 2010 the spec for AVX really has to be finished. :welcome:
In any case i dont care if Intel has the right to change the spec. The only thing that i care about is how this affects me as a consumer and the implementations by AMD and Intel being incompatible is only going to slow down adoption of these features in mainstream applications. So :down: for Intel
05-04-2009, 06:43 AM
kl0012

Quote:

Originally Posted by BrowncoatGR

With sandy bridge due in 2010 the spec for AVX really has to be finished. :welcome:

The spec changes were related only to FMA which will be introduced in Ivy Bridge.

Quote:

In any case i dont care if Intel has the right to change the spec.

AMD changed several times it's spec for x86-64 (even right before Intel released it's first P4 supported x86-64). Applause to Intel for not introducing it's own spec for 64 bit. :clap: :D
05-04-2009, 07:11 AM
Donnie27

Quote:

Originally Posted by kl0012

The spec changes were related only to FMA which will be introduced in Ivy Bridge.

AMD changed several times it's spec for x86-64 (even right before Intel released it's first P4 supported x86-64). Applause to Intel for not introducing it's own spec for 64 bit. :clap: :D

Yep! There were several threads about Intel stealing from AMD and a corrected glitch of was proof:up:

But Intel did introduce their own 64bit, it just wasn't a Hybrid X86-64.
05-06-2009, 12:57 PM
informal

AMD's official stance on AVX/SSE5 and changes in specs

Links of interest:
http://forums.amd.com/devblog/
http://blogs.amd.com/nigeldessau/200...-than-fiction/

Quote:

Originally Posted by N.Dessau

There is a commonly held fallacy that there is one single x86 instruction set. In reality, while all x86 chips run about 99% similar instructions, no two suppliers run exactly the same base. We have a different set to Intel, which is a different set to Via and so on. In fact, one of the things that differentiates our server line from Intel’s is that they don’t even have the same set of functions across the Nehalem line - where as we run all the same functions on the entire family of Quad-Core AMD OpteronTM processors.

This is one of the reasons why AMD Opteron processor-based servers make such good disaster recover solutions - you really can failover running virtual machines to newer, smaller standby systems without worrying that some of the processor functions may not be supported.

While the AMD Opteron processor retains backward compatibility, it is fair to point out that as we deliver new function at each generation, we often have to add extensions to the x86 instruction set (examples are virtualization and 64-bit extensions).

Changing the instruction set can be both complex and expensive for application developers and painful for system designers. AMD recognizes this, and we are trying to reduce some of this cost and complexity by helping to unify the x86 instruction set with the adoption of the Advanced Vector Extensions (AVX).

AMD has always been a champion of open and industry standards, and by adopting the AVX instructions for x86 processors initially announced by Intel in 2008, we can help move this ideal forward. We believe that by proposing and embracing enhancements to the instruction set, AMD provides software developers with a great step towards a more standard platform for innovation.

Now, originally we had focused on what we had called SSE5, a specification we proposed for review by the industry in 2007. However, due to the overlap of functionality between the AVX instructions and SSE5, AMD has decided to recast the SSE5 instructions into the AVX framework. AMD made decision to ensure the continued compatibility of x86 software, and plans to incorporate AVX instructions into AMD processors in 2011.

And, still, we want to continue to advance the ball. In addition to embracing the AVX specification, AMD is proposing further enhancement to the current version of this specification called eXtended Operations (XOP). Given there are features of the SSE5 specification that were positively reviewed in the news and not in the current version of AVX, we have incorporated them into the new proposal. Examples of the functionality include:

* Supporting Enhanced Vectorization
* Accelerating traditional DSP Multi-Media algorithms
* Accelerating floating point algorithms for High Performance Computing

If you want to review the AVX or XOP, AMD is posting theses specification here. I also encourage you to go read a blog written by Dave Christie, a Fellow in our Design Engineering team, to get more insight into the technical details and read what some of our technology partners have to say about this change.

You know, when I hear people cry, “Do not fork the x86 instruction set!” what I really hear is people saying, “Give up driving instruction set innovations!”

Well, there are two reasons why this won’t happen:

* Innovation ‘R US. We believe that bringing innovation to the market is one of our key values and we plan to continue to do what we can to bring users systems that better serve their needs
* There really isn’t a single static x86 instruction set and we need as an industry to make evolution of this instruction set. That’s why we publish changes we are proposing for discussion (and haven’t done it in secret). Our users and the application developers may have good ideas too.

The x86 instruction set will continue to evolve and change and wouldn’t it be great if we could do it together?

Nigel Dessau is senior vice president and chief marketing officer at AMD. His postings are his own opinions and may not represent AMD’s positions, strategies or opinions. Links to third party sites are provided for convenience and unless explicitly stated, AMD is not responsible for the contents of such links sites and no endorsement is implied.

Quote:

Originally Posted by Dave Christie,senior architect

Since we don't control the definition of AVX, all we can say for sure is that we expect our initial products to be compatible with version 5 of the specification (the most recent one, as of this writing, published in January of 2009), except for the FMA instructions, which we expect will be compatible with version 3 (published in August of 2008).

Why the FMA difference? This was not something we did lightly. In December of 2008, Intel made significant changes to the FMA definition, which we found we could not accommodate without unacceptable risk to our product schedules. Yet we did not want to deprive customers of the significant performance benefits of FMA. So we decided to stick with the earlier definition, renaming it FMA4 (for four-operand FMA - Intel's newer definition uses what we believe to be a less capable three-operand, destructive-destination format). It will have a different CPUID feature flag from Intel's FMA extension. At some future point, we will likely adopt Intel's newer FMA definition as well, coexisting with FMA4. But as you might imagine, we may wait until we're sure the specification is stable.
05-06-2009, 01:12 PM
Shintai

*cough* marketing tool *cough*
05-06-2009, 01:23 PM
v_rr

AMD to support Intel's AVX instruction set
http://techreport.com/discussions.x/16871
05-06-2009, 01:51 PM
informal

Well this blog post from Mr. Dave Christie is really shedding more light into the whole SSE5/AVX confusion.

A few key points we can get from reading his post(and these do make my topic title vaild,ie. it IS a SUPERSET since AMD will support BOTH AVX and their own XOP extensions!):

1) AMD will support AVX instr. set extension while adding its OWN extension set named XOP.CVT16 and FMA4.

Quote from Mr. Christie's post :

Quote:

This week, AMD is making a couple of very important announcements for developers: support of Intel's Advanced Vector Extensions (AVX) instruction set in future AMD processors, and the adaptation to the AVX framework of AMD's previous SSE5 instruction set proposal. The latter step has resulted in three new extensions: XOP (for eXtended Operations), CVT16 (half-precision floating point converts), and FMA4 (four-operand Fused Multiply/Add). In this posting I'll give an overview of the capabilities that these extensions provide, and also some insight into why we're taking this step.

Quote:

With this duplication of functionality between SSE5 and AVX/FMA, and AVX's additional features, [B]we felt the right thing to do was to support AVX.[/B] In our minds, a more unified instruction set is clearly what's best for developers and the x86 software industry. With our acceptance of AVX, a key aspect of this instruction set unification is the stability of the specification. Since we don't control the definition of AVX, all we can say for sure is that we expect our initial products to be compatible with version 5 of the specification (the most recent one, as of this writing, published in January of 2009), except for the FMA instructions, which we expect will be compatible with version 3 (published in August of 2008).

FMA differences:

Quote:

Why the FMA difference? This was not something we did lightly. In December of 2008, Intel made significant changes to the FMA definition, which we found we could not accommodate without unacceptable risk to our product schedules. Yet we did not want to deprive customers of the significant performance benefits of FMA. So we decided to stick with the earlier definition, renaming it FMA4 (for four-operand FMA - Intel's newer definition uses what we believe to be a less capable three-operand, destructive-destination format). It will have a different CPUID feature flag from Intel's FMA extension. At some future point, we will likely adopt Intel's newer FMA definition as well, coexisting with FMA4. But as you might imagine, we may wait until we're sure the specification is stable.

Additional value through added previous SSE5 instructions into the AVX spec. thus giving BD cores some more functionality:

Quote:

The fact remains that AVX does not incorporate all of SSE5's features. Since SSE5 was based on months of discussions with ISVs on what sort of capabilities they felt were needed, and had been positively reviewed by the industry when we first put out the specification, we decided to follow through with development of these additional features. To do so most effectively, we redefined them in the AVX framework, resulting in the XOP extension.

2) as a natural consequence of 1)-full AVX support ,AMD must support 256bit wide SSE2/3/4.. instruction set extensions too. This means BD cores will have a superset of full AVX inst. set extensions PLUS an AVX-adopted (previous SSE5) XOP,CVT16 and FMA4 extension sets!

This is very important bit of news. The blog post by senior architect tells us that AMD is embracing the AVX spec. AND incorporating their new SSE5 additional instructions into the AVX-like decoding scheme.The only difference is the FMA extensions which Sandy Bridge will lack anyway and BD cores can't change since it would significantly alter the time to market of AMD's future new gen. uarchitecture.

So Superset stays and was 100% on the money :rofl::ROTF:

EDIT:

A few comments from AMD's industry partners that emphasize the importance of AVX support and of a new superset that AMD created:

Quote:

Absoft
"The addition of AVX support by AMD is a great move as it enables superior performance potential across AMD's x86 family of processors," said Wood Lotz, Absoft CEO. "AMD's use of AVX can also simplify development of high performance compilers and tools for companies like Absoft, and enable customers across a wide variety of industries to build faster applications."

Acumem
"Acumem fully supports AMD's adoption and enhancement of the AVX instructions and will follow this standard as it becomes available in the market. As an ISV for performance tools we clearly see potential for performance improvements with these new additions" said Mats Nilsson, VP Software Engineering at Acumem.

Axceleon
"Axceleon applauds AMDs efforts to support both specifications, AVX and SSE5, in their XOP specification proposal. The further enhancements in FMA4 which accelerate floating point algorithms are very important to Axceleon's HPC customers and will be welcomed across the board" said Mike Duffy, CEO of Axceleon.

Bibble Labs
"We at Bibble Labs are constantly looking for performance improvements, and as such we are investigating AVX because of the possible performance advantage it might bring. We also appreciate that AMD is taking an active role to ensure the instruction sets converge and not create separate, conflicting instruction sets," said Jeff Stephens, Vice President of Product Development, Bibble Labs.

Cakewalk
"We commend AMD for taking an active role in open standards, by unifying the x86 instruction set and merging SSE5 into the AVX specification. This can help improve compatibility and simplify the work for developers implementing this. We look forward to investigating AVX for potential advantages it may bring to our real-time applications and plug-ins," said Noel Borthwick, Chief Technology Officer, Cakewalk.

Nero
"We are pleased that AMD has decided to adopt the AVX instruction set extension instead of offering a variant," said Simone Hoefer, General Manager, Technology at Nero AG. "This will help reduce implementation complexity and multiple code-paths. We are confident that the SIMD (SSE/SSE2) optimizations already implemented will scale nicely to 256-bit/AVX, allowing us to truly embrace this new development."

Smith Micro Software
"Having to choose acceleration solutions that work well on both AMD and Intel CPU platforms, Smith Micro welcomes convergence of the x86 instruction set. AMD supporting AVX is desirable from Smith Micro's point of view," said Uli Klumpp, director of engineering, Smith Micro Software, Inc. "The AVX instruction set extensions are looking promising for further optimizing our computationally most demanding software, DCC and data compression products such as Poser and StuffIt."

Sonic Solutions
"AMD's adoption of AVX will help Sonic unify some of its engineering efforts and reduce development costs," said Jim Roth, Chief Technical Officer, Sonic Solutions. "We welcome this initiative and the proposed enhancements to the x86 processor architecture, which we will leverage to increase the responsiveness and performance of our digital media applications."
05-06-2009, 03:51 PM
v_rr

Wasn't AMD going to create a new extension to X86 with purpose of the Fusion?
Like new instructions that run on GPU.
05-06-2009, 09:30 PM
informal

So Shintai what's your comment on this new development? :p: What happened with your "superset busting"?:shrug:
05-06-2009, 09:52 PM
Trunks

Quote:

Originally Posted by informal

So Shintai what's your comment on this new development? :p: What happened with your "superset busting"?:shrug:

Quote:

Originally Posted by Shintai

*cough* marketing tool *cough*

there you go :)
05-06-2009, 09:56 PM
informal

Never mind his comment has not addressed the issue at all ... And issue being AVX + SSE5(changed sse5) support in BD cores in 2 years.
05-06-2009, 10:48 PM
Macadamia

LOL, UBER PWNAGE. Thanks to AMD for the big clarification.

I already mentioned prior that SSE5 was a superset in general due to its implementation of FMA, but several specs did not adhere. Now add AMD being fully compliant with AVX to the previous setting, it still has FMA inside the CPU spec itself.

So AMD beats Intel to releasing their first SSE5AVX CPU? Whoa.

Quote:

Originally Posted by Shintai

*cough* marketing tool *cough*

What an apt description of... you? :ROTF:
05-06-2009, 10:57 PM
informal

We can coin a new expression on the XS,a small joke if you like : "pulling a sh... on someone" :D -meaning you ignore the facts and stay out of the threads in which you ended up wrong and hoping the thread dies and your pwng is forgotten :D :p:
05-06-2009, 11:15 PM
Brother Esau

Quote:

Originally Posted by Hornet331

How is that and amd thread when the titel mentions both?... oh well, seems I forgot the amd fanboy rule #1: AMD in the title means amd exclusiv, even mentioning the name intel is thread crapping...

When you call for mods, how about changing the thread title itself, it's an invitation for flaming... informal could easily have chosen another thread title, but it wouldn't have caused that much of a stir up... :rolleyes: (talk about double standards)

You know I get a little sick of this Bull :banana::banana::banana::banana: childish name calling and labeling that you troublemakers are oh so fond of! I see all of you with the Balls to call everybody else Fan Boys because it does not coincide with you line of think or your preference ....well tough :banana::banana::banana::banana:!

The fact all of you that are continuously spouting AMD Fan Boy .. AMD Fan Boy only goes to prove one thing that its Intel or the Highway and we are just commoners and beneath all of you because we prefer AMD ......Get Real and Grow Up :rolleyes: How is that you are not a Fan Boy and all of the other chumps that come into these AMD Threads and Purposely Derail them?:rolleyes:.....Once again...OK:rofl:

Speaking of Intel who do you have to thank for your Insight into Overclocking a CPU with a IMC ??? You guessed it the AMD Fan Boys that you all kick ond torment relentlessly ...You guys make me laugh! Self Proclaimed experts talking a Bunch of :banana::banana::banana::banana: is all you do when we were the Ones Debugging Overclocking Quad Core with IMC you were all Talking :banana::banana::banana::banana: and Making Fun of us ..... I guarantee you that for you die Hard Intel Fans here you would know nothing about not blowing up your Precious Nehalem Rigs if it wasn't for us doing all of the work for the Past Year and a Half ya'll wouldn't have a clue in hell and there sure as hell would have been allot of Toasted CPU'S and Motherboards if it weren't for all of us lowly Commoners in the AMD Sector.

Do me a favor all of you shut up and be thankful for what we have given you we are all tired of hearing your Whiny Frigging Negative dysfunctional Rhetoric so piss off or be civil and have some damn manners and respect towards your fellow man.

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