AMD talks up its first Fusion chip

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CHIP DESIGNER AMD has been talking up some of the x86 design features for its first Fusion processor at the International Solid State Circuits Conference (ISSCC) in San Francisco this week.

The upcoming 'Llano' Accelerated Processing Unit (APU) will see the joining of a 32nm silicon-on-insulator (SoI) Phenom II quad core CPU with a DirectX 11 capable GPU on the same die. This is a more sophisticated approach than Intel's at present, in which it simply adds a GPU chip to the processor package and calls that 'integrated'.

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http://www.theinquirer.net/inquirer/...ks-fusion-chip

http://www.eetimes.com/news/latest/s...2700324&pgno=2


:shocked::shocked::shocked:

Oh dear, and again we see the monolithic bs card in game....

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Originally Posted by Hornet331

Oh dear, and again we see the monolithic bs card in game....

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Who cares about monolithic versus 2 separate dies? It's performance per watt that matters. I don't care how any company gets there. :up:

It seems that whenever Intel has no competition, it becomes complacent. AMD seems to be far more innovative than Intel lately, even if its performance isn't as high end.

The Llano's RV8xx DX11 part with 400+ stream processors will simply be in its own league when it comes to performance... Add in the hybrid CF capability with discrete cards and I can't see what kind of redesign the current Intel GMA series need to receive to be even closely competitive with Llano's GPU when Intel integrates them into SB cores.

Quote:

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Originally Posted by informal

The Llano's RV8xx DX11 part with 400+ stream processors will simply be in its own league when it comes to performance... Add in the hybrid CF capability with discrete cards and I can't see what kind of redesign the current Intel GMA series need to receive to be even closely competitive with Llano's GPU when Intel integrates them into SB cores.

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This will rock if the driver support is decent...
And hope OCing will be just as good as for Intel chips, too! :up:

Quote:

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Originally Posted by Hornet331

Oh dear, and again we see the monolithic bs card in game....

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?:confused::rolleyes: (i love these emoticons)

if being monolithic is bad, then why did intel not stay with a glued dual core = quad core thing? only time will tell if SB will have a better approach than llano. in the end; intel went the monolithic route soo....idk.

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Originally Posted by freeloader

Who cares about monolithic versus 2 separate dies? It's performance per watt that matters. I don't care how any company gets there. :up:

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exactly this, it doesn't matter if its one die or not. :up:

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Originally Posted by god_43

?:confused::rolleyes: (i love these emoticons)

if being monolithic is bad, then why did intel not stay with a glued dual core = quad core thing? only time will tell if SB will have a better approach than llano. in the end; intel went the monolithic route soo....idk.

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see above.

Presentation sheets and more info:


http://www.anandtech.com/cpuchipsets...oc.aspx?i=3736
http://www.eetimes.com/news/semi/sho...leID=222700375
http://www.eetimes.com/news/semi/sho...2700375&pgno=2


Regards, Hans

http://images.anandtech.com/reviews/...osure/core.jpg

Core = 9.69mm^2
Core + L2 ~ 1.5x of that? = ~15mm^2

So basically quadcore logic under 90mm^2 (+IMC,HTPad...)?


IMO the total die size should be 140-180mm^2 or so, but no longer do they have to sell it at $99- fetching double the price should be easy, not that it would be a good purchase for desktop.

For laptops though I think this should be their way in, especially with the emphasis on power management- seems to me that this is a laptop oriented design for the most part, being able to target $300+ ASPs that AMD could previously only dream about.

i don't think this is for laptops, this will not include BD cores. The number of transistors show us that.

maybe i'm wrong, but laptops will come with BD cores. My point of view this is for smaller than laptops, maybe single core for iPad of Micro$oft. With a GPU this could be an Ipad killer.

good night ^^

Quote:

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Originally Posted by Kai Robinson

It seems that whenever Intel has no competition, it becomes complacent. AMD seems to be far more innovative than Intel lately, even if its performance isn't as high end.

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That's normal for an underdog imho. If you can't beat your big competitor in the field ppl care the most try to be innovative.

Big companies (especially when they nearly have a monopoly) tend to become slow and uninnovative (does this word even exist?).

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Originally Posted by god_43

?:confused::rolleyes: (i love these emoticons)

if being monolithic is bad, then why did intel not stay with a glued dual core = quad core thing? only time will tell if SB will have a better approach than llano. in the end; intel went the monolithic route soo....idk.

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It's not bad, it's just irrelevant unless it brings a performance increase or power cut.

AOD will allow users to unlock more SP????

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Originally Posted by Macadamia

Core = 9.69mm^2
Core + L2 ~ 1.5x of that? = ~15mm^2

So basically quadcore logic under 90mm^2 (+IMC,HTPad...)?


IMO the total die size should be 140-180mm^2 or so, but no longer do they have to sell it at $99- fetching double the price should be easy, not that it would be a good purchase for desktop.

For laptops though I think this should be their way in, especially with the emphasis on power management- seems to me that this is a laptop oriented design for the most part, being able to target $300+ ASPs that AMD could previously only dream about.

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Later die pictures showed more GPU area so the die for so far is ~205mm^2

http://chip-architect.com/news/Llano_comp2.jpg

Regards, Hans

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Originally Posted by Hans de Vries

Later die pictures showed more GPU area so the die for so far is ~205mm^2

http://chip-architect.com/news/Llano_comp2.jpg

Regards, Hans

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why there are 4 hypertransport links?

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Originally Posted by qcmadness

why there are 4 hypertransport links?

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Just a guess...Hans will obviously know more. :up:

1 HT link to the GPU.
1 or 2 HT link(s) between the CPU cores.
1 HT link to the rest of the system. (PCI-E bus, southbridge, add in card, etc...)

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Originally Posted by freeloader

Just a guess...Hans will obviously know more. :up:

1 HT link to the GPU.
1 or 2 HT link(s) between the CPU cores.
1 HT link to the rest of the system. (PCI-E bus, southbridge, add in card, etc...)

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Yes, interesting all these HT links... They are half width but probably
almost as fast as the full width HT's used up to now (>=6.4GHz)

Maybe for 2 dies per package for higher performance desktops?

or also for the HPC market (CRAY) to build supercomputers getting
a whole lot more TFlops from the GPU's?

or maybe one is used to transport monitor output data to the
South bridge?

Regards, Hans

So any idea how these will perform?

Close to a Phenom II and ... ?

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Originally Posted by Otis11

So any idea how these will perform?
Close to a Phenom II and ... ?

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Porpus-based and double L2 cache, should be similar with PII performance.

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Originally Posted by Hans de Vries

Yes, interesting all these HT links... They are half width but probably
almost as fast as the full width HT's used up to now (>=6.4GHz)

Maybe for 2 dies per package for higher performance desktops?

or also for the HPC market (CRAY) to build supercomputers getting
a whole lot more TFlops from the GPU's?

or maybe one is used to transport monitor output data to the
South bridge?

Regards, Hans

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Hypertranport 3.1: 3.2Ghz
-> HyperTranport 4.0 : 6.4Ghz.:D

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Originally Posted by Hans de Vries

Presentation sheets and more info:


http://www.anandtech.com/cpuchipsets...oc.aspx?i=3736
http://www.eetimes.com/news/semi/sho...leID=222700375
http://www.eetimes.com/news/semi/sho...2700375&pgno=2


Regards, Hans

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cheers :toast:

Quote:

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Originally Posted by Hans de Vries

Yes, interesting all these HT links... They are half width but probably
almost as fast as the full width HT's used up to now (>=6.4GHz)

Maybe for 2 dies per package for higher performance desktops?

or also for the HPC market (CRAY) to build supercomputers getting
a whole lot more TFlops from the GPU's?

or maybe one is used to transport monitor output data to the
South bridge?

Regards, Hans

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hmmmm the latter makes a lot of sense... but do they need a seperate HT link for that? thats what confused me about intel as well, why dont they use that massive qpi bus to move all the display data :confused:

Have we seen stacked HT links before???

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Originally Posted by qcmadness

Porpus-based and double L2 cache, should be similar with PII performance.

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how do you know its porpus based? besides many different improvements, it was my understanding that it would be based on the latest phenom core? i am sure there are plenty of details left out.

is dual channel ddr3 going to be enough bandwidth for both the gpu and cpu?

gpu does not connect by hypertransport.


http://www.theregister.co.uk/2010/02..._chip_preview/

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According to Sam Naffziger, a senior fellow at AMD, the Llano chip will use a 32 nanometer silicon-on insulator process and will have an on-chip DDR3 main memory controller as well as four cores and a DirectX 11 compatible GPU on the die. Naffziger would not divulge the feeds and speeds of the graphics unit, but he said that the GPU is a derivative of the current Radeon HD5000 series and that it will not link to the cores through a HyperTransport link. Instead, it will use a more direct link on the die. The architectural specifics of that link are not being discussed today at ISSCC.

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Regor would be the closest thing to compare per/core performance to obviously.

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Originally Posted by vietthanhpro

Hypertranport 3.1: 3.2Ghz
-> HyperTranport 4.0 : 6.4Ghz.:D

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Hi Vietthanpro,


I probably should have said 6.4 Gb/s (=HT3.1) anything above that
is speculation. I could believe higher speeds on a MCM (multi chip module)

There is a lot going on in the industry to get to higher serial
communication speeds. For instance some recent news:

Engineers explore life beyond 10 Gbit links
Designers rally around 25G, but next step still a mystery
http://www.eetimes.com/news/design/s...2700195&pgno=1

Altera to offer partial reconfiguration at 28-nm
28-Gbps transceivers, embed hard IP also on slate
http://www.eetimes.com/news/latest/s...leID=222600544

Regards, Hans

Quote:

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Originally Posted by Firestrider

is dual channel ddr3 going to be enough bandwidth for both the gpu and cpu?

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That's the big mystery question... How do they solve the bandwidth needs.
I somehow thrust the ATI engineers that they made sure that that's ok.

Maybe on a part of the die which hasn't been shown in public yet. or
maybe in cooperation with the DRAM industry + rival NVidia. It's possible
to put main memory in GDDR5 using TSV (Through Silicon Via's) die stacks.
Elpida is already supplying DDR3 TSV die stacks with 8 memory chips in a
package. The 9th chip is the interface chip which can in principle be
replaced by a GDDR5 interface chip.


Regards, Hans

Quote:

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Originally Posted by Hans de Vries

That's the big mystery question... How do they solve the bandwidth needs.
I somehow thrust the ATI engineers that they made sure that that's ok.

Maybe on a part of the die which hasn't been shown in public yet. or
maybe in cooperation with the DRAM industry + rival NVidia. It's possible
to put main memory in GDDR5 using TSV (Through Silicon Via's) die stacks.
Elpida is already supplying DDR3 TSV die stacks with 8 memory chips in a
package. The 9th chip is the interface chip which can in principle be
replaced by a GDDR5 interface chip.


Regards, Hans

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http://prohardver.hu/dl/upc/2010-01/...to_p.thumb.jpg

http://prohardver.hu/dl/upc/2010-01/...xm_1.thumb.jpg

128-bit, 512MB GDDR3 (E4690 MXM) :)

Is it possible that those "HT links" are single channel GDDR controllers?

Is the Fusion Memory Controller supposed to be implimented on Llano also, or just Bulldozer derivatives? I'm looking forwared to details on that FMC, but that info probably won't be released for a while.

Quote:

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Originally Posted by Hans de Vries

Later die pictures showed more GPU area so the die for so far is ~205mm^2

http://chip-architect.com/news/Llano_comp2.jpg

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Could you distinguish the HT ports from PCIe Lanes/ports ?
AMD earlier said that Fusion parts will come with PCIe Gen 2, only. So there should not be any Hypertransport at all.
http://xtreview.com/images/amd%20cguo%2002.jpg

There are also no NB chipsets mentioned in the table from above, only a SB part (Hudson).

Thus the ports that you named HT2 & HT3 are probably PCIe connectors that could be used for a dedicated graphic card (2x x8).
Another link will be probably used to connect to the southbridge, ATIs ALink is nothing more then a relabeled PCIe.

The last link could be used for anything else, PCIe x1 Slots, onboard chips, etc.

Furthermore the square die area below HT2 and HT3 and above HT4: Could that be the PCIe logic ?

cheers

Quote:

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Originally Posted by Opteron146

Could you distinguish the HT ports from PCIe Lanes/ports ?
AMD earlier said that Fusion parts will come with PCIe Gen 2, only. So there should not be any Hypertransport at all.
http://xtreview.com/images/amd%20cguo%2002.jpg

There are also no NB chipsets mentioned in the table from above, only a SB part (Hudson).

Thus the ports that you named HT2 & HT3 are probably PCIe connectors that could be used for a dedicated graphic card (2x x8).
Another link will be probably used to connect to the southbridge, ATIs ALink is nothing more then a relabeled PCIe.

The last link could be used for anything else, PCIe x1 Slots, onboard chips, etc.

Furthermore the square die area below HT2 and HT3 and above HT4: Could that be the PCIe logic ?

cheers

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You are right Opteron146 according to the presentation.
The PCIe lanes have moved from the chip-set to the CPU/GPU die.
The Llano compilation is already updated.


Regards, Hans

Did anyone see Flipp'n_Waff's response to Kyle...? lol hilarious.

Quote:

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Originally Posted by Hans de Vries

You are right Opteron146 according to the presentation.
The PCIe lanes have moved from the chip-set to the CPU/GPU die.
The Llano compilation is already updated.


Regards, Hans

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An even higher res Llano shot can be found at
http://www.pcgameshardware.de/aid,70...fikkarte/News/:
http://www.abload.de/img/amd-fusion-llano-vierk62mn.jpg
(Thanks to Opteron@Planet3dnow! for the copy - the same as Opteron146 here?)

This might be interesting for core comparisons, for example to find out, what this is (APM? more TLBs? or related to dynamic cache resizing?):

http://info.nuje.de/core_llano_compared.jpg.

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Originally Posted by Dresdenboy

(Thanks to Opteron@Planet3dnow! for the copy - the same as Opteron146 here?)

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Klar, wer sonst :yepp: ;)

Quote:

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Originally Posted by Xoulz

Did anyone see Flipp'n_Waff's response to Kyle...? lol hilarious.

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lol omfg i just saw it lol, here is a link, check out the comments.


http://blogs.amd.com/fusion/2010/02/...ovation-isscc/

Kyle is just being his "natural" self... He just can't help making a fool of himself,even publicly in front of some AMD's VPs. :shakes:

Quote:

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Originally Posted by Dresdenboy

An even higher res Llano shot can be found at
http://www.pcgameshardware.de/aid,70...fikkarte/News/:
http://www.abload.de/img/amd-fusion-llano-vierk62mn.jpg
(Thanks to Opteron@Planet3dnow! for the copy - the same as Opteron146 here?)

This might be interesting for core comparisons, for example to find out, what this is (APM? more TLBs? or related to dynamic cache resizing?):

http://info.nuje.de/core_llano_compared.jpg.

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Nice find! There's one slightly bigger version over there:

http://www.pcgameshardware.de/screen...o-Vierkern.jpg

Regards, Hans

Quote:

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Originally Posted by god_43

lol omfg i just saw it lol, here is a link, check out the comments.


http://blogs.amd.com/fusion/2010/02/...ovation-isscc/

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it's funny that moderator closed one eye on Flippin's sincere advice :D

Quote:

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Originally Posted by Hans de Vries

Nice find! There's one slightly bigger version over there:

http://www.pcgameshardware.de/screen...o-Vierkern.jpg

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Haha, same error as over @P3D, there is just a small "No Deeplink" message.
But it seems that I got a downsized picture last time, or PCGH changed the pic in the meantime.

Anyways, here's the pic:
http://www.abload.de/img/amd-fusion-llano-vierkeeh0.jpg

@Dresdenboy:
I'll change it over at P3D, too.
One idea for the changed area: Maybe some changes in the cache controller, due to the 8T cache cells (K10 had 6T) ?

cheers

Alex

Amidst all this technical talk, can someone please explain whether or not the on-die GPU for Llano and other fusion products will benefit the average user who already has a GPU? If so, how? Will the CPU distribute workloads to the GPU? I've heard that GPU is better at calculating/computing certain jobs than CPUs (ie all that GPGPU stuff).

Well geez, I remember having a discussion with Kyle on [H], where his argument was that the Phenom II chip was a pile of crap and that the headroom for O/Cing was worthless because it never added any value to the chip and wouldn't help AMD sell any. It's not what customers wanted. How crazy is that, on an enthusiast website no less! And I especially liked his Eyefinity review where he had boxes and boxes of intel processors piled up in the backround in plain site. I'm sure that added some good advertising dollars. :D It's pretty clear which brand he prefers at the moment, but come on, still harping on the move from 45nm to 32nm for Bulldozer? How old is that. Anyway, I really didn't expect it would get approved. :D

BTW, I was reading the comments on Dresdenboy's blog. Any truth to that one about the much improved front end here?

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Originally Posted by flippin_waffles

BTW, I was reading the comments on Dresdenboy's blog. Any truth to that one about the much improved front end here?

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I guess he was referring to the discussion @amdzone:
http://www.amdzone.com/phpbb3/viewto...0d27&start=500

No proof, just a patent.

Quote:

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Originally Posted by Opteron146

@Dresdenboy:
I'll change it over at P3D, too.
One idea for the changed area: Maybe some changes in the cache controller, due to the 8T cache cells (K10 had 6T) ?

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BTW, yesterday I looked for any reference to 8T cache cells in the reports and didn't find anything or overlooked it. IIRC, this subtopic has been announced for this ISSCC.

Quote:

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Originally Posted by Dresdenboy

BTW, yesterday I looked for any reference to 8T cache cells in the reports and didn't find anything or overlooked it. IIRC, this subtopic has been announced for this ISSCC.

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Yes, it was mentioned earlier in an eetimes article:

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Much of AMD's paper will focus on circuit techniques the company is using to lower power consumption and leakage of the core. For example, the core's L1 cache uses 8T memory cells to support low supply voltages.

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http://www.eetimes.com/rss/showArtic...leID=221900830

I guess they just forgot that in the telephone conference. IMO, there are still no real ISSCC articles.

Quote:

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Originally Posted by Opteron146

@Dresdenboy:
I'll change it over at P3D, too.
One idea for the changed area: Maybe some changes in the cache controller, due to the 8T cache cells (K10 had 6T) ?

cheers

Alex

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Does 6T mean six transistors per cache cell? So Llano's cache might need more space for the same amount, but on the other hand need less energy?

P.S. Dann bist du wohl auch der Opteron der im Luxx sein "Unwesen" treibt, was? :P

Quote:

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Originally Posted by Oliverda

http://prohardver.hu/dl/upc/2010-01/...to_p.thumb.jpg

http://prohardver.hu/dl/upc/2010-01/...xm_1.thumb.jpg

128-bit, 512MB GDDR3 (E4690 MXM) :)

Is it possible that those "HT links" are single channel GDDR controllers?

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I would like to see Graphics GDDR5 memory in the package yes :^)
If they still hide some of the lower part of the die, then this may be
the reason. The extra memory interface would be very easy to spot.

The other solution, the better one in the long term, is to raise the
128 bit IMC to GDDR5 speeds. This would currently limit the main
memory size. Fermi will use up to 2GB per 128bit databus in the 2nd
half of this year. However, this could rapidly increase with the use
of TSV stacked dies. I guess 4GB to 8GB of GDDR5 main memory
would be enough for 2011.


Regards, Hans

Quote:

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Originally Posted by FischOderAal

Does 6T mean six transistors per cache cell? So Llano's cache might need more space for the same amount, but on the other hand need less energy?

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The blocks containing the L1 data and instruction cache are some 10%
wider relatively compared to the 45nm layout because of the larger 8T
cells. Intel uses 8T cells for the L1 caches at 32nm at well.

The extra room is used for the extra logic Mathias was talking about.


Regards, Hans

Charlie Demerjian has his Llano article up with a lot of new details:
http://www.semiaccurate.com/2010/02/...nm-llano-core/

My thoughts are here:
http://citavia.blog.de/2010/02/11/mo...tails-7987376/

There is still room for surprises.. ;)

Here's a slight oddity of a question for you.

If I have a dual socket board for llano, will I get to use them in Crossfire?

Quote:

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Originally Posted by Motiv

Here's a slight oddity of a question for you.

If I have a dual socket board for llano, will I get to use them in Crossfire?

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Yeah, if you can hook up the crossfire bridge to the CPU! :rofl:

Motiv, Llano won't have Hyper Transport for CPU Interconnect. Only integrated memory controller and PCI Express like Clarkdale/Lynnfield.

Quote:

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Originally Posted by doompc

Motiv, Llano won't have Hyper Transport for CPU Interconnect. Only integrated memory controller and PCI Express like Clarkdale/Lynnfield.

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Shame that. Would of been interesting to see the marketing spin on a plug in upgrade that doubled CPU and GPU performance (and of course crossfire over HT).

I suppose with llano being a more mainstream CPU, it's not really needed.

It might support Hybrid Crossfire with the equivalent discrete GPU though. But that's more like a marketing gimmick than useful feature (1 slow GPU sucks, 2 slow GPUs still suck).

Quote:

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Originally Posted by FischOderAal

Does 6T mean six transistors per cache cell? So Llano's cache might need more space for the same amount, but on the other hand need less energy?

P.S. Dann bist du wohl auch der Opteron der im Luxx sein "Unwesen" treibt, was? :P

---

Yes, 6T stands for 6 transistor, most of the cache in the last several years were based on a 6 transistor bit cell (for storing one bit), Intel implemented an 8T transistor cell in their 45 nm Nehalem, and it appears (interestingly enough) that AMD will do the same.

Logically, 8T should take up more area, depending on the layout how much more area is not going to be exactly clear unless AMD publishes a cell layout picture.

It is counter intuitive that 8T should consume less power than 6T, and all things being equal it 8T would consume more power than 6T. However, 8T allows voltage to be dropped (not as sensitive to lower voltage limit) in lower power standby, which has a net win on power.

http://img59.imageshack.us/img59/494...alystday03.png

Did you all notice the teraFLOP written there, if this is indeed written for the APU it means that they went from a gigaFLOP est. to a teraFLOP est. :)

Quote:

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Originally Posted by ajaidev

http://www.pcgameshardware.de/screen...yst-Day-03.png

Did you all notice the teraFLOP written there, if this is indeed written for the APU it means that they went from a gigaFLOP est. to a teraFLOP est. :)

---

http://www.pcgameshardware.de/screen...yst-Day-03.png

Deeplinking is not allowed.

http://img59.imageshack.us/img59/494...alystday03.png

And yeah, a teraFLOPS should be pretty accurate number for the integrated GPU. :)

Quote:

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Originally Posted by zalbard

Deeplinking is not allowed.

http://www.pcgameshardware.de/screen...yst-Day-03.png

And yeah, a teraFLOPS should be pretty accurate number for the integrated GPU. :)

---

Fixed :up:

The last time Anand referred to this he called it a gigaFLOP class APU, if the teraFLOP moniker is truly for the APU "At stock" its wonderful news.

Quote:

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Originally Posted by ajaidev

Fixed :up:

The last time Anand referred to this he called it a gigaFLOP class APU, if the teraFLOP moniker is truly for the APU "At stock" its wonderful news.

---

I've read that for TeraFLOP class architecture moniker you need 501GFLOPS performance. Still quite a bit more than HD2900 or HD3870 or HD4670 in your CPU :up:

Quote:

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Originally Posted by ajaidev

Did you all notice the teraFLOP written there, if this is indeed written for the APU it means that they went from a gigaFLOP est. to a teraFLOP est. :)

---

In my opinion, they are just referring to their visual computing breakthroughs by breaking the 1 TFLOP barrier.

They clearly wrote 1TFLOP GPU, not 1 TFLOP APU ;-)

Furthermore, think about the memory limitations ... ~800 Shader cores and then dual channel DDR3, which is shared with the CPU cores.

That would be not feasible in my opinion.

Quote:

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Originally Posted by Hans de Vries

Hi Vietthanpro,
I probably should have said 6.4 Gb/s (=HT3.1) anything above that
is speculation. I could believe higher speeds on a MCM (multi chip module)
There is a lot going on in the industry to get to higher serial
communication speeds. For instance some recent news:
Engineers explore life beyond 10 Gbit links
Designers rally around 25G, but next step still a mystery
http://www.eetimes.com/news/design/s...2700195&pgno=1
Regards, Hans

---

Hi Hans de Vries, first is HTlink then PCIe. Why ?

Quote:

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Originally Posted by vietthanhpro

Hi Hans de Vries, first is HTlink then PCIe. Why ?

---

Because of my post #32. Don't aks, read first ;-)

Quote:

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Originally Posted by Opteron146

In my opinion, they are just referring to their visual computing breakthroughs by breaking the 1 TFLOP barrier.

They clearly wrote 1TFLOP GPU, not 1 TFLOP APU ;-)

Furthermore, think about the memory limitations ... ~800 Shader cores and then dual channel DDR3, which is shared with the CPU cores.

That would be not feasible in my opinion.

---

How the GPU access memory is still an unknown really. But the GPU is made on a 32nm SOI process, so higher clockspeeds than in earlier designs might be achievable.

Quote:

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Originally Posted by BrowncoatGR

How the GPU access memory is still an unknown really. But the GPU is made on a 32nm SOI process, so higher clockspeeds than in earlier designs might be achievable.

---

According to Sam Naffziger, the GPU accesses memory through the XBar like the CPU cores. Shared memory model, same type of access. Maybe they added some prefetching logic, which works better for GPU typical access patterns.

Looks promising, but intel has my heart now.

Quote:

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Originally Posted by Badfastbusa

Looks promising, but intel has my heart now.

---

Yes Intel's graphic enabled CPUs have captured the adoration of the masses. Or:
Why would you bother posting this?

I'll let you pick. :rolleyes:

Quote:

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Originally Posted by doompc

It might support Hybrid Crossfire with the equivalent discrete GPU though. But that's more like a marketing gimmick than useful feature (1 slow GPU sucks, 2 slow GPUs still suck).

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I got crossfire 3470's that don't suck they Oc to 900mhz core.... 850mhz ram, passivly.

Extensive interview with Samuel Naffziger - AMD's Senior Fellow about company's upcoming APU "Llano" - http://www.insidehw.com/Editorials/I...sing-Unit.html

Quote:

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Originally Posted by Dresdenboy

An even higher res Llano shot can be found at
This might be interesting for core comparisons, for example to find out, what this is (APM? more TLBs? or related to dynamic cache resizing?):

http://info.nuje.de/core_llano_compared.jpg.

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I see more changes:

Longer Shedulers or ALU/AGUs ??
Increased reorder buffer ??
New unit next to the FPU register?? (currently it is empty space)

http://img504.imageshack.us/img504/4275/comp333.jpg

Worthless for enthusiasts until they improve how multi-GPU solutions work. Right now, GPUs don't play together nearly as nicely as CPUs... the implementation is incredibly clumsy and wasteful.

Great for laptops, though. Ensures that you'll at least get a half-decent integrated graphics chip.

Quote:

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Originally Posted by iddqd

Worthless for enthusiasts until they improve how multi-GPU solutions work. Right now, GPUs don't play together nearly as nicely as CPUs... the implementation is incredibly clumsy and wasteful.

Great for laptops, though. Ensures that you'll at least get a half-decent integrated graphics chip.

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id use it for physics, probably more than enough power to do a better job than quad 3-4ghx cpu dedicated to it.

Quote:

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Originally Posted by Zibi

I see more changes:

Longer Shedulers or ALU/AGUs ??
Increased reorder buffer ??

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Yes, this is mentioned in the articles linked previously:
http://www.xtremesystems.org/forums/...2&postcount=50

Quote:

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New unit next to the FPU register?? (currently it is empty space)

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I think that's new ;-)
I assume that it has something to do with SSSE3/SSSE4.1. When AMD doubled the FPU from 64->128bit they basically copied the whole 64bit FPU. However there was some empty space in the end which was used for old 3DNOW! stuff and need not to be doubled. Thus it would be logical, if AMD uses that free space in the doubled FPU part with another instruction set extension.

Welcome to XS

Opteron146

Quote:

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Originally Posted by iddqd

Worthless for enthusiasts until they improve how multi-GPU solutions work. Right now, GPUs don't play together nearly as nicely as CPUs... the implementation is incredibly clumsy and wasteful.

Great for laptops, though. Ensures that you'll at least get a half-decent integrated graphics chip.

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Apple OS will take care of this :)
Google for Frand Central Dispatch and CLANG/LLVM.

And then think about the current AMD - Apple rumors ;-)

Quote:

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Originally Posted by Zibi

I see more changes:

Longer Shedulers or ALU/AGUs ??
Increased reorder buffer ??
New unit next to the FPU register?? (currently it is empty space)

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Additional to what Opteron146 pointed out, there was another update over 2 months ago:
http://citavia.blog.de/2010/02/09/so...o-die-7974978/
http://data6.blog.de/media/392/43623...32b03fc_m.jpeg
There is also something new in the L/S unit plus new D$ tags.
The ALU/AGU block became longer at the int multiplier end, maybe related to a lower power multiplier implementation or the already mentioned hardware divider support.

why intel and amd try to put gpu into cpu?????

Quote:

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Originally Posted by PatRaceTin

why intel and amd try to put gpu into cpu?????

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to cut costs, nothing more.

Quote:

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Originally Posted by Chumbucket843

to cut costs, nothing more.

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I think there is more
to better manage the power consumption of GPU

Quote:

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Originally Posted by haylui

I think there is more
to better manage the power consumption of GPU

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Separate Dies can do all of the exact same power management tricks that a single die can.
It is all about integration and production cost reduction.

GPU sitting next to memory controller communicates much faster with CPU and memory, too...consider how fast is dedicated VGA memory compared to the memory (=system RAM) which the integrated GPU core in northbridge has.

Just takethe example of side-port memory vs main memory vs dedicated vga memory.

Quote:

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Originally Posted by PatRaceTin

why intel and amd try to put gpu into cpu?????

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Because multicore is the future, and GPUs have lots of cores in less die space ;-)