AMD's Bobcat and Bulldozer

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08-30-2010, 07:28 AM
Dimitriman

Quote:

Originally Posted by informal

Not in a case when terrace is a shareholder in certain company ;). IF BD fails(it will not,but for a sake of an argument) the stock in that company raises and he profits.Simple math :p:

You speak the truth therrr
08-30-2010, 07:52 AM
Sn0wm@n

Quote:

Originally Posted by JF-AMD

See, that statement is what gets people in trouble. Someone reads that statement and assumes 10% lower performance.

IPC will be higher than previous generation
Single threaded performance will be higher than previous generation

megaquote FTW!!!!
08-30-2010, 08:01 AM
Tomasis

Quote:

Originally Posted by Florinmocanu

That's a module mate. 1 core in that module has higher IPC than a Thuban core. Pretty simple. But, when both cores in 1 module work on 2 threads, than you loose 10% performance per core because of the shared components. In single thread scenarios, 1 of the 2 cores works at 100%.

veryyy simple explanation :up::yepp:
08-30-2010, 08:23 AM
JF-AMD

If you are going to say that there is a 20% compromise because we have shared resources, then you have to say that Intel has an 85% compromise from their shared architecture. They share execution units and HT gives you a ~14% integer increase.

Some people like to do math but they don't like to do all the math.
08-30-2010, 08:37 AM
BatteryOperated

Quote:

Originally Posted by JF-AMD

If you are going to say that there is a 20% compromise because we have shared resources, then you have to say that Intel has an 85% compromise from their shared architecture. They share execution units and HT gives you a ~14% integer increase.

Some people like to do math but they don't like to do all the math.

megaquote!!!
08-30-2010, 08:37 AM
Manicdan

Quote:

Originally Posted by JF-AMD

If you are going to say that there is a 20% compromise because we have shared resources, then you have to say that Intel has an 85% compromise from their shared architecture. They share execution units and HT gives you a ~14% integer increase.

Some people like to do math but they don't like to do all the math.

best math since 2+2=4
08-30-2010, 08:43 AM
terrace215

Quote:

Originally Posted by JF-AMD

IPC will be higher than previous generation
Single threaded performance will be higher than previous generation

Can you say, "single-threaded integer IPC will be higher than the previous generation" ?

Because that is what Alsup is saying is NOT the case. (integer performance, yes, but integer performance/clock drops slightly in a thread, made up for by a faster clock)

Anything less than that statement could be satisfied through the not-in-dispute FP improvements, or the more cores part. It's got to be: Integer (not FP), IPC (or "performance/clock", not just "performance"), Single-threaded

Something like, "BD will have higher single-threaded integer performance/clock than the previous generation."

That would actually address (and contradict) the statement that Alsup made.
08-30-2010, 08:44 AM
cegras

Aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaargh

I'm devolving from the level of discussion in this threaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaargh
08-30-2010, 08:46 AM
blindbox

I'm breaking into tears.

Well I for one likes to keep on topic.
madcho, the 33% more cores for 50% more perf is on server loads. You can't reliably guesstimate from there.
08-30-2010, 08:50 AM
geo

Quote:

Originally Posted by nn_step

Here is what it means.

Bulldozer cores are like Intel Hyper-threading cores.

The primary difference is that AMD throws more transistors at the problem by giving each thread it's own set of integer execution units. Added to the fact that AMD’s distributed schedulers and instruction grouping. This is a clear architectural trade-off of performance and decreased control complexity versus size and increased execution complexity. Replicating two full featured ALUs uses more die area, but provides higher performance for certain corner cases, and enables a simpler design for the ROB and schedulers.

The honest truth is if NO CPU designed yet, can keep a constant throughput of 2 instructions per clock. So the more efficient design of the Integer cores, suggest that we shouldn't expect any performance drop at all. [For 99.9% of all user applications ]

ok. if there are no single thread perf drops, then going by the article that compares Real Cores vs HT there should be atleast 40 % improvement compared to similarly clocked Phenom2 at same clocks!! ?
08-30-2010, 08:58 AM
terrace215

Quote:

Originally Posted by JF-AMD

If you are going to say that there is a 20% compromise because we have shared resources, then you have to say that Intel has an 85% compromise from their shared architecture. They share execution units and HT gives you a ~14% integer increase.

What happened to power in those statements? Does performance per watt suddenly not matter? ;)

Or could it be that the adding most of a second integer core actually uses a nice chunk of power when adding that 80% performance? :rolleyes:

Is it possible that the thing to look at would be the performance/W improvements that the 2 different degrees of resource-sharing provide? Nahhhhhh.
08-30-2010, 09:05 AM
terrace215

Quote:

Originally Posted by JF-AMD

How many times do I have to tell you that bulldozer has higher IPC than our current architecture?

Is somebody being paid by intel to continually post these statements?

That statement is from AMD's ex Chief Architect. I think the guy is now retired, but if you think Intel is paying him to post on comp.arch... :rofl:

And your previous statements manage to artfully avoid getting all of "integer" "IPC" (note, IPC, not "performace") and "single-threaded" covered.

It wouldn't be hard to state, assuming your new architect will sign off on it.
08-30-2010, 09:08 AM
Sn0wm@n

Quote:

Originally Posted by terrace215

Can you say, "single-threaded integer IPC will be higher than the previous generation" ? .

read my previous megaquote ....YES it will be improved ....
08-30-2010, 09:12 AM
Hornet331

Come one this gets boring... we can discuss the matter when we have actuall numbers. As it stands now BD is expected to increase IPC and ST performance. Theres not much point in it discussing with a marketing guy and try to make him slip some information regarding this concern.
08-30-2010, 09:13 AM
blindbox

Quote:

Originally Posted by Sn0wm@n

read my previous megaquote ....YES it will be improved ....

Apparently he wants it to be very specific. He thinks something like, AMD drops integer performance to 10% of K10, but increased FP performance by 1001%, hence increased single-threaded performance.

Meh, looks like he still haven't read the whole thread. And he's running out of things to argue about.

EDIT: Anyway, third question answers terrace215's power questions. Honestly man, read the thread, read the slides, we're not here to spoonfeed you, especially seeing how eager you are. Stop nitpicking, and don't say you're not nitpicking.

http://blogs.amd.com/work/2010/08/30...%80%93-part-2/

Nothing that we don't know of though.
08-30-2010, 09:25 AM
Jowy Atreides

Quote:

Originally Posted by terrace215

That statement is from AMD's ex Chief Architect. :rofl:

See:

Quote:

IPC will be higher than previous generation
Single threaded performance will be higher than previous generation

Ex architect is EX for a reason. His version of bulldozer sucked and was cancelled until it could be satisfactory.
08-30-2010, 09:27 AM
LightSpeed

^^

lol

@ terrace215: Give it a break man?
08-30-2010, 09:32 AM
generics_user

i think that a certain forum rule REALLY describes what certain persons are doing in here...

19. Trolling
Anyone entering the forum with the express intent to cause trouble or harm is subject to immediate and permanent ban.
08-30-2010, 09:32 AM
Shadov

...

Quote:

Originally Posted by terrace215

Can you say, "single-threaded integer IPC will be higher than the previous generation" ?

Because that is what Alsup is saying is NOT the case. (integer performance, yes, but integer performance/clock drops slightly in a thread, made up for by a faster clock)

Anything less than that statement could be satisfied through the not-in-dispute FP improvements, or the more cores part. It's got to be: Integer (not FP), IPC (or "performance/clock", not just "performance"), Single-threaded

Something like, "BD will have higher single-threaded integer performance/clock than the previous generation."

That would actually address (and contradict) the statement that Alsup made.

Terrace are you buying a ready product or 1 kg of Ghz like tomatoes?

Who cares about clock for clock if the part performs better in a given TDP budget which it was designed for.

To everyone else reading this thread: can we start a pool for Movieman to ban terrace from all threads including the word AMD? :shakes:
08-30-2010, 09:34 AM
Solus Corvus

Quote:

Originally Posted by savantu

I wouldn't be surprised for this to hold true core for core at the same frequency.

I won't discount the possibility that taking out extra ALUs could lead to a bottleneck. We don't know enough to say otherwise at this point.

But I'm not going to reject the possibility that with all the frontend and cache improvements 2 well fed ALUs could beat 3 poorly fed ones. ALU count alone doesn't determine the average IPC, only the max. K10 isn't anywhere near 2 on average as you pointed out.

Quote:

Originally Posted by terrace215

Can you say, "single-threaded integer IPC will be higher than the previous generation" ?

Why all the fascination with integer instructions? Real code uses a mix of int, fp, logical, and memory instructions. If the IPC of BD versus K10 increases when executing real world code isn't that what matters?

Quote:

Originally Posted by terrace215

What happened to power in those statements? Does performance per watt suddenly not matter? ;)

Or could it be that the adding most of a second integer core actually uses a nice chunk of power when adding that 80% performance? :rolleyes:

Is it possible that the thing to look at would be the performance/W improvements that the 2 different degrees of resource-sharing provide? Nahhhhhh.

Of course adding a whole second set of execution resources is going to increase power consumption compared to HT. It's also going to perform better.
08-30-2010, 09:35 AM
flippin_waffles

Quote:

Originally Posted by terrace215

Can you say, "single-threaded integer IPC will be higher than the previous generation" ?

Because that is what Alsup is saying is NOT the case. (integer performance, yes, but integer performance/clock drops slightly in a thread, made up for by a faster clock)

Anything less than that statement could be satisfied through the not-in-dispute FP improvements, or the more cores part. It's got to be: Integer (not FP), IPC (or "performance/clock", not just "performance"), Single-threaded

Something like, "BD will have higher single-threaded integer performance/clock than the previous generation."

That would actually address (and contradict) the statement that Alsup made.

What difference does it make, either way? I'm starting to wonder if you and your buddies are'nt just sitting around your mothers basement drinking pop, laughing at all the sh1t you're stirring up in various AMD threads.
08-30-2010, 09:37 AM
Sn0wm@n

its obvious that he his scared that bulldozer will become the 2010 pentium killer ... so his stock will likely plunge ... poor him
08-30-2010, 09:41 AM
generics_user

Quote:

Originally Posted by Shadov

Terrace are you buying a ready product or 1 kg of Ghz like tomatoes?

Who cares about clock for clock if the part performs better in a given TDP budget which it was designed for.

To everyone else reading this thread: can we start a pool for Movieman to ban terrace from all threads including the word AMD? :shakes:

i guess that it's up to the admins to decide on this issue; not on us to start a witchhunt on certain persons....

while i think that the only purpose of terrace' posts is to create chaos and troll 80% of all forum members (and to secretly earn some more money from his shares / or directly from intel) we aren't the ones who should decide if a user gets banned only because he says things that we don't like
08-30-2010, 09:41 AM
terrace215

Quote:

Originally Posted by Sn0wm@n

read my previous megaquote ....YES it will be improved ....

You guys apparently don't realize that:

performance != performance/clock (IPC)

IPC != single-threaded IPC

and that the Alsup statement was about the *Integer* pipeline.

It doesn't matter how big the font is that says "Single-thread performance is higher." or "Bulldozer IPC will be higher." Neither of those address the Alsup claim which was that:

Single-threaded integer performance PER CLOCK (i.e. IPC) will be ~5% lower.

I would not have thought that the distinction would require a great deal of analytical reasoning ability to comprehend, but the numerous replies (with one exception that I've seen) indicate that I am either incorrect in my assessment or that educational systems are failing.

And really, all the personal stuff because someone posts something you disagree with? Really?
08-30-2010, 09:42 AM
Solus Corvus

Quote:

Originally Posted by terrace215

IPC != single-threaded IPC

It doesn't? :rolleyes:
08-30-2010, 09:44 AM
terrace215

Quote:

Originally Posted by Solus Corvus

Why all the fascination with integer instructions? Real code uses a mix of int, fp, logical, and memory instructions.

The integer pipeline. That includes the loads & stores. With fp resources being widened, fp performance is taking a large jump-- what's left is the integer pipeline.
08-30-2010, 09:44 AM
generics_user

Quote:

Originally Posted by flippin_waffles

What difference does it make, either way? I'm starting to wonder if you and your buddies are'nt just sitting around your mothers basement drinking pop, laughing at all the sh1t you're stirring up in various AMD threads.

QFT

Quote:

Originally Posted by Sn0wm@n

its obvious that he his scared that bulldozer will become the 2010 pentium killer ... so his stock will likely plunge ... poor him

2011 ;)
he still has plenty of time to sell his stock; he only thinks that trolling the crap out of a forum is going to give him another 1-2 months of rising stock prices (but it's extremely unlikely that some nerds like us posting on this forum are going to affext stock prices :ROTF:)
08-30-2010, 09:46 AM
ajaidev

This is interesting bit from Question's Set no 2 @ AMD blog:

Quote:

“Is there any”programmable-tangible” improvement in synchronization between cores in the same module? In other words, will I get tangible performance improvement if I can partition my multi-threaded algorithm to pairs of closely interacting threads, and schedule each pair to a module?” – Edward Yang

That is a very interesting question.

For the majority of software, the OS will work in concert with the processor to manage the thread to core relationships. We are collaborating with Microsoft and the open source software community to ensure that future versions of Windows and Linux operating systems will understand how to enumerate and effectively schedule the Bulldozer core pairs. The OS will understand if your machine is setup for maximum performance or for maximum performance/watt which takes advantage of Core Performance Boost.

However, let’s say you want to explore if you can get a performance advantage if your threads were scheduled on different modules. The benefit you can gain really depends on how much sharing the two threads are going to do.

Since the two integer cores are completely separate and have their own execution clusters (pipelines) you get no sharing of data in the L1 – and there is no specific optimizations needed at the software level. However, at the L2 cache level there could be some benefits. A shared L2 cache means that both cores have access to read the same cache lines – but obviously only one can write any cache line at any time. This means that if you have a workload with a main focus of querying data and your two threads are sharing a data set that fits in our L2, then having them execute in the same module could have some advantages. The main advantage we expect to see is an increase in the power efficiency of the cores that are idle. The more idle other cores are, the better chance the busy cores will have to boost.

However, there is another consideration to this which is how available other cores are. You need to weigh the benefits of data sharing with the benefit of starting the thread on the next available core. Stacking up threads to execute in proximity means that a thread might be waiting in line while an open core is available for immediate execution. If your multi-threaded application isn’t optimized to target the L2 (or possibly the L3 cache), or you have distinctly separate applications to run, and you don’t need to conserve power, then you’ll likely get better performance by having them scheduled on separate modules. So it is important to weigh both options to determine the best execution.
08-30-2010, 09:46 AM
terrace215

Quote:

Originally Posted by Solus Corvus

It doesn't? :rolleyes:

Not when a marketing guy says it about "Bulldozer". Think of those 33% more cores, all processing instructions. ;)
08-30-2010, 09:47 AM
generics_user

Quote:

Originally Posted by terrace215

The integer pipeline. That includes the loads & stores. With fp resources being widened, fp performance is taking a large jump-- what's left is the integer pipeline.

load/store performance is increased from K10...

just take your time and really think about it if you don't know it already

just stop trolling this forum if the only point in your posts is creating chaos

just stop hiding your real employer if you get paid by intel for spreading completely wrong information on this forum
08-30-2010, 09:48 AM
Sparky

Terrace, seriously, just give it a rest. If people don't want to listen to your view (whether it be wrong or right), saying it incessantly over and over isn't going to do much. You should know this, since people have been saying the same thing over and over to you, and you don't listen either, so, goes both ways ;)

Integer performance isn't all there is to a CPU's overall performance. There is a lot more to it than that. Come on...
Why not wait until the thing is closer to release and we have some harder numbers instead of this "he said she said they said" game that gives random tidbits for people to grab onto and wave around frantically insisting they have all the answers?
08-30-2010, 09:52 AM
Solus Corvus

Quote:

Originally Posted by terrace215

Not when a marketing guy says it about "Bulldozer". Think of those 33% more cores, all processing instructions. ;)

So you are saying that he invented a new definition for the term IPC because he's from AMD and can't possibly be using it the way everyone else does?
08-30-2010, 09:54 AM
Movieman

Quote:

Originally Posted by terrace215

Not when a marketing guy says it about "Bulldozer". Think of those 33% more cores, all processing instructions. ;)

I think you've overstayed your welcome in the News section.
I'm removing your access to News and the AMD section for the benefit of all.
08-30-2010, 10:03 AM
Movieman

It's done. now lets move on..;)
08-30-2010, 10:05 AM
ajaidev

Quote:

Originally Posted by Movieman

I think you've overstayed your welcome in the News section.
I'm removing your access to News and the AMD section for the benefit of all.

That was a bit of a corporal punishment :p: ammm its ok to express ones view, if the other person does not like it he should ignore the other guy.

News section is one of the most happening section in XS :D but i am not one in charge or one who can judge. But i do think that now that he is gone the thread will turn boring with less people digging up technical jargon and what not....
08-30-2010, 10:18 AM
informal

Quote:

Originally Posted by random now banned due

The integer pipeline. That includes the loads & stores. With fp resources being widened, fp performance is taking a large jump-- what's left is the integer pipeline.

The guy above somehow forgets that 2 integer pipelines are now "dislodged" from the integer core and placed inside the FP cluster.Those are integer SIMD units.So if you want to properly count, count all the integer resources .2 ALUs,2Agens(we really have no idea if these can do more than Adress Generation) + 2 or 1 integer simd pipeline.
08-30-2010, 10:19 AM
madcho

A good function to calc terrasse IQ :

short int terrasse(void);
terrasse{
return 0;
}

Ok this is a troll sry :).

About definitions we all should know :

Performance on one thread = IPC x Frequency
CPU Performance in heavy multithread load= IPC x Frequency x multithread speed up.

I guess i'm right ;)
Edited: Lets keep this friendly huh? My typing fingers are getting tired.
08-30-2010, 10:23 AM
Movieman

Quote:

Originally Posted by ajaidev

That was a bit of a corporal punishment :p: ammm its ok to express ones view, if the other person does not like it he should ignore the other guy.

News section is one of the most happening section in XS :D but i am not one in charge or one who can judge. But i do think that now that he is gone the thread will turn boring with less people digging up technical jargon and what not....

Yes it was but had you seen my PM box you'd understand.
There comes a point where one needs tounderstand that they've made their point and move on.
08-30-2010, 10:27 AM
informal

I for one think that Movieman was more than patient with that due.Actually that is an understatement :)
08-30-2010, 10:27 AM
Solus Corvus

I'm really sick of people posting in a thread only to comment about how someone else is a troll. So what if they are? Ad hominems still don't make for valid arguments or civilized discussion. These threads would be so much cleaner if people only remembered "attack the argument, not the person".
08-30-2010, 10:30 AM
AliG

Quote:

Originally Posted by Sparky

Terrace, seriously, just give it a rest. If people don't want to listen to your view (whether it be wrong or right), saying it incessantly over and over isn't going to do much. You should know this, since people have been saying the same thing over and over to you, and you don't listen either, so, goes both ways ;)

Integer performance isn't all there is to a CPU's overall performance. There is a lot more to it than that. Come on...
Why not wait until the thing is closer to release and we have some harder numbers instead of this "he said she said they said" game that gives random tidbits for people to grab onto and wave around frantically insisting they have all the answers?

just put him on your ignore list, that's what I did
08-30-2010, 10:30 AM
Pointhore

Quote:

Originally Posted by Movieman

I think you've overstayed your welcome in the News section.
I'm removing your access to News and the AMD section for the benefit of all.

Hooray!!! Thats the best thing I've read all day.:yepp: It was funny in the beginning but he started to get a little annoying after a while. :shrug:

Hopefully the discussion will stay on what is known about BD and not what people dream up in thier minds.

Quote:

But i do think that now that he is gone the thread will turn boring with less people digging up technical jargon and what not....

I think once more info is released this thread will stay plenty active
08-30-2010, 10:39 AM
AliG

Just wondering, what with all the chatter about bulldozer being 2+2 (alu+agu), aren't all intel cpus from core 2 and on 3+1? Correct me if I'm wrong, but if that's the case and the grand majority of consumer applications don't use more than 2 alus at a time, then I don't really what the issue is.

Now what I can see being an issue is Sandy Bridge performing considerably better than expected (I recall many rumors saying it was just an efficiency platform, and minimal if no ipc improvements would be seen), however that really isn't a discussion for this thread anyways.
08-30-2010, 10:40 AM
Hornet331

Quote:

Originally Posted by Solus Corvus

I'm really sick of people posting in a thread only to comment about how someone else is a troll. So what if they are? Ad hominems still don't make for valid arguments or civilized discussion. These threads would be so much cleaner if people only remembered "attack the argument, not the person".

Wise words, but people resort to personal attacks if they have no or limited understading whats going on... :p:

Quote:

Originally Posted by AliG

Just wondering, what with all the chatter about bulldozer being 2+2 (alu+agu), aren't all intel cpus from core 2 and on 3+1? Correct me if I'm wrong, but if that's the case and the grand majority of consumer applications don't use more than 2 alus at a time, then I don't really what the issue is.

Now what I can see being an issue is Sandy Bridge performing considerably better than expected (I recall many rumors saying it was just an efficiency platform, and minimal if no ipc improvements would be seen), however that really isn't a discussion for this thread anyways.

While its true that they are only 3+1 conroe introduced a 4(+1) for the decoding stage, just as BD did now. So the utilisation of the alus is/was higher.
08-30-2010, 10:43 AM
Manicdan

Quote:

Originally Posted by ajaidev

This is interesting bit from Question's Set no 2 @ AMD blog:

thanks for the update from round 2, i was waiting for this, he posts a thread in the AMD section, but im too busy here to check it out every 5 minutes.

the round of questions do provide some more fun info, and the comments are where the real goodies show up across the next few days
08-30-2010, 10:43 AM
Particle

It may not refute the argument, but if someone is genuinely a "troll" they don't really deserve to be able to participate in a civil discussion. Thread crapping when a person can't prove an argument or disprove one they dislike does nothing but detract from the quality of the overall debate.
08-30-2010, 10:45 AM
tifosi

Quote:

Originally Posted by Movieman

I think you've overstayed your welcome in the News section.
I'm removing your access to News and the AMD section for the benefit of all.

Nothing personal against "terrace215", or anyone else... Opinions are just that, opinions! Everybody has one, just like they have an a$$#0L3... Facts, we will only find out when someone perhaps will leak some numbers... I did read in forums here only that somewhere in a cave in my own damned country, there's a system running this piece of hardware in question... A whole 16-pack (for as many cores) :P will be given to you dear fella... find out more please! You know who you are...

Movieman, if you come to New Delhi, India, do sound me off, i'll buy you a beer. :)

I just wish that it would be here soon... :P More pleasurable than owning the chip itself would be knowing what black magic went into making it :D

EDIT:
1) Ok, i had to apologize for my language...
2) Seriously getting harder to decide which would be more fun, owning one... or knowing about it more... :P Both, would be better :D
08-30-2010, 11:05 AM
Hornet331

Quote:

Originally Posted by Particle

It may not refute the argument, but if someone is genuinely a "troll" they don't really deserve to be able to participate in a civil discussion. Thread crapping when a person can't prove an argument or disprove one they dislike does nothing but detract from the quality of the overall debate.

Quite interesting, by that definition he wasn't a trol lat all. He provided a logical argument/question with some facts (even when they where old), yet people had no real facts to counter his spesific question (ST IPC). The only facts that where available where increased ST performance and increased IPC (not specifed if its ST or not).

Anyway personally I prefer hard numbers, so all this theoretical mindgames arn't my cup of tea.
08-30-2010, 11:05 AM
qcmadness

Quote:

Originally Posted by AliG

Just wondering, what with all the chatter about bulldozer being 2+2 (alu+agu), aren't all intel cpus from core 2 and on 3+1? Correct me if I'm wrong, but if that's the case and the grand majority of consumer applications don't use more than 2 alus at a time, then I don't really what the issue is.

Now what I can see being an issue is Sandy Bridge performing considerably better than expected (I recall many rumors saying it was just an efficiency platform, and minimal if no ipc improvements would be seen), however that really isn't a discussion for this thread anyways.

Prefetching and branch prediction plays a major role for high utilization of ALU / FPUs.

As stated before, most programs have IPC of < 1.0.
08-30-2010, 12:17 PM
AliG

Quote:

Originally Posted by qcmadness

Prefetching and branch prediction plays a major role for high utilization of ALU / FPUs.

As stated before, most programs have IPC of < 1.0.

right that's what I thought, because otherwise we would be seeing zero increase from core 2 to sandy bridge as primarily only the logic and prefetchers were changed
08-30-2010, 12:52 PM
generics_user

Quote:

Originally Posted by Hornet331

Quite interesting, by that definition he wasn't a trol lat all. He provided a logical argument/question with some facts (even when they where old), yet people had no real facts to counter his spesific question (ST IPC). The only facts that where available where increased ST performance and increased IPC (not specifed if its ST or not).

Anyway personally I prefer hard numbers, so all this theoretical mindgames arn't my cup of tea.

only that every "fact" he postet was already debunked several posts earlier (actually in the BD news in the OP)

the 2 AGU / 2 ALU isn't genuine at all as the new units made Bulldozer wider than K8 was which was able to do only a total of 3 AGU / ALU operations at the same time; Bulldozer is cap able of doing a total of 4 agu/alu operations at the same time

additionally Single threaded IPC has to increase to make 8 cores running at 90% of their peak performance (each core in a BD module, when both cores are fully utilized, runs at 90% of the performance compared to a single BD core with an unutilized second core in its own module)
so all cores in the 150% faster statement by AMD have to run at only 90% of their peak single thread performance, which makes calculating single thread IPC even more complicated than ever before ;)
08-30-2010, 01:23 PM
JF-AMD

Quote:

Originally Posted by Manicdan

thanks for the update from round 2, i was waiting for this, he posts a thread in the AMD section, but im too busy here to check it out every 5 minutes.

the round of questions do provide some more fun info, and the comments are where the real goodies show up across the next few days

I post it in the AMD section because it is a blog, not news. I don't want people accusing me of being a spammer. I will leave the news posts for when we actually announce something ;)
08-30-2010, 01:34 PM
gallag

Quote:

Originally Posted by informal

I for one think that Movieman was more than patient with that due.Actually that is an understatement :)

You are actually the worst troll on xs, You constantly complane about people trolling and yet all you have to do is look at your own post history http://www.xtremesystems.org/forums/...rchid=20942262 Do you agree that you are trolling far more in the anand sb preview thread than the guy you are complaning about here did in this thread? We can compare posts and see who stuck to the topic in hand with there posts and offerd rebutels relavent to the subject, And who did not.

Its the same people trying to turn XS into the zone, You guys hate any negitive input in any AMD thread but just look at your posts in any Intel threads, Dont take my word, Just look.
08-30-2010, 01:42 PM
god_43

why cant we just let this thread die already...geeez gallag take it to pm man!
08-30-2010, 01:47 PM
Particle

Quote:

Originally Posted by Hornet331

Quite interesting, by that definition he wasn't a trol lat all. He provided a logical argument/question with some facts (even when they where old), yet people had no real facts to counter his spesific question (ST IPC). The only facts that where available where increased ST performance and increased IPC (not specifed if its ST or not).

Anyway personally I prefer hard numbers, so all this theoretical mindgames arn't my cup of tea.

Just so we're 100% clear, I wasn't talking about this specific case. I'm only commenting on "trolls" in general as I find them as annoying as they are pervasive.
08-30-2010, 01:56 PM
gallag

Quote:

Originally Posted by god_43

why cant we just let this thread die already...geeez gallag take it to pm man!

Hit a nerve? Again, Just look at your post history, You are one of them, All pro AMD and anti Intel, I can understand you being pro AMD but I just hate the way you guys get on peoples cases for being negitive or simple not being over positive in AMD threads yet you will go into Intel threads and do it your self???
08-30-2010, 02:08 PM
informal

gallag, I usually don't bother reading anything you post,it's just a waste of time:shrug: .Paranoia level is high,i will give you that.

Quote:

Originally Posted by AliG

right that's what I thought, because otherwise we would be seeing zero increase from core 2 to sandy bridge as primarily only the logic and prefetchers were changed

There were many core level changes ,especially in the prefetch area,one of the weaker points of 10h cores.
08-30-2010, 02:15 PM
Olivon

Fanboyz (AMD, Intel, nVidia ... whatever) are so boring ...

Is it possible to have a fair discussion here between open-minded people ?
08-30-2010, 02:16 PM
Hornet331

Quote:

Originally Posted by generics_user

only that every "fact" he postet was already debunked several posts earlier (actually in the BD news in the OP)

the 2 AGU / 2 ALU isn't genuine at all as the new units made Bulldozer wider than K8 was which was able to do only a total of 3 AGU / ALU operations at the same time; Bulldozer is cap able of doing a total of 4 agu/alu operations at the same time

Yes one module is capable of 4 agu/alu ops, but that requiers 2 threads. For single thread your down to 2/2, but with a fornt-end thats much more capable then that of K8

Quote:

Originally Posted by generics_user

additionally Single threaded IPC has to increase to make 8 cores running at 90% of their peak performance (each core in a BD module, when both cores are fully utilized, runs at 90% of the performance compared to a single BD core with an unutilized second core in its own module)
so all cores in the 150% faster statement by AMD have to run at only 90% of their peak single thread performance, which makes calculating single thread IPC even more complicated than ever before ;)

Your making a mistake, your talking about relative performance, which is not related to IPC at all or is only one part of the equation.
08-30-2010, 02:16 PM
gallag

Quote:

Originally Posted by informal

gallag, I usually don't bother reading anything you post,it's just a waste of time:shrug: .Paranoia level is high,i will give you that.

Is that the paranoia about Intel paying of anandtech you like to bring up in Intel threads when you are trying to be negitive, Could you just try not being a hypocrite? Stop going into Intel threads just to be negitive or stop complaning when people do it to AMD. And anyone can see I am not talking shi2 or being paranoide, All they have to do is look at your post history, Its not my opinion, Its all there in black and white.

I will not ruin this thead anymore, A lot of good info in it and it would be a shame for it to be locked so all I am saying is think about it guys, Are you what you say you hate?
08-30-2010, 02:20 PM
informal

What paying up of anandtech,what are you babbling about? :shrug: Where did i say that in the thread you mention?You are lost. The review @ AT was quite good .
Denial is just a one symptom of paranoia btw.

A lot of good info was lost in between 50 posts terrace alone produced in this thread,posts that were basically a beating of dead horse,posting questions that can't be answered here or even if they were(like JF did) the answers would be disregarded and trolling would continue.

Quote:

Originally Posted by Hornet331

Yes one module is capable of 4 agu/alu ops, but that requiers 2 threads. For single thread your down to 2/2, but with a fornt-end thats much more capable then that of K8

We don't know that for sure. And what was K8 capable in theory and what was possible in reality are 2 different things.
08-30-2010, 02:22 PM
radaja

gallag so true:yepp:
08-30-2010, 02:29 PM
Hornet331

Quote:

Originally Posted by informal

We don't know that for sure. And what was K8 capable in theory and what was possible in reality are 2 different things.

Why its on the chart?

Sure the forntend remains and is capable of decoding 4+1 instructions, but for singelthread int workload one core only has 2alu/agus.

There is no way bulldozer can fuse the int cores to make it act like a virtual 4alu/agu core, afair even JF denied this in this thread.
08-30-2010, 02:36 PM
informal

Quote:

Originally Posted by Hornet331

Why its on the chart?

Sure the forntend remains and is capable of decoding 4+1 instructions, but for singelthread int workload one core only has 2alu/agus.

There is no way bulldozer can fuse the int cores to make it act like a virtual 4alu/agu core, afair even JF denied this in this thread.

There won't be any "fusing" of the cores,that's not possible. But AMD is not disclosing all the details such as ,why they now call the 2 pipelines Agen?There was never in the past such a term in their diagrams.It's has always been AGU and this was paired with 1 ALU,with separate schedulers.Now we have unified scheduler and this new Agen unit ,outside of L/S unit that is also on the diagram(standing separately too).And finally we have 2 additional integer units in the FPU .SO if you want to count it you can say its 2+2+1(2) in terms of integer execution power.

edit: the only "fusing" that may happen is in terms of FPU execution,when one core can use both FMAC units for itself.
08-30-2010, 03:28 PM
spursindonesia

all i see is, AMDers are most likely proud of AMD's CPU mArch (sometime over optimist about it), and regarding Intel mArch, they admit its good but not ceding on Intel's superiority claim (sometime understating or underestimating Intel mArch capability). Intel trolls ? Well, nothing that AMD creates worth jacksh1t for 'em, that's one thing for sure. Sometime i'd like to think this forum drama as class struggle in life, beetween the bully haves and the defensive have nots, LOL. :rofl:
08-30-2010, 03:33 PM
JF-AMD

Quote:

Originally Posted by informal

There won't be any "fusing" of the cores,that's not possible. But AMD is not disclosing all the details such as ,why they now call the 2 pipelines Agen?There was never in the past such a term in their diagrams.It's has always been AGU and this was paired with 1 ALU,with separate schedulers.Now we have unified scheduler and this new Agen unit ,outside of L/S unit that is also on the diagram(standing separately too).And finally we have 2 additional integer units in the FPU .SO if you want to count it you can say its 2+2+1(2) in terms of integer execution power.

edit: the only "fusing" that may happen is in terms of FPU execution,when one core can use both FMAC units for itself.

In current architecture our pipelines are shared between ALU and AGU. With bulldozer we actually break them out and make them dedicated, 2 for each.

Different engineers write things different ways. It is not that "AMD is changing what we call them" but that an engineer wrote it that way. Marketing tends to refrain from editing technical slides as they know more than us in that area.
08-30-2010, 04:16 PM
Hans de Vries

Our friend who goes by the name dougsf30/terrace215/chipper/chipdesigner/tatertot/justaview/gloo...
and 100 more names has a history of driving people nuts (and maybe himself as well...)

To recapitulate this thread:

AMD Architects : IPC increases (Anand article commenting on the 2 ALUs an 16KB L1)

terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!! instead of getting worse.

terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!!!! You are spreading FUD

terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, AMD has given up improving IPC.

JF-AMD posting: IPC increases!!!!!!! How many times did I tell you!!!

forever{
terrace215 post: IPC decreases, because .....
terrace215 post: IPC decreases, says .... of AMD
terrace215 post: IPC decreases, according to AMD's presentation.
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD has given up improving IPC.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
.....}
until (interrupt by Movieman)

Regards, Hans
08-30-2010, 04:24 PM
Mechromancer

^^^LOL! That is the most epic post EVER! So very very true.
08-30-2010, 04:31 PM
nn_step

Quote:

Originally Posted by Hans de Vries

Our friend who goes by the name dougsf30/terrace215/chipper/chipdesigner/tatertot/justaview/gloo...
and 100 more names has a history of driving people nuts (and maybe himself as well...)

To recapitulate this thread:

AMD Architects : IPC increases (Anand article commenting on the 2 ALUs an 16KB L1)

terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!! instead of getting worse.

terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!!!! You are spreading FUD

terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, AMD has given up improving IPC.

JF-AMD posting: IPC increases!!!!!!! How many times did I tell you!!!

forever{
terrace215 post: IPC decreases, because .....
terrace215 post: IPC decreases, says .... of AMD
terrace215 post: IPC decreases, according to AMD's presentation.
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD has given up improving IPC.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
.....}
until (interrupt by Movieman)

Regards, Hans

Correction

while(!interrupted)
{
cout << "terrace215 post: " << random(bull_sh1t_reason) << endl;
}
08-30-2010, 04:33 PM
Movieman

Quote:

Originally Posted by Hans de Vries

Our friend who goes by the name dougsf30/terrace215/chipper/chipdesigner/tatertot/justaview/gloo...
and 100 more names has a history of driving people nuts (and maybe himself as well...)

To recapitulate this thread:

AMD Architects : IPC increases (Anand article commenting on the 2 ALUs an 16KB L1)

snip~
.....}
until (interrupt by Movieman)

Regards, Hans

Hello Hans.
Are you sure of all those names at the top of your post?
The reason I ask is that I got a "holier than thou" multi PM response from him after I removed his access to News and AMD section.
Yes, I chuckled too at your post!:D

Oh, forgot,no one drives me nuts. I just smile, grab my hammer and hit them upside the head so hard their grandchildren will walk with a 15degree list.:p:
08-30-2010, 04:35 PM
informal

"The more I post the more it decreases." part is the critical point the code above,cracked me up :D .
That was truly an epic post Hans :)
08-30-2010, 04:45 PM
Motiv

Quote:

Originally Posted by JF-AMD

In current architecture our pipelines are shared between ALU and AGU. With bulldozer we actually break them out and make them dedicated, 2 for each.

Different engineers write things different ways. It is not that "AMD is changing what we call them" but that an engineer wrote it that way. Marketing tends to refrain from editing technical slides as they know more than us in that area.

Being an absolute noob, could someone explain this to me.

How many pipelines are on the P2 (x4 for arguments sake), how do they feed the ALU & AGU normally.

To me it looks like bulldozer has cut down by 1 ALU&AGU per 'core'.
08-30-2010, 04:49 PM
Movieman

Quote:

Originally Posted by Motiv

Being an absolute noob, could someone explain this to me.

How many pipelines are on the P2 (x4 for arguments sake), how do they feed the ALU & AGU normally.

To me it looks like bulldozer has cut down by 1 ALU&AGU per 'core'.

I'll let you know when I get my hands on a pair of the unobtainable model 7196SE BD 16 core cpu's that run at 4GHz..:rofl:
08-30-2010, 04:50 PM
AliG

Quote:

Originally Posted by Hans de Vries

Our friend who goes by the name dougsf30/terrace215/chipper/chipdesigner/tatertot/justaview/gloo...
and 100 more names has a history of driving people nuts (and maybe himself as well...)

To recapitulate this thread:

AMD Architects : IPC increases (Anand article commenting on the 2 ALUs an 16KB L1)

terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!! instead of getting worse.

terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.Y confesses this.

JF-AMD posting: IPC increases!!!! You are spreading FUD

terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, AMD has given up improving IPC.

JF-AMD posting: IPC increases!!!!!!! How many times did I tell you!!!

forever{
terrace215 post: IPC decreases, because .....
terrace215 post: IPC decreases, says .... of AMD
terrace215 post: IPC decreases, according to AMD's presentation.
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD has given up improving IPC.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
.....}
until (interrupt by Movieman)

Regards, Hans

you sir, have earned prime location on my signature.

It's free too! Gotta cherish those things as overclocking no longer is..
08-30-2010, 04:54 PM
Motiv

Quote:

Originally Posted by Movieman

I'll let you know when I get my hands on a pair of the unobtainable model 7196SE BD 16 core cpu's that run at 4GHz..:rofl:

well they say it has a longer pipeline, so in my world...

..a longer pipeline means at least 5ghz on air :shocked: *

*I can but dream
08-30-2010, 05:03 PM
informal

Quote:

Originally Posted by Motiv

Being an absolute noob, could someone explain this to me.

How many pipelines are on the P2 (x4 for arguments sake), how do they feed the ALU & AGU normally.

To me it looks like bulldozer has cut down by 1 ALU&AGU per 'core'.

Agner Fog's microarchitecture.pdf is a good place to start.It has a part where it tries to identify the bottlenecks in every major x86 design today,so there is 10h(or wrongly called K10). Essentially 10h can in theory do a massive of 9(nine) "micro ops"* but retire only 3 "macro ops"** . There is a bottleneck in the retirement part of the design(but the utilization of 9 units can't be effectively measured in real world as the document says;it is clear that some of the time exec. units are underutilized ,especially 3rd AGU which is redundant due to 2 ports to L1D cache).

*macro op is split into these micro instructions and then sent to execution units
**macro op is an instruction the decoder deals with;1 x86 instruction typically = 1 or 2 macro ops

edit:
continued on to Bulldozer
Front end can take up 4 x86 instructions(can't tell what is the relation to the RISC like macro ops in 10h decoder stage) and dispatch it in 2 groups of 4(macro ops?). Each integer core can do 4 instructions (2 arithmetic and 2 address,but the Agen unit can maybe do some math work too ). Still a lot is unknown so we can't say what else is in there and how AMD organized it.At least not until launch .
08-30-2010, 05:32 PM
god_43

Quote:

Originally Posted by nn_step

Correction

while(!interrupted)
{
cout << "terrace215 post: " << random(bull_sh1t_reason) << endl;

cin >> wait_responses;

if (wait_responses = true) {

cout << "terrace215 post: " << random(spout_more_sh1t) << endl;

}

}

fixed...although might not work well if it was a real program ;p.
08-30-2010, 05:43 PM
nn_step

Quote:

Originally Posted by god_43

fixed...although might not work well if it was a real program ;p.

wait for response isn't required, since it is apparent that such activity doesn't actually exist. [At least in most of the posts made]
08-30-2010, 05:47 PM
qcmadness

Quote:

Originally Posted by Motiv

Being an absolute noob, could someone explain this to me.

How many pipelines are on the P2 (x4 for arguments sake), how do they feed the ALU & AGU normally.

To me it looks like bulldozer has cut down by 1 ALU&AGU per 'core'.

http://www.xbitlabs.com/articles/cpu...0_6.html#sect0

Quote:

Upon the availability of data, the scheduler may issue one integer operation to ALU and one address operation to AGU from each queue. There can be maximum two simultaneous memory requests. So, up to 3 integer operations and 2 memory operations (64-bit read/write in any combination) may be issue for execution per clock. Micro-operations from various arithmetic MOPs are issued for execution from their queues in an out-of-order manner, depending on the readiness of the data.
08-30-2010, 06:44 PM
jtdigital

isn't the bulldozer going to be released in 2nd quarter 2011 when the sandybridge 8 core arrives to do battle? :D
08-30-2010, 07:02 PM
Hans de Vries

Quote:

Originally Posted by qcmadness

http://www.xbitlabs.com/articles/cpu...0_6.html#sect0

page 251 of: http://support.amd.com/us/Processor_TechDocs/25112.PDF

Quote:

A.3 Superscalar Processor

The AMD Athlon 64 and AMD Opteron processors are aggressive, out-of-order, three-way
superscalar AMD64 processors. They can fetch, decode, and issue up to three AMD64 instructions
per cycle with a centralized instruction control unit (ICU) and two independent instruction
schedulers—an integer scheduler and a floating-point scheduler. These two schedulers can
simultaneously issue up to nine micro-ops to the three general-purpose integer execution units
(ALUs), three address-generation units (AGUs), and three floating-point execution units. The
processors move integer instructions down the integer execution pipeline, which consists of the
integer scheduler and the ALUs, as shown in Figure 6 on page 252. Floating-point instructions are
handled by the floating-point execution pipeline, which consists of the floating-point scheduler and
the floating-point execution units.

or alternatively:

http://www.chip-architect.com/news/2...Core.html#1.20

But don't forget that the average number of ALU instructions is something like 0.4/cycle
which is 4, 5 times less as two ALUs can provide.

Regards, Hans
08-30-2010, 07:20 PM
blindbox

Quote:

Originally Posted by Hans de Vries

forever{
terrace215 post: IPC decreases, because .....
terrace215 post: IPC decreases, says .... of AMD
terrace215 post: IPC decreases, according to AMD's presentation.
terrace215 post: IPC decreases, don't trust marketing guys.
terrace215 post: IPC decreases, because of the 2 ALUs..
terrace215 post: IPC decreases, the marketing guy isn't talking about IPC
terrace215 post: IPC decreases, because of the 16KB caches
terrace215 post: IPC decreases, AMD has given up improving IPC.
terrace215 post: IPC decreases, The AMD architect says it decreases by 5%
terrace215 post: IPC decreases, Bulldozer is only optimized for server workloads.
terrace215 post: IPC decreases, AMD presentation sheet no.X tells us so.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
terrace215 post: IPC decreases, The more I post the more it decreases.
.....}
until (interrupt by Movieman)

Regards, Hans

You've summed it up better than we all could.
08-30-2010, 07:23 PM
god_43

Quote:

Originally Posted by nn_step

wait for response isn't required, since it is apparent that such activity doesn't actually exist. [At least in most of the posts made]

lool thats true..i have failed. cast out of troll programming school : (.

on topic. yeah its supposed to be 2011 q2, should be fun!
08-30-2010, 07:26 PM
JF-AMD

Quote:

Originally Posted by god_43

lool thats true..i have failed. cast out of troll programming school : (.

on topic. yeah its supposed to be 2011 q2, should be fun!

on topic, it is 2011. that is all that has ever been said.
08-30-2010, 09:45 PM
JumpingJack

Guys ... David has posted a terrific summary of Bulldozer ... http://www.realworldtech.com/page.cf...2610181333&p=1
08-30-2010, 10:12 PM
tifosi

Quote:

Originally Posted by Movieman

Hello Hans.
.... Oh, forgot,no one drives me nuts. I just smile, grab my hammer and hit them upside the head so hard their grandchildren will walk with a 15degree list.:p:

:rofl:

I honestly am waiting like thousands more to get a sneak peak... :P I don't live in that city which i mentioned earlier with the cave running the (early sample) hardware in question... or i'd have had done anything, akin to indiana jones (which is lamo me thinks) to get to the 16 core unobtanium-optronium! :P
08-30-2010, 11:01 PM
-Boris-

Quote:

Originally Posted by Hornet331

Yes one module is capable of 4 agu/alu ops, but that requiers 2 threads. For single thread your down to 2/2, but with a fornt-end thats much more capable then that of K8

Your making a mistake, your talking about relative performance, which is not related to IPC at all or is only one part of the equation.

No, a BD Core has 2 ALUs AND 2 AGUs available. 2+2=4. A Phenom II has 3 ALUs OR 3 AGUs. 6/2 = 3.

EDIT:
And PLEASE, can we dedicate this thread to Bulldozer and not forum moderation? I too welcome the ban, but I'm sure we got enough criticism and back-patting here. There are other places we can continue doing that. :)
08-31-2010, 12:06 AM
[XC] Oj101

I heard via the grapevine that it'll be 1H2011 for server, 4Q2011 for desktop :(
08-31-2010, 12:44 AM
ajaidev

Quote:

Originally Posted by JumpingJack

Guys ... David has posted a terrific summary of Bulldozer ... http://www.realworldtech.com/page.cf...2610181333&p=1

nice article by David and thanks for the heads up...:up:
08-31-2010, 12:51 AM
geo

Quote:

Originally Posted by Oj101

I heard via the grapevine that it'll be 1H2011 for server, 4Q2011 for desktop :(

:( come on AMD make it the other way round :P
08-31-2010, 12:54 AM
-Boris-

Quote:

Originally Posted by geo

:( come on AMD make it the other way round :P

Might see a Bulldozer FX at the same time as the server chips. ;)
08-31-2010, 02:22 AM
informal

Quote:

Originally Posted by JumpingJack

Guys ... David has posted a terrific summary of Bulldozer ... http://www.realworldtech.com/page.cf...2610181333&p=1

Thanks,that is a great article.
08-31-2010, 02:24 AM
savantu

Quote:

Originally Posted by -Boris-

No, a BD Core has 2 ALUs AND 2 AGUs available. 2+2=4. A Phenom II has 3 ALUs OR 3 AGUs. 6/2 = 3.

..

K10 has 3 ALUs and 3 AGUs. No matter how hard you and others try to downplay K10 execution resources, fact is, a K10 integer core has more resources than a BD integer core.

The docs linked by Hans are pretty clear.

http://www.xtremesystems.org/forums/...&postcount=681
08-31-2010, 02:33 AM
informal

Bobcat is 2way(2ALU+2AGU) design,has 90% of Propus and is a low power design with solid perfromance.One can expect Bulldozer core to stump over Bobcat core but both have less ALUs/AGUs than 10h. Number of units means nothing if you can't effectively use them and you know that.The number of core level changes is pretty big,from L/S improvements,prefetch,BP,shared L2 etc..As Anand wrote(info from AMD) ,per core performance will be better than 10h.
08-31-2010, 03:07 AM
JF-AMD

Quote:

Originally Posted by savantu

K10 has 3 ALUs and 3 AGUs. No matter how hard you and others try to downplay K10 execution resources, fact is, a K10 integer core has more resources than a BD integer core.

The docs linked by Hans are pretty clear.

http://www.xtremesystems.org/forums/...&postcount=681

No, you are wrong. Old architecture has shared resources, new architecture has dedicated resources.

A BD integer core will do more IPC and perform single threads faster than an old core.

Why do you keep saying these things even though I have posted the information in multiple places?
08-31-2010, 03:19 AM
freeloader

Quote:

Originally Posted by JF-AMD

No, you are wrong. Old architecture has shared resources, new architecture has dedicated resources.

A BD integer core will do more IPC and perform single threads faster than an old core.

Why do you keep saying these things even though I have posted the information in multiple places?

JF...have you personally seen running BD chips yet or whatever the server variant is called? Just wondering how you're so sure if you haven't bench tested one yet.

Does anyone here know when BD compatible socket motherboards will go on sale?
08-31-2010, 03:24 AM
STaRGaZeR

Quote:

Originally Posted by JF-AMD

No, you are wrong. Old architecture has shared resources, new architecture has dedicated resources.

He's right. K10 has more resources, shared or not.
08-31-2010, 03:29 AM
-Boris-

Quote:

Originally Posted by freeloader

JF...have you personally seen running BD chips yet or whatever the server variant is called? Just wondering how you're so sure if you haven't bench tested one yet.

Does anyone here know when BD compatible socket motherboards will go on sale?

I'm pretty sure that when you have the position JF has in a company you get pretty accurate numbers from engineering and so on. There is no need for him to sit down and bench engineering samples personally. Would be quite stupid if engineering lied about the performance in internal reviews and documents.
You know this isn't Dilbertland right? ;)
08-31-2010, 03:31 AM
-Boris-

Quote:

Originally Posted by STaRGaZeR

He's right. K10 has more resources, shared or not.

If you can't use it it isn't a resource. Phenom has only three integer pipes. In one of those pipes the AGU and ALU have to take turns being part of the resource pool.
08-31-2010, 03:34 AM
informal

10h can retire 3 macro ops.BD integer core/fp core should be able to do 4.

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