AMD's 3GHz K10 to break 30,000 3DMark06 (Inq)

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Originally Posted by LOE

Yes IT IS

K8 was developed keeping dual cores in mind, but by the time K8 launched there was no demand for dual core chips, and chips ware pretty big themselves.

But due to the fact K8 was designed to be a dual core, amd launched X2 without the need to develop a new core. Intel couldn't offer a native dual core chip based on netburst simply cause the core was lacking core interconnects interface, even the cores of the monolithic 840EE communicated with each other through the FSB, like the later MCM pendium Ds did.

Native is better in terms of performance, x2 scales better than PentiumD, but chips are larger and yields - lower. MCM is more flexible and probably the better way to do things. I think amd go for the native stuff cause they want to cut development costs. Of course intels approach was lame - using the FSB for core to core communication. AMD could have used HT to make MCM modules and they would have been very close to a native design.

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It depends how you define native dualcore. X2 is just 2 totally seperate cores with a shared SRI thats basicly its northbridge. In "nativeness" you would have C2D>CD>X2>Presler>Smithfield.

Also native doesnt mean it scales better by default. A C2D doesnt scale superiour to X2. Tho its just as more native to K8, that K8 is to P4.

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Originally Posted by hipro5

:D :yepp:

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hey george
looks like i'll be able to fend off these new CPUs with a Celeron :shocked: :D
http://www.xtremesystems.org/forums/...d.php?t=157673

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Originally Posted by LOE

But due to the fact K8 was designed to be a dual core, amd launched X2 without the need to develop a new core. Intel couldn't offer a native dual core chip based on netburst simply cause the core was lacking core interconnects interface, even the cores of the monolithic 840EE communicated with each other through the FSB, like the later MCM pendium Ds did.

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Actually all intercore communications in x2 K8 goes through the main memory just like in Pentium D.
http://www.xbitlabs.com/articles/cpu...nalysis_4.html
So, I have to state that I can’t find any indication of direct data transfers from one execution core to another in the Athlon 64 X2 processor. According to my tests, the most recent copy of data is always read from system RAM. This must be a limitation of the MOESI protocol implementation. The following seems to happen when data are accessed: on receiving a read request probe read that the second core puts on the system bus, the first core performs a write-back of the modified cache line into memory. After this write or at the same time with it, the requested line is transferred to the second core. If the data in the first core’s cache haven’t been modified, they are read from system RAM. Why is there no direct transfer between the cores via the crossbar switch? Ask AMD’s engineers about that! :)

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Originally Posted by kl0012

Actually all intercore communications in x2 K8 goes through the main memory just like in Pentium D.
http://www.xbitlabs.com/articles/cpu...nalysis_4.html
So, I have to state that I can’t find any indication of direct data transfers from one execution core to another in the Athlon 64 X2 processor. According to my tests, the most recent copy of data is always read from system RAM. This must be a limitation of the MOESI protocol implementation. The following seems to happen when data are accessed: on receiving a read request probe read that the second core puts on the system bus, the first core performs a write-back of the modified cache line into memory. After this write or at the same time with it, the requested line is transferred to the second core. If the data in the first core’s cache haven’t been modified, they are read from system RAM. Why is there no direct transfer between the cores via the crossbar switch? Ask AMD’s engineers about that! :)

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QFT!

Barcelona will connect to an L3 the same same way. Last thing I saw said there wasn't any Core to Core, L1 to L1 or even L2 to L2 interconnections. Each are separate Core that can run without the rest of the system or cores. You can't split a C2D like that. Sure two Cores that make up C2Q is different.

If K10 is faster and IHMO it will be in some apps, it will be faster because of its Core Improvements, not some Native BS. Singled threaded app/s should bare this out. These type apps will shoe the improvement made to each core. The problem is AMD's marketing folks would rather talk Catch Prases since that easier to grasp. IMHO, that's disrespecting the folks who love them. That's like saying our fans are Dumb so let's give them something simple.

I see the off topic discussion is going rampant again..Hmm,mods must have a day off :)

Back on K10 topic.New info is coming out,this time with some AMD slides

Inside AMD K10 Architecture

Some new info from here:
http://www.hardwaresecrets.com/article/480/1

From this page :http://www.hardwaresecrets.com/article/480/5 of the article we have a glimpse of 45nm offerings(all with some new codenames as Suzuka 45nm quad core based on Shangai :))

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Here is a quick summary of the cores that will be launched for the server market based on K10 architecture:
Barcelona: quad- or dual-core Opteron on the 2000 and 8000 series, 512 KB L2 memory cache per core, 2 MB L3 memory cache, registered DDR2 memory, socket 1207 (socket F), HyperTransport 1.x, 65 nm manufacturing process.
Budapest: dual-core Opteron on the 1000 series, 512 KB L2 memory cache per core, 2 MB L3 memory cache, conventional DDR2 memory, socket 1207 (socket F), HyperTransport 1.x or 3.0, 65 nm manufacturing process.
Shanghai: quad- or dual-core Opteron on the 2000 and 8000 series, 512 KB L2 memory cache per core, 6 MB L3 memory cache, registered DDR2 memory, socket 1207 (socket F), HyperTransport 1.x, 45 nm manufacturing process.
Montreal: octal- or quad-core Opteron on the 2000 and 8000 series, 1 MB L2 memory cache per core, 6 MB or 12 MB L3 memory cache, registered DDR3 memory, socket G3, HyperTransport 1.x, 45 nm manufacturing process.
Suzuka: quad- or dual-core Opteron on the 1000 series, 512 KB L2 memory cache per core, 6 MB L3 memory cache, conventional DDR3 memory, socket AM3, HyperTransport 3.0, 45 nm manufacturing process.

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From here we can see the uni vs split power plane difference in K10 Barcelona:
http://www.hardwaresecrets.com/imageview.php?image=7812


Here is a Phenom desktop line up:

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Here is a quick summary of the cores that will be launched for the desktop market based on K10 architecture:
Spica: A single-core Sempron LE CPU, with 512 KB L2 memory cache, regular DDR2 memory, HyperTransport 3.0 and socket AM2+.
Rana: Dual-core Athlon X2 LS CPU, with 512 KB L2 memory cache per core, L3 memory cache (value not disclaimed) regular DDR2 memory, HyperTransport 3.0 and socket AM2+.
Kuma: Dual-core Phenom X2 CPU, with 512 KB L2 memory cache per core, 2 MB L3 memory cache, regular DDR2 memory, HyperTransport 3.0 and socket AM2+.
Agena: Quad-core Phenom X4 CPU, with 512 KB L2 memory cache per core, 2 MB L3 memory cache, regular DDR2 memory, HyperTransport 3.0 and socket AM2+.
Agena FX: Quad-core Phenom FX CPU, with 512 KB L2 memory cache per core, 2 MB L3 memory cache, regular DDR2 memory, HyperTransport 3.0 and socket AM2+ or socket 1207+.

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And finally the roadmap(showing the Dual Core Rana clearly as Stars core and NOT the RevG derivative as some earlier suggested)
http://www.hardwaresecrets.com/imageview.php?image=7813

Server roadmap:
http://www.hardwaresecrets.com/imageview.php?image=7822

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Originally Posted by STaRGaZeR

Don´t be a fool. Neither Smithfield or Presler are native dual cores, they are MCMs of Prescott and Cedar Mill.

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Maybe you should do some research before talking out of your south pole....;)

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Originally Posted by MR_SmartAss

So the highest clocked K10 would be the 2.4GHz at launch. Well, thats a bad news.

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Umh , no.

IIRC the highest part will be 2GHz~95w and higher clocked ones will arrive in Q4 ( nov-dec ).

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Originally Posted by MR_SmartAss

So the highest clocked K10 would be the 2.4GHz at launch. Well, thats a bad news.

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First,who said 2.4Ghz will be the launch freq.?And if it is ,why is it a "bad news"?You know how K10 performs,show us the review..:rolleyes:

Second,latest informations suggest 2.2Ghz at launch,not 2.4Ghz.The higher clocked versions for servers are due out in late October.

2.4 at launch is certainly better than 2.0 at launch, so I'm happy :)

Unfortunately that probably won't be enough to beat a 3.33ghz yorkfield :(

Ok,don't show me the benches( like you would know..)

Also,the picture does show the launch speeds BUT it doesn't say if they will be mass available in 6 days.They could announce 2.4Ghz and launch it in late Sept./early October
You need to understand that there will be huge demand for these parts in server market and AMD must supply enough(not only for 2.4Ghz,for all K10 models)
So the lower clock scenario is more likely since most will want the best perf./watt/$ K10 can offer ,and it will surely be the 2Ghz version.No doubt about the fact that 2.4Ghz would look much better if it is available in 6 days(which it could btw,we simply don't know ATM)

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Originally Posted by informal

They could announce 2.4Ghz and launch it in late Sept./early October

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Gee, a paper launch. That would be so like AMD. :rolleyes:

Yeah,whatever works for you...

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Originally Posted by informal

You know how K10 performs

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Originally Posted by MR_SmartAss

Yes.

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:rofl: :ROTF:

FINALLY

BARCELONA REVIEW

From msimax's link :D

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Understanding the artistic and socioeconomic roots of extravant Barcelona architecture

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:rofl:

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Originally Posted by LOE

very funny, but we have barcelona benches for a long time now...

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Only the first few pages though :p:

We need more posts !!! if you google K10 then you surely will enter extreme forums :p

-First a 3 GHZ Phenom is NOT an overclock one

http://www.hothardware.com/News/30GH...sFire_Spotted/

http://www.youtube.com/watch?v=R7EZmYth6TM

-Second a 2 GHZ Barcelona beats a 2.33 GHZ Clovertown in Floating-Point

http://www.vnunet.com/tv/?channel=vn...86_vnunet_0096

AMD 2 GHZ FP =78

Intel 2.33 GHZ FP =60

-Third something nice to see easy swapping cpu's from duo-core to quad-core

http://youtube.com/watch?v=SYvupXNmaKQ

-Fourth i DONT believe that the Phenom can do 30,000 in 3dmark06 even with trifire.
sure it's going to be a powerfull cpu but not by that much i think it will have not problem beating the c2q by about 10-30% & i doubt ,it would be more then that.

-Fifth i think that's enough ,for now anyway :D

Some more news here,
http://www.eetimes.com/news/latest/s...leID=201804214
Half way through performance of Barcelona is mentioned.

Goodman...specfp_rates is not floating point as such. Its heavy memory bandwidth floating point bench. If it should beat it in floatingpoint it would be specfp without rates on.

K8 today already beat Core 2 in SpecFp_rates. But Core 2 beats K8 in specfp.

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Originally Posted by Shintai

Goodman...specfp_rates is not floating point as such. Its heavy memory bandwidth floating point bench. If it should beat it in floatingpoint it would be specfp without rates on.

K8 today already beat Core 2 in SpecFp_rates. But Core 2 beats K8 in specfp.

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I'll take your word for it because i dont know much about specfp benchmarks , only the ones for desktop pc , 3dmark , sandra etc..