There is no maximum spec for PHASE spike below GND,
however, there is an absolute maximum rating for (BOOT
PHASE) of 7V; exceeding this limit can cause damage to t
IC, and possibly to the system. Since the BOOT signal is
typically 5V above the PHASE node most of the time, it on
takes a few volts of a spike on either signal to exceed the
limit. A good design should be characterized by using the
math function or differential probe, and monitoring these
signals for compliance, especially during full loads, where
the signals are usually the noisiest.
If the power efficiency of the system is important, then other
FET parameters are also considered. Efficiency is a
measure of power losses from input to output, and it
contains two major components: losses in the IC (mostly in
the gate drivers) and losses in the FETs. Optimizing the sum
involves many trade-offs (for example, raising the voltage of
the gate drivers typically adds power to the IC side, but may
reduce some power on the FET side). For low duty cycle
applications (such as 12V in to 1.5V out), the upper FET is
usually chosen for low gate charge, since switching losses
are key, while the lower FET is chosen for low R
,
DS(ON)
since it is on most of the time. For high duty cycles (such as
3.3V in to 2.5V out), the opposite is true.
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Originally Posted by nn_step
Is it safe to put a heatsink on them.. say a cut up AXP heatsink?
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