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Samples in 2010, but 2011 for 32nm products.
http://phx.corporate-ir.net/phoenix....rol-analystday
Look at Rick Bergman's pdf presentation.
Still vague about Bulldozer timing, nothing more than "2011" (products) and "2010" (samples).
Possibly more during afternoon "breakout sessions"
lets hope AMD didn't plan on using GF to manufacture the 6800's.
It's not a fresh news... :rolleyes:Quote:
Originally Posted by terrace215
It was 2011 since last analyst day,so nothing changed apparently.Quote:
Originally Posted by terrace215
BTW,bulldozer is now confirmed to be AM3 compatible ,a huge plus.
http://img233.imageshack.us/img233/2659/desktopoe.png
And he said about Bulldozer "very highend" platform
informations are dispersing over few threads (http://www.xtremesystems.org/forums/...=232784&page=6) (http://www.xtremesystems.org/forums/...d.php?t=238693)
I urge mods to create dedicated "AMD Analyst day 2009" thread and merg all other posts and threads in it!
32nm products only in 2011 is a bit of news, at least if all this year you've been listening to AMD's misleading talk about their 32nm "ramping" in 2010. Of course, what they left deliberately vague was the fact that this "ramp" was not a production ramp, hoping folks would think they'd have 32nm PRODUCTS in 2010.Quote:
Originally Posted by Oliverda
Then, at the last CC we got "deep in the back half of 2010", i.e. Q4, for production STARTS, which fits with 2011 32nm products.
So, at this point, 1 to 1.25 years behind Intel on 32nm revenue shipments, despite the bluster about "closing the gap" that they provide every couple years.
http://img137.imageshack.us/img137/1289/29226078.png/Quote:
Originally Posted by terrace215
Q3 production starts and by the end of 2010 shipment of products.
Thuban six core(Leo platform) is now Q2 2010,a pull in again(they say H1 so it can be Q1 i guess,but unlikely).It was Q3 in last product roadmap 2 months ago.
http://img137.imageshack.us/img137/4151/92275007.png
They stated that 32nm SOI SHP yields will be ~50% by the year's end
Update on the BD cores,now i read it is 4x4way cores :shock:,not 2x2way as dresdenboy speculated(shame on him /joke :) ).
Misleading? What kind of misleading are you talking about? :rolleyes: The AMD has never told that they will have 32nm CPU in the market in 2010.Quote:
Originally Posted by terrace215
A slide from the previous year:
http://www.techpowerup.com/reviews/A...images/26k.jpg
Good morning...
when you consider that some of the "legends" of this forum like Shintai firmly believed that Bulldozer will not be on market before the end of 2012... yeah guess you're right than, this "piece of info" that you've put on thread title is important...Quote:
Originally Posted by terrace215
On the other side, fact that there are bunch of old posts on this forum with God-knows-when leaked AMD roadmaps stating that Zambezi is out in 2011... then your's "add-on" in thread title is really pointless!
But then again apparently you were the one who didn't folow those posts and roadmaps
Also when AMD spoke about ramping up 32nm in 2010 AMD meant production 'cos at that time AMD owned production....
Bottom line Bulldozer EVT and ES products are coming in 2010, so your thread title IS pointless!
Mmm, no.Quote:
Originally Posted by informal
I direct you to:
This time around I’d expect as I said the ramp to start deep in the back half of next year.
That's the CEO, Dirk, saying this last month:
http://seekingalpha.com/article/1668...e=-1&find=deep
And, "back half" = H2, "deep in the back half" = Q4, not Q3.
And, of course, no products til 2011. AMD claims about 10 weeks from start to out, so 2011 products fits with starts in Q4 2010 or later.
Remember we're talking about AMD, not the GloFo foundry, whatever that bar means.
EVT samples are Q4 2010 for BD cores ,so it doesn't matter what date it is exactly.Products are 2011 like it was known for a year now.
BD cores look like a game changer,2 shared int units,256b wide FPU,APU support,advanced clock gating and Turbo functionality,platform longevity(G34 and MA3 compatible).
EVT and ES samples are not products, nor were they that specific about WHAT level of sample they hope to provide in 2010. :ROTF:Quote:
Originally Posted by Nedjo
I wouldn't be surprised to see Bulldozer products slip to Q1 2012, actually. Best case is probably Q3 2011. There's a lot of verification work that needs to happen for a new server part, even once they've debugged and tuned the silicon.
Yeah they could have said it's Q3 2013 and when they launch it in H1 2011 they can say we overdelivered by 2 years! :rolleyes:
informal, don't go in to this pointless arguing with some one who is obviously misinterpreting pure facts, and hoping that AMD will slip Bulldozer to an "Apocalypse year" :)Quote:
Originally Posted by informal
come here and give us more info from the analyst day: http://www.xtremesystems.org/forums/...d.php?t=238702
This kind of misleading:Quote:
Originally Posted by Oliverda
http://www.informationweek.com/news/...SSfeed_IWK_All
There's Dirk telling folks they'll be ramping up 32nm production in mid-2010 with VOLUME in Q4!
All the fans went wild when that was announced... but, no, sorry, just the usual AMD spin labeling their "sampling period" as "ramping up", but leaving it vague on purpose.
Q&A,Bergam hints that they are doing the BD tape-out at the start of the next year and having silicon in H1 2010 for testing purposes.
I highly suspect they already taped out BD samples at 45nm and verified the design works as it should so the job now is to "just" shrink it to a new node.Remember BD design was 2009 and 45nm without AVX. The delay is logical looking at things from this POV.
No, they can't. New arch in 2013 isn't something they can tell to shareholders. In fact theirs predictions lately were a bit optimistic (like a 30% of market share in 2009).Quote:
Originally Posted by informal
Roadmaps are not law/set in stone, if things go good and they can pull things in if things go bad they extend the roadmap out to a later date, its part of planning.
I see you swallowed AMD's marketing meme for this Analyst Day. "Changing the game"... "game changer"... :rofl:Quote:
Originally Posted by informal
Lately they've also been saying that performance benchmarks don't really matter....
Uh Oh.
http://blogs.amd.com/work/2009/10/09...st-benchmarks/
I highly suspect you are wrong, but that does make for some nice wishful thinking.Quote:
Originally Posted by informal
Ok.Relax now,listen to the webcast and don't be so negative :p:
Lets move the talk to here -> http://www.xtremesystems.org/forums/...d.php?t=238702
Thanks!
Yeah, this thread is full of wishful thinking. Like that BD might come out in 2012. Lol.Quote:
Originally Posted by terrace215
I can't see a single quote in the article where Meyer states this. :rolleyes:Quote:
Originally Posted by terrace215
From the link, the first paragraph:Quote:
Originally Posted by Oliverda
Dirk Meyer, chief executive of Advanced Micro Devices, said Friday the chipmaker plans to "ramp up" production of next-generation 32-nanometer processors in the middle of next year with volume production starting in the fourth quarter.
More information from GloFo slides: http://phx.corporate-ir.net/External...xUeXBlPTM=&t=1
The left side of the bar represents RISK production (!). This is the time that you stop running test vehicles through a process and start running the first customer designs. Meaning customers get back first silicon samples. So *that* is what GloFo is promising AMD for Q3 2010. First 32nm silicon. No wonder all the 32 products are listed as 2011.
See the 6th slide.
just like they were listed 367 days ago:Quote:
Originally Posted by terrace215
http://www.techpowerup.com/reviews/A...images/26k.jpg
so I guess your definition of news is anything that can be fitted in that number of days?
:rolleyes:
I believe the bold part is wrong.First silicon samples are not risk production.First silicon samples are being done now(test wafers) and Bergam said first BD samples will be early next year.So by the end of the next year they will have EVT samples ready and H1 2011 is a logical target for launch (both server and client).Quote:
Originally Posted by terrace215
AMD definitely full of win... in creating colorfull slides. :p: They are chempions in that. I remeber similar presentation before Barcelona intro. Yet I don't deny that Bulldozer may be well a great success.Quote:
Originally Posted by Mechromancer
Like i said a few posts back,Bergam let it slip that BD cores may already be taped out or set to tape out soon:
http://www.semiaccurate.com/2009/11/...rth-has-moved/
Quote:
Bulldozer has taped out, the earth has moved
More analyst day dirt dug up
by Charlie Demerjian
November 11, 2009
THREE VERY INTERESTING tidbits snuck out in the Q&A session at the AMD analyst day today. It seems that Fusion and the new cores have taped out and are at the fabs.
The new cores were said to begin sampling to OEMs in 2010. When pressed on the timing of tapeouts, one AMD spokesperson said that the fabs were 'running product now'. That means the chips have taped out and the fun is about to begin.
Next up was the process the Fusion cores will be on. The first of them will be made on a silicon-on-insulator (SOI) process, something that makes a lot of sense. It is much easier to port a GPU from bulk silicon to SOI than to do things the other way around. The answer did not preclude bulk silicon variants of Fusion in the future, but since the first generation cores are not made on it, I would not expect that to happen for a while.
The last bit was confirmation of what we have know, or at least have strongly suspected for a while, that the first generation of Fusion products will be a 'stars' core. The optimistic view of this is that AMD is reusing the old K10 variant for time to market reasons. Basically the uncore was done first, and since it is modular, why not use it?
If you are pessimistic, you could see this as the Bulldozer and Bobcat cores being massively late. Given that they were on the roadmap for 45nm and delayed about 2 years ago to 32nm, this has a ring of truth to it. Because it was a planned move, and one that rationalizes a likely untenable earlier schedule, I don't think this is a delay, or even a bad thing. The 'delay' probably avoided another "Barcelona".
In the end, it looks like AMD is on track. 2010 will likely be full of pain, but you can finally see the light at the end of the tunnel. The first of the new parts have taped out, so it is only a matter of time before details start leaking. Then we will know if the grand plan is working, at least on a technical level.S|A
uhn... not to make anyone angry... but why does that remind me of Dunnington... :eh:Quote:
Originally Posted by FlanK3r
hmm on second thought, its quite different, a extra scheduler for fp shared between two cores seems interesting, but the basic setup still reassambles the dunnington scheme quite strong (2 cores share 2nd levle cache and then 4+ cores share 3rd levle cache).
Dunno,why?In what regard? It doesn't remind me of dunnington at all :shrug:
The design approach like this has never been tried before(shared front end with hardware mutithreding based on sharing some parts of the core,namely integer execution units,while having SMT like FPU/SIMD which will be dual thread capable a la SMT and 256b wide;shared L1I cache among int clusters,globally shared L2 and L3;AVX support ;advanced turbo clock/boost features for individual parts within a "core" etc.).
Dunningtion is basically monolithic design based on 3 merged Penryn dice with huge L3 to alleviate the FSB bottleneck(which is still there...).Nothing novel uarchitecture wise.
The BD design approach has only been discussed in several academic papers thus far,and in Fred Weber's (AMD) presentation from 2005. No company has ever made a MPU based on this multithread design.It's a risky move but they seem pretty confident in the abilities of the new core.
Similar to dunnington?? Are you serious?? :down:Quote:
Originally Posted by Hornet331
Editied original post, again first impression was -> wth looks like dunnington (cache wise). I corrected that.Quote:
Originally Posted by informal
The core has an interesstening concept, but no 1st levle cache for FP seems quite risky, if the 2nd level cache isn't fast enough.
do you even read any post beyoned the first sentence?Quote:
Originally Posted by flippin_waffles
SSE will be serviced directly from shared L2 cache over double width L2 bus(when compared to today's 128b L2).The possible L1 bottleneck would be alleviated this way since FP/SSE stuff would be serviced over another bus from 2nd level shared cache ,leaving L1I and L1D for two 2-way int clusters exclusively .Quote:
Originally Posted by Hornet331
That is not a quote.:ROTF:Quote:
Originally Posted by terrace215
Didn't see these two posted yet:
http://img259.imageshack.us/img259/2002/bull1.jpg
http://img443.imageshack.us/img443/8014/bull2.jpg
Yes, but more bandwidth doesn't mean automatically that the cache has a lower latency. AMDs 1st level cache where always superrior in terms of latency to intels 1st level cache, but they lacked in the 2nd level department.Quote:
Originally Posted by informal
Face,thanks for posting the slides from pdf :). I didn't have the time to upload these,these are good addition to the discussion.Only you should have posted it in other (official) thread too ;).
I'd expect they did their jobs well and addressed all the potential bottlenecks as good as they possibly could. The FPU units will rely on the L2 cache heavily so I'd expect it will be low latency.Quote:
Originally Posted by Hornet331
How about a thread merge? :p:
I've added Face's post in the "official" thread: http://www.xtremesystems.org/forums/...d.php?t=238702Quote:
Originally Posted by Hornet331
please let's all go there! ;)
Depends who's posting. :p:Quote:
Originally Posted by Hornet331
AnandTech said that the FPU will use both L1 caches.Quote:
Originally Posted by informal
http://www.anandtech.com/cpuchipsets...oc.aspx?i=3674 (just below the second image)
I have one doubt about this core. Will it be able to greatly improve single threaded performance?
why would that be important in year 2011? He'll who cares about single thread performance now?Quote:
Originally Posted by Helmore
But that's legit question, so let's move it on the "official" thread: http://www.xtremesystems.org/forums/...d.php?t=238702
:up:
Actually it uses only the L1I cache,but yeah it is a shared resource too.Good catch.Quote:
Originally Posted by Helmore
As for the single-thread question, the module looks like it was designed to improve single-thread performance by utilizing 2x2way execution units,making it a 4 way capable design. Each of the 2 way cores would deliver 90% of today's Phenom 3-way execution strength and it's proven fact that going beyond 2 way in classical sense(simple decoding expansion) yields very small gains:i remember a figure of 10% improvement for 2way->3 way,can't recall the number for going 4 way but it ain't high at all.
So you'll have 2 2way integer cores trying to extract maximum performance from both serial and parallel code and dual threaded SIMD unit will try to extract highest ILP level from simd code.
Edit(on the topic of throughput performance): John Fruehe from AMD said that engineers told him that adding the second integer core to the one BD module costs only 5% of extra die area but gains 80% more throughput performance!Talk about the efficiency gain :). And we know that one "integer" core within a module is projected to be at 90% of Athlon IIs(mainstream MPU today) performance as stated in Bobcat presentation slides.
Bulldozer is very impressive. Cant wait for Bulldozer vs sandy bridge/ivy bridge benchmarks. Hopefully bulldozer smokes SB so that intel fast tracks its future releases. Currently they are in cruise control and releasing cpus at a relaxed pace.
Could be you are confusing Bulldozer with 32nm in general. What Dirk said was 'ramping 32nm in mid 2010' not ramping Bulldozer in 2010. Llano is 32nm and it would be reasonable to assume that it will intro before Bulldozer since Llano is Deneb-based.:DQuote:
Originally Posted by terrace215
I was actually trying to do that, but yesterday for some reason the forum was painfully slow and it didn't let me get into the other thread.. so I settled here : )Quote:
Originally Posted by informal