STOP THIS MADNESS!!! "We Intend To Support" is NOT the same as we support. You're all over the place with this thing, AMD's own documents disprove your point and you seem to be gullible to be pinning all your arguments on a discussion between an engineer and an architect (of some sort). Shintai is right; he was right all along just that some would rather go after him than prove their point - which you're finding hard to do. Jesus!Quote:
Originally Posted by informal
Shintai, SSE5 specs are still online and can be found here: http://developer.amd.com/CPU/SSE5/Pages/default.aspx
Zucker,stop posting if you have no clue about the topic at hand.I provided the links with proof about Bulldozer instruction set support. There might be changes on intel's part in the future(ie. they change AVX basic spec again),but at this very moment BD cores will support the previously(10 times repeated) version 5 of AVX and version 3 of FMA ,plus BD cores will have their own "exclusive" XOP extensions,a number of SSE5 instructions that are not included in AVX but could be important and valuable for HPC crowd.
That still doesnt change anything. And the other PDF is version 3.03 from May 2009. The same type of instructions I listed are still missing. Both 256 and 128bit.Quote:
Originally Posted by informal
And your new PDF is from....August 2007. SSE5 is also a SSE4.x competitor. Not AVX.
I´m sure you can recall this:
http://images.anandtech.com/reviews/...5/SSEGraph.png
Of course do they "just" intend to support it because they Bulldozer is an upcoming product and Intel could abuse their market position again by changing the spec in the last moment. Why this ridicules hair splitting?!Quote:
Originally Posted by Zucker2k
Shintai stated several times that Bulldozer is not going to be AVX compatible, and even worse, that it has an inferiour instruction set, which is a totally baseless claim at best!
It's not new pdf,ffs man.. It's an old spec. of SSE5 since you said and I quote :"Hence there is NO former SSE5 instructions." There are and i gave you a link. XOP extensions,the one AMD links to are an added(made by AMD ) instructions, that are a sort of "leftover" from SSE5.These weren't duplicated in AVX and since AMD already got a positive review from developers they decided to use VEX decoding scheme on them and include them too(like a new 3dnow if you will). When Mr. Christie(a BD core design team member) stated they will support version 5 of AVX,it means they will support version 5-no mroe no less. You can find version 5 online and guess what-in order to be compatible ,the instruction format must be the same.
You are simply an ignorant troll my friend!Quote:
Originally Posted by Shintai
AMD just made an industry announcement on planning to support AVX on the Bulldozer platform. All what depends on it's realization is if Intel is going to abuse their market position again by changing the spec before AMD can make the changes in time!
So what is your fricking problem here!?!
You do know that SSE5 is dead by itself and moved into AMDs new spec in the Volume 6 PDF? Right?Quote:
Originally Posted by informal
Or do I even have to repost your own quotes:
And that the instructions in Volume 6 is FAR from the same as Intels AVX spec? Right?Quote:
Now, originally we had focused on what we had called SSE5, a specification we proposed for review by the industry in 2007. However, due to the overlap of functionality between the AVX instructions and SSE5, AMD has decided to recast the SSE5 instructions into the AVX framework. AMD made decision to ensure the continued compatibility of x86 software, and plans to incorporate AVX instructions into AMD processors in 2011
Or is AMD now wrong or is it some later revision of Volume 6 or some new Volume 7 that will back up your claims? You have everything pointing against you with your superset.
AMD seems to choose to support a selection of the AVX instructions. those they have most faith in. However there is no promoted SSE instructions in form of VEX.128 and VEX.256 that is also part of the AVX spec just to mention the most obvious.
Volume 6 IS an SSE5 in AVX form(using VEX decoding) .It IS AMD's special set of instructions,an addition. ADDITION.Quote:
Originally Posted by Shintai
AVX support means a support for complete AVX set of instructions,like Mr Christie already confirmed .
And "these" or "all of it" are these(taken from question Mr Fog directed to Mr. Christie in devblog i already linked to):Quote:
Originally Posted by BD core designer,D. Christie
* XOP
* FMA4
* CVT16
* SSSE3
* SSE4.1
* SSE4.2
* AVX non-destructive instructions
* AVX 256-bit registers
You need to read AMDs Volume 6 and Intels AVX spec PDFs....Quote:
Originally Posted by informal
Christie didnt confirm it. Intend != Confirm.
And AMDs perception of AVX seems to be a subset of what Intel calls AVX: And even that they dont have full support for...yet.
There is absolutely no VEX.x going on for AMD. And why did you link the SSE5 PDF if you knew it was absolete and recasted into AVX? Or did you first find out later....
Now be a good boy and read the 2 PDFs instead of this continual jibberish.
Ahh this is pointless. You are just trolling again without a shred of credibility,trying to contradict the man who is designing the very bulldozer core.I wasted so much space here proving you wrong and still you are going strong in your delusional world. Good luck man,you'll need it .
I see that you have put in a monumental effort for another person who is simply not worthy of the effort.Quote:
Originally Posted by informal
Actually its you who contradict him. You changes his wording to fit your wishes.Quote:
Originally Posted by informal
AMD right now, as you can see in their PDF, only have partial AVX support. However since its still work in progress for AMD also with Bulldozer design. Then its just not done yet.
They intend to have full AVX support in 2011. That means they plan on it, hope on it so to say if nothing goes wrong. It does however not mean its confirmed or that they already have.
You simply played a super fanboy and ran away with the ball. Changing the original statements into something better.Quote:
1. To have in mind; plan: We intend to go. They intend going. You intended that she go.
2.
a. To design for a specific purpose.
b. To have in mind for a particular use.
3. To signify or mean.
shintai has a point and is just being savaged by two members, You guys need to chill and learn how to discuss like adults.
I only see one member mention the word troll. who is the other ?Quote:
Originally Posted by gallag
Actually its you who contradict him. You changes his wording to fit your wishes.Quote:
Originally Posted by informal
AMD right now, as you can see in their PDF, only have partial AVX support. However since its still work in progress for AMD also with Bulldozer design. Then its just not done yet.
They intend to have full AVX support in 2011. That means they plan on it, hope on it so to say if nothing goes wrong. It does however not mean its confirmed or that they already have.
You simply played a super fanboy and ran away with the ball. Changing the original statements into something better.Quote:
1. To have in mind; plan: We intend to go. They intend going. You intended that she go.
2.
a. To design for a specific purpose.
b. To have in mind for a particular use.
3. To signify or mean.
Confirmed? Lets see again what he said:Quote:
Originally Posted by informal
Intend or confirm....hmmm :rolleyes:Quote:
Originally Posted by Mr. Christie
I should have mentioned something about these. We intend to support all of it, with the possible exception of CVT16, which might not appear in the initial AVX-compatible products (hence the separate feature flag)
Well Doh,it's a future product :rolleyes: . It's due out in ~2years from now,in 2011. A lot can happen,intel can change the spec again. But,as BD core designer said,the BD cores will have AVX support PLUS XOP support. It's very simple.You failing to grasp that AVX in its current state is supported,even after a man behind the very core states so,is ridiculous at best and rude at worst.
Gentlemen..
Let's play nice ok.
Let dave read the forum without seeing potential bloodbaths..
It's tough with your first coffee of the morning.:D
Thank you.
What? I don't even know how to respond to this, What did I say about the word troll?Quote:
Originally Posted by Final8ty
You said being attacked by 2 members?Quote:
Originally Posted by gallag
I assumed calling someone a troll is an attack(justified or not). i would like to see your definition & quote what you would consider an attack on shintal from this thread.
But its not supported yet. Thats something the latest PDF from AMD from this month confirms. That AMD might intend something else is a different story. but as today the answer is no.Quote:
Originally Posted by informal
... because what AMD announces to it's industry partners is a lie because Shintai says so.Quote:
Originally Posted by Shintai
Yeah Shintai, they will publish the whole spec of their cores ,disregarding the competitive reasons and blurb out specification just for your viewing pleasure :rolleyes:.
For you,even if Dirk Meyer came and showed you the designs in details,in person,it wouldn't be enough...
The fact is the core is a good 2 years away.AMD just announced major plans about major extension set incorporated in their future core. You wanting to see a blueprint won't change a thing since a) you can't have it and b)it will still be there...
So what you say is that Intel exposed their Sandy Bridge and Ivy Bridge cores? Got more excuses? This is an instruction list of supported instructions not a diagram...Quote:
Originally Posted by informal
You jumped the gun and got caught with your hand in the cookie jar. Bravo!
Lol no kidding :rolleyes: . They do not have to post anything about their new core. They just said it will be there(the support) .The pdf sheets you demand will be there by the time BD cores launch.Now ,at this moment AMD has no reason to publish anything,especially in the position they are right now(post nehalem period). We still don't know what implementation 256-bit vector register will have(ie. true 256b registers or 2x128bit implementation).
@informal Most likely the implementation will be in the forum of 2x 128 bit's thats what intel is gunning for anyways.
@Shintai AMD and Intel have outlined these SDK's so that developers get started on the basic framework it does not take 24Hr's to write up an application core or a FP Engine that supports AVX or SSE5. If you say that Intel and AMD give developers more info than what is released to the public that would be wrong at least at this stage. AVX used to include lots of things that were striped out in ver. 2 and may get re-attached in ver. 3 but the basic working model will remain the same.