Q6600 G0 & Ballistix Tracers OCCT Mix 2 Hrs Stable Configuration
Q6600 G0 & Ballistix Tracers OCCT Mix 2 Hrs Stable Configuration:
My OC exp tells me that RF0219 BIOS does help my Q6600 at *8 multi acheived FSB475 using 333 Strap but it wasn't fully stable enough to pass OCCT/PRIME stress tests long enough (Everest Tests or similar permittable).
Q6600 at *8 multi and high FSB460+ can means a lot more stress on the NB than equivalent clock using *9 multi. *9 multi could bring the CPU clock all the way up to 3870mhz Prime SmallFFT stable on air but at the cost of lower system bandwidth. *8 multi brings out better overall system performance but at the cost of stability due much higher NB clock speed (Using NBCC calculation: FSB * Stock Multi/Set Multi = FSB465 * 9/8 = 2093mhz vs 1860mhz). RF0219 is still a little more stable than MF bioses at high FSB configuation becouse of fewer occassions of "DET RAM" hang. Overall OC experience is a bit more smoother than the MF bioses I've tried.
Stability is my main concern and I can finally pass OCCT Mix 2 Hrs stress test using RF0219 Bios at 465FSB*8 Multi, 333 Strap. Technically speaking, RF0219 bios doesn't give me an advancement in OC but it does help my system stabilized at FSB465. No DET RAM hang and no odd problems.
The additional finer tuning options in the RF bios gives me a slightly more system bandwidth at no additional cost to system stability when you tuned the settings right. You need to have an idea of the FSB set to the corresponding FSB strap used to know how much further bandwidth can you gain from adjusting the performance level settings in Transaction Booster.
Here is the full configurations for your reference:
Extreme Tweaker
Ai Overclock Tuner : Manual
OC From CPU Level Up : AUTO
CPU Ratio Control : Manual
- Ratio CMOS Setting : 8
FSB Frequency : 465
FSB Strap to North Bridge : 333
PCI-E Frequency: 110
DRAM Frequency: DDR2-1116
DRAM Command Rate : 2T
DRAM CLK Skew on Channel A : Normal
DRAM CLK Skew on Channel B : Normal
DRAM Timing Control: Manual
CAS# Latency : 5
RAS# to CAS# Delay : 4
RAS# Precharge : 4
RAS# ActivateTime : 8
RAS# to RAS# Delay : 3
Row Refresh Cycle Time : 35
Write Recovery Time : 6
Read to Precharge Time : 3
Read to Write Delay (S/D) : 8
Write to Read Delay (S) : 3
Write to Read Delay (D) : 5
Read to Read Delay (S) : 4
Read to Read Delay (D) : 6
Write to Write Delay (S) : 4
Write to Write Delay (D) : 6
Write to PRE Delay : 14
Read to PRE Delay : 5
PRE to PRE Delay : 1
ALL PRE to ACT Delay : 5
ALL PRE to REF Delay : 5
DRAM Static Read Control: Disabled (Enable will gives you slightly more bandwidth at the cost of stability)
Ai Clock Twister : Stronger
Transaction Booster : Manual
C/P: A1 A2 A3 A4 A5 | B1 B2 B3 B4 B5
LVL: 07 07 07 07 07 | 07 07 07 07 07
Common Performance Level [8]
Pull-In of CHA PH1 Enabled
Pull-In of CHA PH2 Enabled
Pull-In of CHA PH3 Enabled
Pull-In of CHA PH4 Enabled
Pull-In of CHA PH5 Enabled
Pull-In of CHB PH1 Enabled
Pull-In of CHB PH2 Enabled
Pull-In of CHB PH3 Enabled
Pull-In of CHB PH4 Enabled
Pull-In of CHB PH5 Enabled
CPU Voltage : 1.48750 (1.464-1.472)
CPU PLL Voltage : AUTO (1.664-1.680)
North Bridge Voltage : 1.65 (1.680)
DRAM Voltage : 2.12 (2.208)
FSB Termination Voltage : 1.40 (1.456)
South Bridge Voltage : 1.075 (1.104)
Loadline Calibration : Enabled
CPU GTL Reference : 0.63X
North Bridge GTL Reference : 0.67X
DDR2 Channel A REF Voltage : AUTO
DDR2 Channel B REF Voltage : AUTO
DDR2 Controller REF Voltage : DDR2-REF (1.104)
SB 1.5V Voltage : 1.5
CPU Spread Spectrum : Disabled
PCIE Spread Spectrum : Disabled
http://i41.photobucket.com/albums/e2...ableRF0219.jpg
http://i41.photobucket.com/albums/e2...-4-8Stable.jpg