It's a joke.Quote:
Originally Posted by BeardyMan
So many of the guys in the WCG team have bought quads as they are the best bang for the buck and I don't have one so I thought I'd tease..:D
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It's a joke.Quote:
Originally Posted by BeardyMan
So many of the guys in the WCG team have bought quads as they are the best bang for the buck and I don't have one so I thought I'd tease..:D
Quote:
Originally Posted by jabway
It may well be a Barcelona related thread but if the topic of conversation naturally branches into different tangents then why get upset about it? I actually really want to know how this is so upsetting? The topic is still cpus's, do we have to walk on egg shells around here to avoid upsetting a few people that don't like a company (as sad as this is:ROTF: ) even if it is relevant to the topic in hand?
Regards gallag
Exactly.Quote:
Originally Posted by mstp2009
Interesting fact: AMD has a special mobile process for their mobile chips (thicker gate oxides, etc), designed to reduce idle leakage. This was how the 90nm Turion 64 parts could defeat the 90nm Dothan parts for real-world workloads. This was true for the 90nm Turion 64 series; I don't know about the 65nm parts though.
Not wanting to upset AMD Fans, you should leave Intel out of your comments. Why do you have to bring up Intel? Oh wait that was meant to be negative towards Intel LOL! :rofl:Quote:
Originally Posted by Shadowmage
Anyway, Dothan lost some benchmarks to Turion because Dothan ran on old generation Platforms that used slower FSB, slower and much less memory Bandwidth, slower I/O, crappier Video and etc... It had little to almost nothing to do with the Processor. Desktop Yonah (still on a crappy Platform) vs, X2 proved that. See Anand's first Yonah Review?
It is kind silly of when;
Bring up Intel in a positive Manner in an AMD thread and it's Thread Crapping.
Trash out Intel or just write negative stuff even if it's false and all is OK.
I say this to you and MovieMan with a lot of respect, if folks are warned for bringing up Intel in a good way, folks should be warned for bringing up Intel in a negative way or using false info. These kinds of lines "This was how the 90nm Turion 64 parts could defeat the 90nm Dothan parts for real-world workloads." invites a reply. Then we get folks whining about "We're not talking about Intel". See the problem? You guys can't have it both ways. If you hate Intel that frackin' bad, go to the AMDZone or etc..? Please?
I'm hoping these chips perform at least mildly well so competition can keep going.
lolQuote:
Originally Posted by Donnie27
Both Turion 64 and Dothan are outdated; their time has past. EG people talk :banana::banana::banana::banana: about Prescott now and it's no problem. Did I say AMD rawks and Intel sucks? No, Intel clearly has a better processor on all fronts (power and performance and cost, but only for non-superbudget computers) at the moment. Stop being so sensitive.
The problem with you is that you don't know much about the subject matter and make incorrect conclusions from data. That's the main reason why you always get flak from your replies (good example is your previous comment about prefetching).
Very uncommon to see such an insightful post in normal day to day banter. The center of the Fmax distribution pretty much determines health and quantity of the yield of any particular process, examples...Quote:
Originally Posted by savantu
F04 10 stage delay is normally distributed: http://date.eda-online.co.uk/proceed...iles/07g_1.pdf Figure 2, and this only accounts for variation within die and from stage to state in a 12 stage design.
Or the statitical cummulation of all process variation results in a normally distributed Fmax:
http://eda.ee.ucla.edu/EE201A-04Spring/GIT-PV.pdf see Figure 1.
This is why this rumor is so critrical, if true them AMD has moved the Fmax peak distribution from the 1.8-1.9ish range a bit higher. It is hard to tell since there is not 'indication' of sigma, so 3 sigma from center is hard to understand what kind of volume.
However, statistically speaking, even at 3 sigma only 0.3% of the population will be at or greater than 3 sigma away.... this is good enough for some 'black box' limited editions, but hardly enough to satisfy a volume launch....
It is a big question mark (?) and we will only know when the processors actually start showing up in volume.
Quote:
Originally Posted by Shadowmage
So does Intel:
http://www.theregister.co.uk/2005/09...-leakage_65nm/
Though Intel uses this for the ULW parts and not the normal mobile parts.
ehh barcelona will launch at 2.6Ghz...
I'm quoting this in 3 months...
So AMDs press release was false?Quote:
Originally Posted by xlink
You still don't get it do ya'? You love to try and put down folks, especially those you don't agree with so that's nothing new, typical Fanboy schlock. It's not about what Rawks or not. I'm tagged as one of the biggest Intel Fanboys here, now show where I said AMD sucks?Quote:
Originally Posted by Shadowmage
I made a simple request, well, simple for some folks. If you want an exclusive AMD thread or conversation, leave Intel out of it and then there are fewer conflicts. If you can't stand being told something as obvious as C2D is Faster, then you have a personal problem.
No, if anyone is clueless here, it's you;) To solve this one, go to the Intel section and start a thread called "Intel's Smart L2 and Smart Memory Access is simply Pre-fetching" as you implied . I'll show you LOL! When all is said and done, the results are the only thing that matters. Again, shouldn't be in a thread about Barcelona launch speeds.:rofl:
In before thread going south.
Oh wait, it already has..
Lol. Every Barcelona/AMD thread has the big 3 Intel drones making their necessary appearance. It's like the 3 stooges, but instead of being funny they're actually incredibly annoying.Quote:
Originally Posted by Frank M
Then again, I've come to expect this here. *shrug*
3 Stooges or etc..... One more time and in bold--->Again, shouldn't be in a thread about Barcelona launch speeds.Quote:
Originally Posted by Mav451
no. and I have no hard information on it either.Quote:
Originally Posted by Shintai
pure speculation and the like.
that's basically my gut feeling. I'm willing to bet that the launch will be at around 2.6Ghz give or take. If I'm wrong, feel free to bring this up again in the future and to call me a fool, I won't hold it against you.
Penryn's new high-k transister design is supposed to provide for 20% more efficiency, translating to better clock per wattage and also providing better performance in general. I dunno, but at 2.2ghz.. maybe AMD will release 3.0ghz? I think it's a little farfetched since if you really think about it, 3.0ghz is incredibly high binned for AMD already.. and to expect 4 cores to come out perfect like that is going to be hard. That exclusivity of that would push prices up pretty high for those 3.0ghz Phenoms. Intel's projecting 3.8Ghz wolfdales and I don't doubt them when they say that...Quote:
Originally Posted by RPGWiZaRD
I don't know anything about Smart L2 and SMA, but you know... Intel's L2 and L3 cache latencies are very little. L2 has a latency of around 12 and their L3 has a latency of 14....... AMD's L2 has a latency of 18... and their L3 has a latency of around 30-40 something from what I've heard. I admit, I'm an intel fanboy, but even I would like to see atleast competing barcelona scores for benchmarks. I'm actually hoping all of these benchmarks, the superpi especially, is fake. 39 second 1mb is bad... my PD could beat that, but in all reality, AMD's chip doesn't sound very impressive, and the cache sizes and latencies would probably explain the super pi score. AMD's chips may have more L1, but they really can't compete against 8mb-12mb of 12 lat L2 cache....Quote:
Originally Posted by Donnie27
wow....can't say i miss this portion of Xtremesys but....what the hell...
i'm of the opinion that top launch speeds for september will be 2.2ghz as an SE part (120w TMax)
Bottom-end, if i can hazard a guess will be either 1.8 or 1.9ghz (remember, AMD is running 100mhz model changes vs. the 200mhz changes of the F3 series opterons).
availability will be there; embargos end on 9/10 so, expect the typical crappy reviews from everyone at 1130pm the night before. can't you tell that i've done this before?
cheers,
dave
Not really. My K7 Barton-Sempron with 256kB of L2 with latency of 20 in a badQuote:
Originally Posted by StealthyFish
board which can't even set memory right (no 1T) or oc decently, my best time
was 53s. With higher fsb and 1T, it would probably be high 40s.
Current Intel Processors doesn't use an L3. SO if you meant L1 and L2, sure. It's kind of hard to talk to these guys when they put their love for AMD in front of common sense. I've seen AMD Fans call other AMD Fans Intel fans because they didn't repeat AMD's spin.Quote:
Originally Posted by StealthyFish
Now since Intel's and AMD architectures are different, Cache dependence, the Amount of Cache and even the way the cache is setup (Inclusive-Exclusive) is different for each company as well. I believe each is using what's best for them. Small fast is good for Intel just as a larger L1 is better for AMD. Intel tried L3 and got mixed results on the desktop. Another example, read up on L1/L2 cache ECC or error correction and tell me if you still think AMD's way is the best way to do it?
K10 will not only need a smarter Pre-Fetch as the other guys mistakenly still don't get. Even after linking these same 3 Hardcore AMD fans to what Smart Cache and Smart Memory access was, they still didn't get it. It will matter for K10 as well if AMD doesn't improve on its Dumb Memory Access, K10 will not Gain that much. Meanwhile how blocks of memory is stored, how that stored memory is accessed and even the speed of access will only get better for Intel.
Maybe you should read up on K10's architecture before telling people to read about ECC, cache ad smart memory.Quote:
Originally Posted by Donnie27
I posted on here six months ago tha AMD use Intel like smart memory access and the Geeks much smarter than me said it wasn'tadvanced. Now since I, like 99.998% of everyone else, I don't have one, we'll just have to waite and see. That's what the "if" is for.:DQuote:
Originally Posted by LordEC911
"It will matter for K10 as well if AMD doesn't improve on its Dumb Memory Access"
Well, I'm just comparing L2 and L3 together. L1 is considerably less latency than L2 or L3, for Intel and AMD. No way should L1 even be near a latency of 10, otherwise, it'd be pointless. Intel currently doesn't use L3 for their consumer products, but they have perfected their L3 to almost L2 standards (if you've seen intel's itanium server products like the montecito, you can't deny that intel hasn't been working on L3), and that is a very large benefit for intel processors as they can load more cache to the processor and distance itself away from the core farther while suffering very little performance loss due to greater latencies. I've noticed AMD has been saying a lot about their L3 cache, but with the latencies that I've seen, it doesn't look to assist in gaining processor performance. These technologies you mention may assist in that, but like I've said, I don't know much about them, so it'd be fruitless (and quite retarded), for me to argue with you on that point (or anyone else for that matter). That does make sense though. I was stating that despite the architecture differences, processors would benefit from lower latency cache. Kind of like processor frequencies. doesn't matter what the architecture is, the higher clocked the processor, the better performance it will output (though the amount it will increase will be discriminatory).Quote:
Originally Posted by Donnie27
But I think before we continue this discussion, more research would have to be made. If we're going to base most of our information on assumptions, we might as well be a bunch of [h]ardforum noobies having a dumb flamewar.
Please keep your flamebaiting to yourself :rolleyes:Quote:
Originally Posted by Donnie27
We don't need threads going south.
Intel's cache tech is much better than anyone's. Cache may be the whole reason for AMD's speed problems and even the cold bug. :shrug:
Yep, throwing huge amount of cache, i.e. transistors, to help with their poor branching/logic is certainly an awesome design.Quote:
Originally Posted by lapdog
SOI & large cache are two different things, though there might be a loose correlation. (CPU/architecture is not my best strength)