Intel plans to deliberately limit Sandy Bridge overclocking

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Originally Posted by Solus Corvus

Yeah, let's all start talking about AMD. :rolleyes:

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Yeah,I don't know why GloFo and Llano launch were dragged into this by terrace.

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Originally Posted by informal

No it's not... take a look yourself:

If you consider the 1.2mm2 "a considerable amount",then you are correct sir.:p:
The SSE part of the core has changed negligibly .Where is the widened(256bit) SSE logic?How did it fit inside the same die area?

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you must have really good eyes if you can see the SSE and AVX units.

it's easier to claim double pumping like you have but do you realize that the logic required to reach those clock speeds would be 50% more and use 3-10x more power? also did you know that RTL code cant even reach those clocks so you have to custom design millions of transistors?

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Originally Posted by Solus Corvus

Yeah, let's all start talking about AMD. :rolleyes:

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Amazing! event in a thread with the title like "Intel plans to deliberately limit Sandy Bridge overclocking" ... The tittle is totally BS, but still ... :clap: :clap: :clap:

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Originally Posted by Hornet331

Hmm theres something wrong with that picture, cause it lsts SB with 2mb, yet its either 1.5mb or 2.5mb l3 per core.

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Maybe explanation by Hans here:

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Originally Posted by Hans De Vries

The total L3 cache is really 8MB but 1/2 MB of each core is reserved for the GPU:

You can see the 5 identical interfaces to the L3 cache ring. The leftmost is the GPU
interface. At the right there is a 6th somewhat different ring interface to the IMU

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Quote:

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Originally Posted by Chumbucket843

you must have really good eyes if you can see the SSE and AVX units.

it's easier to claim double pumping like you have but do you realize that the logic required to reach those clock speeds would be 50% more and use 3-10x more power? also did you know that RTL code cant even reach those clocks so you have to custom design millions of transistors?

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I just countered your "greatly increased die area" comment with an actual hard data.I didn't say I believe it's double pumped,it's just a possibility.AVX/SSE part is the top left rectangular part of the core.

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Originally Posted by informal

Where did you hear the 1.5/2.5MBs figures?

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SB quad-core has 6mb of L3, the hexa & octo-core versions have 15mb and 20mb of L3

do your math

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Originally Posted by thebanik

I guess the similar rumors where floating when Nehalem was about to be released, so lets see something more concrete before worrying.......

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yupp. :up:

Sweeper,the 6MBs are actually the usable part of the 8MBs,like Hans explained in the link i posted above... Read up.That's why Hornet asked about the 1.5Mbs of cache dedicated to each core.

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Originally Posted by qcmadness

Launch =/= shipment

NVIDIA launched GTX480 / GTX470 in March, and shipped in April.

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As AMD & Intel use the terms these days "launch" is AFTER "production shipments" NOT before.

For example, both SB and Ontario will have shipments in Q4 and launch in Q1.

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Originally Posted by informal

Where did you hear the 1.5/2.5MBs figures?

Maybe explanation by Hans here:



I just countered your "greatly increased die area" comment.I didn't say I believe it's double pumped,it's just a possibility.AVX/SSE part is the top left rectangular part of the core.

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1,5mb figure come form the ES that where posted here.

dualcore with 3mb
http://www.xtremesystems.org/forums/...d.php?t=250145

quadcore with 6mb
http://forum.coolaler.com/showthread.php?t=240578

2,5mb numbers are still rumors, but since the 1,5mb where spot on I guess there is also somewhat true for SB-E.


Btw. drwho if it might be possible can you gives us a hint if there will be 2 or 3 plattforms? Theres is quite a confusion if S2011 really reaches down to the consumer space or if there is a S1356.

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Originally Posted by terrace215

As AMD & Intel use the terms these days "launch" is AFTER "production shipments" NOT before.

For example, both SB and Ontario will have shipments in Q4 and launch in Q1.

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Let's see if you can get SandyBridge or Ontario in Q1.

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Originally Posted by Hornet331

1,5mb figure come form the ES that where posted here.

dualcore with 3mb
http://www.xtremesystems.org/forums/...d.php?t=250145

quadcore with 6mb
http://forum.coolaler.com/showthread.php?t=240578

2,5mb numbers are still rumors, but since the 1,5mb where spot on I guess there is also somewhat true for SB-E.

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Half a megabyte per each core's cache block is reserved for a GPU,so QC SB has 6(8)MB and SB-E has 15MB of usable cache(or following the previous math,actually 3x6=18MB of total cache).

20MB L3 cache seems not possible at 32nm and 1356 LGA....
One question tu Bulldozer, i dont know, if 8 cores are 8 bull. modules or only 4 modules???

To SB: exist samples SB for highend oor to time are only 1155 ES?

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Originally Posted by informal

Half a megabyte per each core's cache block is reserved for a GPU,so QC SB has 6(8)MB and SB-E has 15MB of usable cache(or following the previous math,actually 3x6=18MB of total cache).

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SB-E has no gpu... :p:

edit: ok that part with the gpu makes sense, so we have 2mb cache for the gpu alone, not bad.

Also as Hornet already asked DrWho,I would like to know more about the s2011 and its possible sliding down to consumer space and how will it co-exist with s1356.

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Originally Posted by Hornet331

SB-E has no gpu... :p:

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Oops forgot about that :). Why the 2.5MB figure then? For the iGPU models it makes sense ,but for the E part?

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Originally Posted by informal

Sweeper,the 6MBs are actually the usable part of the 8MBs,like Hans explained in the link i posted above... Read up.That's why Hornet asked about the 1.5Mbs of cache dedicated to each core.

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Yes, This is why you can have a Sandy Bridge with disabled GPU and 8MB L3 cache (2MB per core).

http://www.xtremesystems.org/forums/...10&postcount=1


Regards, Hans

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Originally Posted by FlanK3r

20MB L3 cache seems not possible at 32nm and 1356 LGA....
One question tu Bulldozer, i dont know, if 8 cores are 8 bull. modules or only 4 modules???

To SB: exist samples SB for highend oor to time are only 1155 ES?

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4 modules

Now should be low-end (2-4 core)

I just want to know if there will be unlimited overclocking on non-unlocked parts.

This is really quite a strange move by Intel.... Unless the gulf between Sandy Bridge and Bulldozer is insanely huge this kind of BS will move me straight towards AMD. Hopefully this is just overblown FUD as it was with Nehalem.

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Originally Posted by Hans de Vries

Yes, This is why you can have a Sandy Bridge with disabled GPU and 8MB L3 cache (2MB per core).

http://www.xtremesystems.org/forums/...10&postcount=1


Regards, Hans

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This is incorrect assemptions. Can't say more, but this is pure speculation in the wrong direction, Sorry for the bad news. (The size of the cache and the GPU cache needs are not related, good imagination by the way ;-) )
(The other questions answers are under NDA ... sorry)
The good new is that the title of this thread is totally silly and wrong too :)

This thread was just a Big piece of :spam:
Francois

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Originally Posted by Drwho?

(The other questions answers are under NDA ... sorry)

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I feard so, but thx anyway. :up:

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Originally Posted by Drwho?

Amazing! event in a thread with the title like "Intel plans to deliberately limit Sandy Bridge overclocking" ... The tittle is totally BS, but still ... :clap: :clap: :clap:

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so coming from an intel guy, the SB will OC. and are all of them really having an IGP, dose intel need graphics share numbers that bad

Drwho?: some evidence about this?

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Originally Posted by FlanK3r

Drwho?: some evidence about this?

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Well, The AMD bullDozer architect wishes that I answer you (Poker Face), this time, it is like conroe, to figure out the real performance of SB, you will have to wait very close to launch, most of what is out there is not having the right tuning, and I really like it this way. :yepp: :rofl:

After all, competition is like a Poker game ... playing with all the card on the table never worked ...
:shrug:

You can decide to believe AMD about SandyB ... but you would not use the most realable experts about 32nm ... outch .. sorry, could not resist :ROTF:

Just friendly jokes, ok ... ?

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Originally Posted by Drwho?

Well, The AMD bullDozer architect wishes that I answer you (Poker Face), this time, it is like conroe, to figure out the real performance of SB, you will have to wait very close to launch, most of what is out there is not having the right tuning, and I really like it this way. :yepp: :rofl:

After all, competition is like a Poker game ... playing with all the card on the table never worked ...
:shrug:

You can decide to believe AMD about SandyB ... but you would not use the most realable experts about 32nm ... outch .. sorry, could not resist :ROTF:

Just friendly jokes, ok ... ?

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Francois:
This isn't just to you but to all companies.
ALL of you want to hide the numbers till the day the parts release.
I think your all wrong in your thinking.
IF it's a great part then shout it to the world.
Show it,tout it,say to the world: "Beat this you suns a biatches"
Oh, did I say I'm a sort of in your face type of guy?:rofl:

cheers to that MM lol. Honestly the NDA thing is played out, and with the cloud hanging over the oc community right now, some good bloody news would be awesome :)

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Originally Posted by Movieman

Francois:
This isn't just to you but to all companies.
ALL of you want to hide the numbers till the day the parts release.
I think your all wrong in your thinking.
IF it's a great part then shout it to the world.
Show it,tout it,say to the world: "Beat this you suns a biatches"
Oh, did I say I'm a sort of in your face type of guy?:rofl:

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Intel is a very open company, when we include new improvements, we always take time to explain to external experts like the excellent David Kanter how we archived those speed and cool tricks. If we do that too early, it actually allow our competitors to catch up faster, decreasing the return on investment of our Research and Dev ... This can actually cause you to sell your fabs if you keep doing it ... :)
Fortunatly, the business guys at Intel know all of this, In French , we say "You don t teach a old Monkey for to make grins ..."
It is important to do not get your competitor guessing your next moves, while it is important to intel to be predictable for its partners and people working with our hardware and developping for the PC ...
I am not involve into those decisions, but I understand the smartness behind it, and I get trained every year to respect the law, and do it the right way.

I just hope that explaining this to you guys does not bore you, I hope it is interesting to you to understand what we do. (Not because we don t like you, we just protect our R&D investments , being copied too early cost $)

DrWho?
(My personal view on the thing)

Plus.... if we know how awesome the next stuff is gonna be and its not too far away... we might just not bother buying that 980x tomorrow... just wait and save our cash.

ALTHOUGH..... the newer stuff will always be better :)

DrWho, just a simple question: If a random Chinese guy in Taiwan can get a sample of SB and run various tests and post the results online,what do you think are the chances the competitors performance labs haven't done the same thing,even earlier ? Even if the SB samples are, as you say "untuned" ,the guys over at your competitors labs are smart enough to project the correct performance data fairly accurately. Same goes for the "other way around case"(your guys getting competitor's samples).
All in all,NDAs are there for a reason,but this late into the development process of both SB and Bulldozer, no 3rd party leak can change much(like the Chinese guy's results can't change what AMD can do with their next gen parts).
We are grateful though for your postings,even though you can't say much due the NDA constraints.

Perhaps Intel is so confident in their product's performance they feel that their SB at stock voltage will outperform AMD products even when overclocked?

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Originally Posted by josh1980

Perhaps Intel is so confident in their product's performance they feel that their SB at stock voltage will outperform AMD products even when overclocked?

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Core i7 does already on many benchmarks ...

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Originally Posted by informal

I just countered your "greatly increased die area" comment with an actual hard data.I didn't say I believe it's double pumped,it's just a possibility.AVX/SSE part is the top left rectangular part of the core.

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i said considerable (!great) and 10-15% is so. my measurements match up fairy well with hans' for all but SB. with smaller and smaller cores it becomes harder to measure accurately. i suggest you try and see what you get.

It's actually 7% increase in core size(excl. L2), if you want to nitpick :). And general consensus is that this is not nearly enough for monolithic 256bit hardware.But intel has the smartest guys in the design teams,so there must be something new and innovative they did with SB's SSE units.

Im sure someone will figure out a way to do a physical mod on the chips now to unlock some level of OC

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Originally Posted by informal

DrWho, just a simple question: If a random Chinese guy in Taiwan can get a sample of SB and run various tests and post the results online,what do you think are the chances the competitors performance labs haven't done the same thing,even earlier ? Even if the SB samples are, as you say "untuned" ,the guys over at your competitors labs are smart enough to project the correct performance data fairly accurately. Same goes for the "other way around case"(your guys getting competitor's samples).
All in all,NDAs are there for a reason,but this late into the development process of both SB and Bulldozer, no 3rd party leak can change much(like the Chinese guy's results can't change what AMD can do with their next gen parts).
We are grateful though for your postings,even though you can't say much due the NDA constraints.

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One important parameter of the integration happening, with the GPU getting into the CPUs (as Core i3/i5 already) is that the buses and all the programmability included in those new generation processors can impact dramatically the performance and power usage. The Taiwan or Chinese guy running the SB does not have the receipe, and those part can behave very far from what the final product will do, a wrong code in the power control unit can change your performance by massive factors, latencies can change, bandwitch can be limited by not well programmed power saving features.
Policies between sub systems can be conflicting ... This is a very hard work to do it right, and the tool required to figure out those thing are not available yet outside ...
So, don't trust what you see online, it can be optimistic or pesimistic, time will tell you, but not me .... :up:

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Originally Posted by Drwho?

This is incorrect assemptions. Can't say more, but this is pure speculation in the wrong direction, Sorry for the bad news. (The size of the cache and the GPU cache needs are not related, good imagination by the way ;-) )
(The other questions answers are under NDA ... sorry)
The good new is that the title of this thread is totally silly and wrong too :)

This thread was just a Big piece of :spam:
Francois

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Hi, François,

I have no problem in believing you that the title of this thread,
(which is the title of the article it refers to) is crap and fud.

For the other part, the architectural features of Sandy Bridge,
there is an ancient saying in Dutch which goes as follows:

"An old grinning Monkey does not need to have signed an NDA
to see some things from a mile away...." :)

So for those who ask me I'll say:

1) The L3 cache located next to each core is 2MB.
2) The AVX unit of Sandy Bridge is two fold hiper-pipelined.

(It handles 256 bit SIMD words with 128 bit hardware by
inserting the second 128 bit data into the pipeline after
half a cycle after the intermediate results of the first half
are stored in the halfway registers)


Regards, http://www.goldy.vwat.net/images/Grinning_Monkey.gif


But I respect that your position on this is like: http://www.aspencountry.com/assets/p...4999/34513.gif

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Originally Posted by Hans de Vries

But I respect that your position on this is like: http://www.aspencountry.com/assets/p...4999/34513.gif

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more like
http://1.bp.blogspot.com/_rDVdeht_mI...nny_monkey.jpg

oh please... come one you guys are both in +35years old and you still act like kids? :confused:

LOL this thread is funny.

And Dr. Who, lets assume you can overclock SB.

It will lose hard against a SR-2 platform with 2 X5680's.

So your wrong... it wont destory everything out there.

And im willing to bet current westmere-ep's will be very close to it.

I think they are joking around :).
Hans' speculation seems reasonable so far,let's see what next IDF brings us.

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Originally Posted by Drwho?

Well, The AMD bullDozer architect wishes that I answer you (Poker Face), this time, it is like conroe, to figure out the real performance of SB, you will have to wait very close to launch, most of what is out there is not having the right tuning, and I really like it this way. :yepp: :rofl:

After all, competition is like a Poker game ... playing with all the card on the table never worked ...
:shrug:

You can decide to believe AMD about SandyB ... but you would not use the most realable experts about 32nm ... outch .. sorry, could not resist :ROTF:

Just friendly jokes, ok ... ?

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it means intels competitive advantage is lower nm ;) like ati did with nvidia, huh?

it will be exciting to see the battle of Fabs, not designers :D

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Originally Posted by Hornet331

oh please... come one you guys are both in +35years old and you still act like kids? :confused:

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if you dont act like a kid, you die of old age

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Originally Posted by Drwho?

Research and Dev ... This can actually cause you to sell your fabs if you keep doing it ... :)

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Oh man that was so cruel mwaha ha :rofl:

Sandybridge -DT= 4core /8 threads, LGA 1155 3.0ghz clock speed 3.8 turbo , TDP 65-95W all i can really find, Bet you guys didnt know after ivry bridge their bringing out haswell and rockwell which are 16 nm :D

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Originally Posted by NaeKuh

LOL this thread is funny.

And Dr. Who, lets assume you can overclock SB.

It will lose hard against a SR-2 platform with 2 X5680's.

So your wrong... it wont destory everything out there.

And im willing to bet current westmere-ep's will be very close to it.

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Well, sandy bridge generation will have dual CPU too , what was your point?

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Originally Posted by NaeKuh

LOL this thread is funny.

And Dr. Who, lets assume you can overclock SB.

It will lose hard against a SR-2 platform with 2 X5680's.

So your wrong... it wont destory everything out there.

And im willing to bet current westmere-ep's will be very close to it.

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You do know who Dr Who is right? When he talks about Intel he uses the word 'we' and that not just because he's french.

Edit: Actually it might be hard to tell, because he's a little excitable, but I guess it's the first time he's been 'forced' to dampen a rumour that incorrect about this new architecture. He's easily as excited about this as he was when he explained to everyone that the 1366 i7's would overclock fine if was just different and that everyone would enjoy it.

ok ppl when ever you see a thread by me, and you dont like the title....blame the article. i never change the titles, i believe it is more journalistic to leave them as is (no matter how flaming them are). so stop attacking me ok?

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Originally Posted by Hornet331

oh please... come one you guys are both in +35years old and you still act like kids? :confused:

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5 yrs till I have to grow up :(

I want to say so much on this thread things like no, multiplier, voltage, ratio, bios among other things but cant...

:(

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Originally Posted by thebanik

I guess the similar rumors where floating when Nehalem was about to be released, so lets see something more concrete before worrying.......

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considering what :banana::banana::banana::banana: 1156 was for overclocking, 1155 will only be worse. Thats the cost of throwing everything and the kitchen sink onto the cpu package.

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Originally Posted by ajaidev

I want to say so much on this thread things like no, multiplier, voltage, ratio, bios among other things but cant...

:(

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is it a subliminal message that you have an ES sample???

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Originally Posted by slaveondope

:rofl::ROTF: ya sure ok:yepp: companies arent concerned in the least about making money:up:

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thats not what i said... the people who make these decisions at intel dont know the retail market and dont know about overclocking and how powerful of a marketing tool it is... hence, they didnt care about extra logic for overclocking. now its up to the retail guys at intel to fix this by releasing unlocked cpus and trying to implement a divider for dmi to split off bclock from the other clocks again.

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Originally Posted by Hornet331

You still have a reference clock aka base clock and from this clock all other clock domains are sprung off. The difference is, that for mainstream SB you have locked DMI and PCIE multiplicators. So if you increase reference clock you also increase both of this clocks.

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you think they already HAVE a divider in place? that makes no sense... if they would, then the ES cpus would have them enabled to debug it... they clearly arent capable to altering bclock without dmi because there isnt any divider in the current 1155 cpus. and i doubt there ever will be...

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Originally Posted by Hornet331

Well it hasn't to be the PCI-E bus but more like the DMI bus, since on currenct platforms its locked at a fixed frequency and uneffected by increasing the reference frequency. But now for the value/mainstream platform its directly tied to the reference clock.

And if the signals form the DMI bus get "unclear" you lose the comunication to the PCH.

You don't have this problem with the enthusiast plattform since there you can chage the multis and keep them in certain frequency spectrum.

Anyway as some posters already said, it to eraly to say anthing absolute. We'll know more next IDF in september.

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i wouldnt be surprised if the problem is caused by timings not matching up and maybe too small buffers...
dmi is largely based on pciE and pciE is fine with higher clocks, so whatever intel added protocol wise to make it dmi, must be responsible for this... either that or they altered the interface and reduced buffers and cut down the design to safe transistors resulting in worse clock margins...

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Originally Posted by qcmadness

The CPU distributors have the instrument to check if the CPUs are burnt by OC.

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thats what they told you ;)
all those "tools" do is meassure the internal resistance between the different ground and power planes, you cant conclude from that HOW the cpu burned, actually you cant even tell whether it burned our not as it might as well be a pcb or pad issue causing those readings... :P

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Originally Posted by Drwho?

i am the only one with real Perf data in hands ...

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houston to francois, houston to francois, we lost track of you, are you still in the solar system? :D

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Originally Posted by ReverendMaynard

same crap as when the i7's first released. Apparently back then, bclks were locked and we couldn't use more that 1.65v vDIMM. Lol on both counts.

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no, bclocks were limited by the same clock buffer but luckily some people in intel found a way to work around the buffer. and luckily they managed to fix the vdimm issue as well.
in this case the change they would have to do to fix overclocking would be pretty big afaik, so im sceptical if they will do it... BCLOCK overclocking that is... i think they will just release multi unlocked cpus... but for what price? :/

i think theres a lot of misunderstanding about this...
there wont be bclock overclocking, most likely, but whoever is claiming that there wont be ANY overclocking is talking bs...

what many people ARE upset or worried about though is not the claims of no overclocking, BUT:

1. there will be unlocked cpus, but not all of them will be unlocked... which means there will be cpus with locked multipliers and no bclock adjustments either, which will be FULLY LOCKED and wont be able to overclock beyond 5-10%.

2. the unlocked cpus will most likely come at a price premium, so yes, we will still be able to overclock, but this time around we will have to PAY for it... there wont be any free overclocking, and there wont be any massive percentage and price performance overclocks using entry level cpus and pushing them into the realms of the super highend performance wise...

and that sucks...
i sure hope intel or a mainboard maker figures out a way to improve or enable proper bclock overclocking...

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Originally Posted by Metroid

I have heard this just before Nehalen was launched. I believe when I see it. Probably this is just another crapload created.

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it wasnt a load of cr4p then and it isnt now, its getting blown out of proportion, YES! but its not made up or nonsense...
last time around intel solved it, luckily, this time its a bit tougher to solve but lets hope they will get if fixed within the next couple of months...

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Originally Posted by Drwho?

Albert Einstein said "Make everything as simple as possible, but not simpler" , so, I am going to say it as simple as I can, and you guys can quote me to reply to those silly stuffs:
"Overclocking will be different on SB, but it will still be a lot of fun too, and it will be as good/high as usual, and Anybody who claim the opposite just have an agenda"

Sorry for not sharing my results ... hehehe ... but well, you guys are slow on your SuperPi results and so on .... hahahahahaha

Drwho?

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o rly?
so we will see something like this on 1155? ;)
http://www.xtremesystems.org/forums/...d.php?t=255305

and yes, i do have an agenda, i love the overclocking spirit and that thread right there is full of it. getting a cheap piece of equippment and tweaking the cr4p out of it, THATS the true overclocking spirit!
not spending shtloads of money on custom gear and then simply pushing the buttons other people set in place for you...

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Originally Posted by Drwho?

"Intel plans to deliberately limit Sandy Bridge overclocking" ... The tittle is totally BS, but still ... :clap: :clap: :clap:

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on that i actually agree with you :D :toast:
i dont think intel did it on purpose, its more like they unplugged the cables, put them in a different way and all major channels worked for them, but they didnt notice that they unplugged their customers from the playboy channel :D

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Originally Posted by Hornet331

oh please... come one you guys are both in +35years old and you still act like kids? :confused:

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what??
just cause their having a joke on the side? :confused:
i think you misunderstood their posts, i dont think either of their replies was meant in a bad way at all, they are both joking... :D
and francois, respect, im surprised you replied the way you did :D :toast:

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Originally Posted by Johnny87au

Sandybridge -DT= 4core /8 threads, LGA 1155 3.0ghz clock speed 3.8 turbo , TDP 65-95W all i can really find, Bet you guys didnt know after ivry bridge their bringing out haswell and rockwell which are 16 nm :D

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haswell is 16nm now? :confused:

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Originally Posted by god_43

ok ppl when ever you see a thread by me, and you dont like the title....blame the article. i never change the titles, i believe it is more journalistic to leave them as is (no matter how flaming them are). so stop attacking me ok?

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i dont think anybody meant to attack you :)

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Originally Posted by god_43

ok ppl when ever you see a thread by me, and you dont like the title....blame the article. i never change the titles, i believe it is more journalistic to leave them as is (no matter how flaming them are). so stop attacking me ok?

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Don't worry if you hadn't posted the thread, the Dr would probably not have bothered to show up at all, I bet he's looking for a Tamiya Nissan GTR to assemble.

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Originally Posted by saaya

no, bclocks were limited by the same clock buffer but luckily some people in intel found a way to work around the buffer. and luckily they managed to fix the vdimm issue as well.
in this case the change they would have to do to fix overclocking would be pretty big afaik, so im sceptical if they will do it... BCLOCK overclocking that is... i think they will just release multi unlocked cpus... but for what price? :/

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Lol reading that paragraph you are beliveing that engineering only consists out of luck?

What vdimm issue? If you allude to the 0,5V "issue", nope its still there. If you want to kill your nehalem cpu fast just increase ram voltage 0,5V above the qpi voltage and watch it die (over several days).

Creating and fixing problems has hardly something to do with luck, but rather with hard work, knowledge and determination.

@ saaya
http://upload.wikimedia.org/wikipedi...oadmap.svg.png

So Intel is pretty confident SB will be faster than Bulldozer it seems. Is Intel confident that their integrated GPU will be faster than AMD's GPU? If so, that is FAR more interesting than hearing about the CPU cores.

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Originally Posted by Johnny87au

@ saaya
http://upload.wikimedia.org/wikipedi...oadmap.svg.png

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thats rockwell, haswell is still 22nm...

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Originally Posted by Mechromancer

So Intel is pretty confident SB will be faster than Bulldozer it seems. Is Intel confident that their integrated GPU will be faster than AMD's GPU? If so, that is FAR more interesting than hearing about the CPU cores.

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My guess is that the GPU in SB won't be quite as strong as the GPU in Llano (Bulldozer does not come with an iGPU, at least not until some future part), but that both will be strong enough that the discrete GPU market will shrink considerably; Only "serious gamer / designer" folks will bother adding one.

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Originally Posted by saaya

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Originally Posted by Drwho?
i am the only one with real Perf data in hands ...

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houston to francois, houston to francois, we lost track of you, are you still in the solar system? :D

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Do you really Think that the parts out there has final tuning in? look at the stepping ... :rofl:

SandyB is very different than what you are use to ... may be you are a little bit over confident ... To quote morphius, "Don't think you are, know you are!"

in my case, I prefert Kouros ... Houston is not launching as much space craft than Kouros.
http://newsimg.bbc.co.uk/media/image...07585685-1.jpg ... and i am in perfect synch with what I know about SandyB :) :up: :up: :up: :up:

Francois, i would like to thank you for participating here, it is great that you take the time to talk to us!

But, i do have a question, any timeframe on the G3 intels? and will they have 6gb/s interface?:D

DrWho,to get things straight, you are denying 2 of the Hans' speculations about the L3 cache located next to each core and about the SSE unit organization?

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Originally Posted by Drwho?

Do you really Think that the parts out there has final tuning in? look at the stepping ... :rofl:

SandyB is very different than what you are use to ... may be you are a little bit over confident ... To quote morphius, "Don't think you are, know you are!"

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Are there even "classic" steppings with SB, cause with SB we should get upgradeable firmware? I still wonder what capabilities this FW has, and how much you can influence the CPU with it.

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Originally Posted by Hornet331

Are there even "classic" steppings with SB, cause with SB we should get upgradeable firmware? I still wonder what capabilities this FW has, and how much you can influence the CPU with it.

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well, this is not firmware, this is the regular systems, but it is much more advanced now that things are getting integrated. Especially on the power management side, you don t want laptop parts and desktop parts to behave the same. Nothing new, just more nodes to adapt to where stuff go. If you look at the literrature about Nehalem, it is already in. Thinking that the receipe to optimize all of this is in those leaked sample is funny. What would mean that Intel People are so good that we don t need the silicon to tune the CPU ... lol I wish! But sorry very much like you and me, Human! :yepp:

Let's take an example, turning OFF the top of the 64 to 128bits of an SSE execution can save 50% of the power, in the mean time, turning it back on is not instantanious ... so, for a workstation, you don t want that feature ON, while, on a laptop , you really want this ... Now, if you go through the all design of a core like Nehalem, you ll find many places where you can enable those kind of power saving. you want to turn off your cores when you see only single threaded workloads, etc ... all of those policies need to be tuned.
The new generation of CPUs are not what people are use to, there are reason why the Core i3/i5 have those amazing level of performance with the same power envellope as Penryn ...
Power gating is very powerfull if you take the time to do it very deep everywhere and you have a power control unit smart enough to do it right.

Those new processor architectures are really amazing, provide awesome flexibility, with billion like transistor count.
Intel Rarely speak about it, but we do have performance counters all over the CPU, monitoring all the phenomena inside the machine, and vTune allow you to get access and see the statistics about all of this. If you are really into performance and CPU architecture, there are documentation and free version of vTune. help yourselfs, and look at all those nodes that can be monitored. The CPUs are not 486 or Pentium like for a long time, NEhalem toke it to a much higher level, and this was only the 1st step.

Francois

PS: by the way, i just posted this using Wimax enable Core i7 620M, and I am in the middle of the silicon valley, Indoor , using WIMAX-4G
http://www.speedtest.net/result/890654237.png
This is the way to go :) ==> http://www.clear.com/

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Originally Posted by Drwho?

If you are really into performance and CPU architecture, there are documentation and free version of vTune. help yourselfs, and look at all those nodes that can be monitored. The CPUs are not 486 or Pentium like for a long time, NEhalem toke it to a much higher level, and this was only the 1st step.

Francois

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where? i must have this.:)

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Originally Posted by Drwho?

well, this is not firmware, this is the regular systems, but it is much more advanced now that things are getting integrated. Especially on the power management side, you don t want laptop parts and desktop parts to behave the same. Nothing new, just more nodes to adapt to where stuff go. If you look at the literrature about Nehalem, it is already in. Thinking that the receipe to optimize all of this is in those leaked sample is funny. What would mean that Intel People are so good that we don t need the silicon to tune the CPU ... lol I wish! But sorry very much like you and me, Human! :yepp:

Let's take an example, turning OFF the top of the 64 to 128bits of an SSE execution can save 50% of the power, in the mean time, turning it back on is not instantanious ... so, for a workstation, you don t want that feature ON, while, on a laptop , you really want this ... Now, if you go through the all design of a core like Nehalem, you ll find many places where you can enable those kind of power saving. you want to turn off your cores when you see only single threaded workloads, etc ... all of those policies need to be tuned.
The new generation of CPUs are not what people are use to, there are reason why the Core i3/i5 have those amazing level of performance with the same power envellope as Penryn ...
Power gating is very powerfull if you take the time to do it very deep everywhere and you have a power control unit smart enough to do it right.

Those new processor architectures are really amazing, provide awesome flexibility, with billion like transistor count.
Intel Rarely speak about it, but we do have performance counters all over the CPU, monitoring all the phenomena inside the machine, and vTune allow you to get access and see the statistics about all of this. If you are really into performance and CPU architecture, there are documentation and free version of vTune. help yourselfs, and look at all those nodes that can be monitored. The CPUs are not 486 or Pentium like for a long time, NEhalem toke it to a much higher level, and this was only the 1st step.

Francois

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BUT..BUT what about those of us that don't want any powersaving anything turned on.My machines run at 100% load 24/7/365.25...:D

Although I have a pair of L5630 32nm quads that I'm testing in my SM X8DA3 board right now and seeing 175w usage(8C/16T@2130MHz) on a kill-a-watt is very pleasing to my wallet!

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Originally Posted by Movieman

BUT..BUT what about those of us that don't want any powersaving anything turned on.My machines run at 100% load 24/7/365.25...:D

Although I have a pair of L5630 32nm quads that I'm testing in my SM X8DA3 board right now and seeing 175w usage(8C/16T@2130MHz) on a kill-a-watt is very pleasing to my wallet!

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well, let s say for example that you run a non optimized code, like PhysX (lol) where the code is only using x87 ... or scalar SSE for the x64 version (low 64 bit), then, Nehalem architecture will turn off the high part of the execution unit, and save power to give you more frequency using Turbo ... helping to maximize your experience and processing power. In the case of overclockers, well, when you OC, those features mostly turn off when they are tuned well ... and this is where we go back to the point that tunning needs to be done and applied right.
early proto stepping never get the final tuning.

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Originally Posted by Chumbucket843

where? i must have this.:)

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I think hes talking about this ;)
http://software.intel.com/en-us/intel-vtune/

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Originally Posted by Drwho?

well, let s say for example that you run a non optimized code, like PhysX (lol) where the code is only using x87 ... or scalar SSE for the x64 version (low 64 bit), then, Nehalem architecture will turn off the high part of the execution unit, and save power to give you more frequency using Turbo ... helping to maximize your experience and processing power. In the case of overclockers, well, when you OC, those features mostly turn off when they are tuned well ... and this is where we go back to the point that tunning needs to be done and applied right.
early proto stepping never get the final tuning.

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Thanks for the info..
Will we see dual socket SB boards?:D
( and when,chips I can get, boards you have all locked away for yourself! ):rofl:

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Originally Posted by Chumbucket843

where? i must have this.:)

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http://search.intel.com/default.aspx...=en_US&q=vtune

Here are some of the litterature on vtune ...

here is some usefull resources ...
http://www.intel.com/Assets/PDF/manual/252046.pdf
http://search.intel.com/default.aspx...0documentation

You can see a lot of very intimate details of the architecture if you spend the time to read all of this.

Francois

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Originally Posted by NBF

I think hes talking about this ;)
http://software.intel.com/en-us/intel-vtune/

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i want the free one. im not paying $700 for vtune because it's not worth it for me. all i want to do is check out statistics on ipc, branch prediction, caching etc.

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Originally Posted by Chumbucket843

i want the free one. im not paying $700 for vtune because it's not worth it for me. all i want to do is check out statistics on ipc, branch prediction, caching etc.

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Its free for evaluation for a 30 day period.

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Originally Posted by Chumbucket843

i want the free one. im not paying $700 for vtune because it's not worth it for me. all i want to do is check out statistics on ipc, branch prediction, caching etc.

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http://software.intel.com/en-us/arti...ware-download/

but only for linux. But v-tune offers a lot of information for basic information you also could try: http://www.cpuid.com/softwares/perfmonitor.html

edit: damn didn't noticed perfmon doesn't work with nehalem...

and thx for the reply Francois. :)

@Drwho?
The mainstream Sandy Bridge is getting out earlier than expected, maybe the same will be the case for high-end SB?. Do you have any estimate when we can expect the real existing stuff?

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Originally Posted by Sam_oslo

@Drwho?
The mainstream Sandy Bridge is getting out earlier than expected,

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It's been shipments in Q4, launch in Q1 for a long time now. Some dope wrote an article saying it was coming early after misinterpreting Otellini's CC comments that the SB *ramp would be faster* due to strong customer interest. Intel did not say anything was coming *sooner*, and Intel has repeatedly said that customers do not care for Q4 launches, they prefer Q1... so even if they COULD launch it in Q4... they wouldn't.

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Originally Posted by terrace215

It's been shipments in Q4, launch in Q1 for a long time now. Some dope wrote an article saying it was coming early after misinterpreting Otellini's CC comments that the SB *ramp would be faster* due to strong customer interest. Intel did not say anything was coming *sooner*, and Intel has repeatedly said that customers do not care for Q4 launches, they prefer Q1... so even if they COULD launch it in Q4... they wouldn't.

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Indeed.

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Originally Posted by Sam_oslo

@Drwho?
The mainstream Sandy Bridge is getting out earlier than expected, maybe the same will be the case for high-end SB?. Do you have any estimate when we can expect the real existing stuff?

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I can t answer those kind of Question ... I love my job too much ;-) :rofl:

drwho, can you say anything about the third gen atom? :)

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Originally Posted by Drwho?

I can t answer those kind of Question ... I love my job too much ;-) :rofl:

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Can you answer mine from above?:D
Thanks for the info..
Will we see dual socket SB boards?
( and when,chips I can get, boards you have all locked away for yourself!

and one more..will SB be limited to 4 cores?

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Originally Posted by Movieman

Can you answer mine from above?:D
Thanks for the info..
Will we see dual socket SB boards?
( and when,chips I can get, boards you have all locked away for yourself!

and one more..will SB be limited to 4 cores?

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Actually he's already mentioned dual socket SB.

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Originally Posted by Drwho?

Well, sandy bridge generation will have dual CPU too , what was your point?

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Originally Posted by Movieman

and one more..will SB be limited to 4 cores?

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Why shoul SB limited to 4 cores?

SB is the name for the whole µarch, so we get teh full spectrum. Form dualcores up to 8+ cores.

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Originally Posted by Iconyu

Actually he's already mentioned dual socket SB.

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Originally Posted by Hornet331

Why shoul SB limited to 4 cores?

SB is the name for the whole µarch, so we get teh full spectrum. Form dualcores up to 8+ cores.

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Hush guys, MM is asking tricky questions to get him talking about the real deal. He didn't fall for my trick tho. :rofl:

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Originally Posted by -Sweeper_

drwho, can you say anything about the third gen atom? :)

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yeap, it is much faster than arm ... with better low power ...
(Now, i ll get a lot of hate mails ;) ) hehehehe ... :ROTF: :ROTF: :ROTF:


This is my opinion, it is ok to disagree, not ok to crusify me :up:

Let 's close this thread ... all was said ... Intel does not have a crazy plan to stop overclocking, otherwise, i would have hanged the dudes in my attic :) (Metaphore)

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Originally Posted by Movieman

Can you answer mine from above?:D
Thanks for the info..
Will we see dual socket SB boards?
( and when,chips I can get, boards you have all locked away for yourself!

and one more..will SB be limited to 4 cores?

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4 cores for 1156, not sure of 1355

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Originally Posted by Drwho?

yeap, it is much faster than arm ... with better low power ...
(Now, i ll get a lot of hate mails ;) ) hehehehe ... :ROTF: :ROTF: :ROTF:


This is my opinion, it is ok to disagree, not ok to crusify me :up:

Let 's close this thread ... all was said ... Intel does not have a crazy plan to stop overclocking, otherwise, i would have hanged the dudes in my attic :) (Metaphore)

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Now we just need dual core versions, running meego with a decent gui ^^

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Originally Posted by Drwho?

yeap, it is much faster than arm ... with better low power ...
(Now, i ll get a lot of hate mails ;) ) hehehehe ... :ROTF: :ROTF: :ROTF:


This is my opinion, it is ok to disagree, not ok to crusify me :up:

Let 's close this thread ... all was said ... Intel does not have a crazy plan to stop overclocking, otherwise, i would have hanged the dudes in my attic :) (Metaphore)

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Any chance of pushing for external reference voltage control for internal receiver lines on critical signal stages? I know all references are internally derived (makes sense from many perspectives). This stuff is all automated now and I wonder if we can increase clocking margins somewhat on some processors with a manual shift - the effects of sub-zero temperatures on certain Tx stages can change voltage swing.

[QUOTE=Hornet331;4483956]Lol reading that paragraph you are beliveing that engineering only consists out of luck?

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Originally Posted by Hornet331

What vdimm issue? If you allude to the 0,5V "issue", nope its still there. If you want to kill your nehalem cpu fast just increase ram voltage 0,5V above the qpi voltage and watch it die (over several days).

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err no? what makes you think so?
ive run vdimm and vtt over .5v apart for 2 or 3 weeks without an issue...
vtt was 1.2v and vdimm 1.9...
it wasnt stable, i thought the mem was dieing but then saw vtt was at default... i must have had forgotten to adjust it when i tweaked the system 2-3 weeks before i noticed this.

and no, i dont think it has anything to do with luck :confused:
where exactly do i say something that sounds that way?
the part of my post your quoted doesnt hint at luck at all... :confused:

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Originally Posted by Johnny87au

@ saaya
http://upload.wikimedia.org/wikipedi...oadmap.svg.png

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well thats what i said... its 22nm, not 16... i guess i misunderstood his post, it sounded as if he was saying haswell was 16nm...

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Originally Posted by Drwho?

Do you really Think that the parts out there has final tuning in? look at the stepping ... :rofl:

SandyB is very different than what you are use to ... may be you are a little bit over confident ... To quote morphius, "Don't think you are, know you are!"

in my case, I prefert Kouros ... Houston is not launching as much space craft than Kouros. ... and i am in perfect synch with what I know about SandyB :) :up: :up: :up: :up:

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no, i never said that and im sure the final parts will be a few % faster per clock, i noticed the same with lynnfield... its funny cause what i wanted to hint at was you sounding overly confident that you are the only one out there with accurate sb information... and you reply telling ME that i am overconfident... :lol:
well im not making any big claims, and in this thread i havent made any claims about performance or clocks at all... so why are you telling me i sound overconfident? :confused:

lol at kuorus :D :toast:

oh one more thing, can you say anything about skulltrail2? :D

Quote:

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Originally Posted by terrace215

It's been shipments in Q4, launch in Q1 for a long time now. Some dope wrote an article saying it was coming early after misinterpreting Otellini's CC comments that the SB *ramp would be faster* due to strong customer interest. Intel did not say anything was coming *sooner*, and Intel has repeatedly said that customers do not care for Q4 launches, they prefer Q1... so even if they COULD launch it in Q4... they wouldn't.

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your saying sb wont come out until q1 2011?
or 1355/2011 wont come out until q1 2011?

So , does that mean in the current generation the SB and the NB has separate base clock ?
I always thought they both relied on a single clock generator , I guess that explains why something like the PCI-E and SATA bus operate at a frequency of 100MHz .

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your saying sb wont come out until q1 2011?
or 1355/2011 wont come out until q1 2011?

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SB 1155 is supposed to have production shipments in Q4, and launch in early Q1. So, systems and retail parts should not be available before Q1, although maybe some parts will leak into shops in asia?

SB 2011 (is there even a 1355 anymore, I think desktop may have moved to 2011?) is later, due in mid-2011.

DrWho: are you running on D0/ES2 step or later?
BTW: isn't that PCU uController in SNB based on ARM core?:rofl:

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Originally Posted by terrace215

SB 1155 is supposed to have production shipments in Q4, and launch in early Q1. So, systems and retail parts should not be available before Q1, although maybe some parts will leak into shops in asia?

SB 2011 (is there even a 1355 anymore, I think desktop may have moved to 2011?) is later, due in mid-2011.

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well i heard early q4 launch to catch the christmas shoppers... the boards are def ready... :shrug:

and yes, like i said before, i havent heard of 1356 in ages... actually i never heard of 1356, i just heard and saw that there will be a 1366 replacement with vrm12 with a few pins added or removed. it would make sense if intel canned B2 aka 1356 and went for R for both MP, DP and sever and workstation SP... the costs of R and B2 were probably so close to each other that it didnt make much sense to have two platforms? especially since it fragmented the server market... and well, you want tri channel with less cores? you can have that with a socket R cpu and mainboard... just dont connect some of the pins and there you go...

so yeah, i never actually heard of 1356, all i heard of was quad channel, 8+ cores with bclock overclocking... from what i can see and read atm, im very sure that this is 2011 and not 1356...

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Originally Posted by Mumak

DrWho: are you running on D0/ES2 step or later?
BTW: isn't that PCU uController in SNB based on ARM core?:rofl:

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shhhhh! :D
come on mumak, leave francois' home-made beef jerky in his attic and dont embarrass him here ^^

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Originally Posted by saaya

well i heard early q4 launch to catch the christmas shoppers... the boards are def ready... :shrug:

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Well, I guess anything is possible, though that goes against their claim that OEMs dislike Q4 launches, and when asked if Sandy Bridge was coming early on the CC they said:

David Wong – Wells Fargo

Thank you very much. Paul, you mentioned that you are very excited about Sandy Bridge and this was one of the reasons for accelerating 32 nm, does this mean that you are planning to bring out Sandy Bridge earlier than scheduled, and when might we expect to see first launches of systems that have Sandy Bridge in them?

Paul Otellini

Well, we will talk more about the product in a lot of detail at IDF in a couple of months. In terms of product granularity, I really don’t want to get more granular than we have been which is that we will ship Sandy Bridge for revenue this year, late this year.



So, unless he is sandbagging, shipping for revenue LATE this year probably rules out a launch this year, since they like a month or two of shipments prior to launch, at least lately. And moreover, with Llano stuck in process hell, there's no competitive pressure to launch early...

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Originally Posted by Sam_oslo

We are talking about upcoming mainstream LGA1155 Sandy Bridge CPUs, not the high-end which comes later.

It is a natural move if Intel try yo to limit the OC of mainstream to prevent a direct competition with hight end. I guess that's the lesson Intel has learned from i7, when we all bought a sub $300 920 and OCed it to beat the $1000 975.

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Exactly!

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Originally Posted by Xanth

Exactly!

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oh come on... like this is the first time intel cpus could overclock which resulted in some people buying a cheaper cpu and overclocking it... yeah, thats never been here before :rolleyes:

and 300$ for a 920... why do you think they priced the cheapest 1366 cpu that high? cause they KNEW a lot of people would overclock... an i7 probably costs intel around 50$ to make, if even that... dont think that intel isnt perfectly aware of this situation and adjust prices accordingly...

and terrace... no idea... i dont get why oems dont like q4 btw...
why would that be? :confused:

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Originally Posted by informal

DrWho,to get things straight, you are denying 2 of the Hans' speculations about the L3 cache located next to each core and about the SSE unit organization?

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DrWho, good dodge, maybe you are re-enacting the French football team who went on strike

:rofl:

Would you please give an answer to informals question....

:yepp:

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Originally Posted by Drwho?

Well, sandy bridge generation will have dual CPU too , what was your point?

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Im sorry werent we talking about 1155?

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Information provided by Intel in its own presentations about its upcoming mainstream LGA1155 Sandy Bridge CPUs appears to confirm the company has designed the CPUs to deliberately limit overclocking.

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Didnt you say 1155 was gonna blow away everything?
Did we even get into 2011?
Isnt this article @ 1155 specifically?

Are you telling us, 1155 and 2011 are gonna be identical?
:shakes:

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Originally Posted by Iconyu

You do know who Dr Who is right? When he talks about Intel he uses the word 'we' and that not just because he's french.

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Yes i know who he is... and honestly i can care less if he's gonna pull NDA gag orders.

He's trying to throw Han's finding under a Rug, and make us all deny it.

Ie.. he's trying to control information.

And im also like this to JFAMD and AMD, so Intel doesnt get a freebie from me either.

guys, francois doesnt have to answer any questions you know...
you should ask him in a nice way and he might actually reply, even if he avoids the main point of the question...
if you push him to answer your questions hes just gonna roll his eyes and close the tab...

Quote:

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Originally Posted by saaya

guys, francois doesnt have to answer any questions you know...
you should ask him in a nice way and he might actually reply, even if he avoids the main point of the question...
if you push him to answer your questions hes just gonna roll his eyes and close the tab...

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Well thats completely up to him, isnt it?

Dont think he is at the age where he will throw his toys out the pram.........saying that; he is French, LOL, hehehehehee

(Yes. just kidding :) ;) )..........

Dr Who:im confused, whats SB highend platform? LGA 1356 or LGA2011 (desktop only). At next IDF we will see "new roadmap" with this CPUs? Thx

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Originally Posted by Mumak

BTW: isn't that PCU uController in SNB based on ARM core?:rofl:

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Nop ... The PCU is actually much faster than an ARM ... :rofl: :ROTF: :rofl: :ROTF: :clap: :yepp: :rofl: :ROTF: :rofl:

pls, answer to me ,-). If can it :-)

I don't think that this sort of info can be disclosed to public yet.

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Originally Posted by FlanK3r

pls, answer to me ,-). If can it :-)

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