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Where did you see this spec? AMD has made no mention of latiencies... a link would be great.Quote:
Originally Posted by informal
Latency is fixed with repect to clock ticks, some programs report in ns (nanoseconds), but when converted to clock cycles by dividing by the clock period is fixed by cycle.
I know im crude but i bet my right foot im right on that one.Quote:
Originally Posted by informal
You will never face the fact even if Hector himself comes over to your house in the middle of the night and say we lost this round.
I heard every excuse there is about about this CPU so far, its secret and its cat and mouse, sending underperforming cpus bla bla bla..
Whatever shows up its a new excuse to counter with.
Today its finding the golden powerup at 2.4ghz that will make VIA buy Intel for 1 buck.
ROFL. Right.Quote:
Originally Posted by informal
Care to share your source?
I'm also calling BS on this one. Please show us a historical example of where a BIOS update provided >5% improvement in performance.Quote:
Originally Posted by informal
And since you are pretty notorious for not providing sources, please give us your source as well. ;)
IPC cannot scale better than linearly with freq.It only can go lower(due to various reasons).The point is the platform(all around) was not final,and this is backed up with his statement that in week time they saw a good improvement(measurable,not 5%) with new samples and boards.
PS This is going nowhere, to be frank.The whole thing cannot be discussed since we actually know nothing about the stage of readiness of the whole systems used(AT's and from the dude from coolaler's forum)
Ok so this is fair... but once all is set in stone, BIOS, memory, etc... a 2.6 barcey will be 30% faster than a 2.0 GHz barcey.... that we can agree upon.Quote:
Originally Posted by informal
But the coolaler's system is interesting to debate, even though I do agree -- there is skepticism. The CPUID behavior appears to indicate that this is DVT not EVT.
Agreed, yet you keep insisting (against the limited evidence) that K10 is going to be a C2Q killer.Quote:
Originally Posted by informal
While we all hope that is true, if just for the sake of competition, there is no evidence to support that claim. And I believe that is the major beef that people have (unsubstantiated claims).
Go laugh on the floor at yourself.Quote:
Originally Posted by mstp2009
http://www.techarp.com/showarticle.a...tno=424&pgno=2
Above contains a mistake by techarp(it was supposed to say north bridge,but the point is clear)Quote:
L3 Cache
The Barcelona features a large, shared L3 cache that is at least 2MB in size. This L3 cache will be shared by all cores, whether it's a dual-core or quad-core processor.
This cache is 32-way set associative and is based on a non-inclusive victim cache architecture. The latency for any core to retrieve data from the L3 cache is said to be less than 38 clock cycles. Oddly enough, AMD says the actual latency depends on the clock speed of the south bridge.
True -- if there is going to be a competitive Q4 and 2008 we need a good run from K10. There is so much conflicting info from hearsay to leaked benchmarks we are still pretty much in the dark.Quote:
Originally Posted by mstp2009
That is NOT a mistake by techarp. It is correctly listed as southbridge. Northbridge latency is the IMC latency, and that is constant. Southbridge (i.e. peripheral interconnect) is going to vary depending on the external bus speed.Quote:
Originally Posted by informal
Interesting... this is something I had not seen... so AMD is adjusting cycle latency to account for clock in L3.... wow, they are really trying squeeze as much from it as they can....Quote:
Originally Posted by informal
Latency is a physical manifestation of the design/processing of the chip, it is the time required for the request/read and/or write to complete the job, this is temporally fixed, for worst case the CPU sets that to x number of cycles such that X*period > min time for latency, interesting..... if this is true, then these chips will be difficult to overclock, I wonder if they are giving options to increase the L3 latency in BIOS?
Finally ,agreed :).Quote:
Originally Posted by JumpingJack
AS for the coolaler dude,the results are very strange.Don't know if he has the DVT,maybe so.But the platform he used is unknown,as well as the bios involved(i remember AnandTech said back in June,that K10 at that point needed some have bios patching in order to work).Fits perfectly with ES that were only for platform testing and not perfomance evaluation.AnandTech even got 2 samples but couldn't get them to even boot the system even after 1 month)
Haaaa, I did not see the southbridge part, what does the soutbridge have to do with anything the L3 is doing?Quote:
Originally Posted by mstp2009
I think you are wrong as for the OC part.These chips will be easier to OC than X2s based on K8.SInce the L3 and IMC reside on the one and the same power plane,one can set it to higher/lower clocks(and in full async. from the 4/2 cores) in order to get the highest OC possible with good cooling.Quote:
Originally Posted by JumpingJack
Nothing,mstp is talking out of his ass :)Quote:
Haaaa, I did not see the southbridge part, what does the soutbridge have to do with anything the L3 is doing?
Only thing I can think of is that AMD has the L3 cache acting similar to what we see in the snoop filter of the newer Intel server chipsets. Prefetching data from RAM or (possibly) the hard drive?Quote:
Originally Posted by JumpingJack
Neither make much sense, however. As you correctly pointed out, have an adjustable speed (i.e. latency) on the L3 cache would make increasing the clocks on K10 a b!t#@. And there is no easy fix to that except to LOCK the L3 cache back to processor frequency.
Was that called for?Quote:
Originally Posted by informal
You are a p r ick.
Actually, I think the split power plane will make it harder.... but now it is becoming clear, I think TechARP may have misprinted, it makes more sense that the L3 will fix withrepect to the IMC (northbridge) fequency and that will vary with the frequency divider necessary to drive the memory.Quote:
Originally Posted by informal
In terms of OCability, this may or may not be true.... the details of how AMD has implemented the L3 cache is sketchy now based on your link.... if they are adjusting the number of L3 cycle latency dynamically (as you interpret), this means that they are adjusting to keep the L3 cycle latency at the border edge of the physical time it takes for signalling L3... if this is true, overclocking will crap out the L3 very very early. This is why I wonder if they will provide BIOS writers (or should I say BIOS writers provide us) with the ability to adjust the L3 latency cycles.
All I know is I want to see AMD come out with a dual socket 8 core system that can kick the crap out of my clovers.
That will accomplish many things:
1) Strengthen AMD's share of the marketplace
2) Force Intel to "work" harder
3)Drop prices for all of us
4)Give the AMD fans something to smile about.
It's been a long year for you guys and I can understand the frustration.
I'm not being sarcastic there, I mean that.
I think everyone can agree with this.Quote:
Originally Posted by Movieman
QFT!Quote:
Originally Posted by Movieman
Agree also, but i lost faith.
Intel will get even bigger and AMD wont catch up.
AMD has to go with low price to sell if the cpu isnt performing.
It just look bad..and dark and evil Intel is happy.
Forgeting all the other points, there is one thing that tends to get overlooked that AMD does that is much better than Intel's solution: cpu placement on a dual socket board.
With the large spacing that AMD uses one can use a top end aftermarket heatsink.
On the intels with just one inch between the sides of the sockets your much more limited..
This is in general true, but I think Intel did themselves on very good one by keeping 45 nm Penryn family in the same socket, and evidently drop in.... this does not happen often.Quote:
Originally Posted by Movieman
You know what is funny, I pulled this paper out quite a while ago and archived it away.... thinking cool... but had not read it.Quote:
Originally Posted by informal
http://www.cs.utah.edu/~rajeev/pubs/ieeetoc03.pdf
I just remembered I had it....
Yes, and I have confirmation that my current SM boards will take the Harpertowns with the current available bios from SM site.Quote:
Originally Posted by JumpingJack
Got that from SM on the phone this week..
I just want them to add another 2 inches between the sockets so we can use some good heatsinks..:D
Here is more info on AMD's cache architecture for K10.
DIRECT from the horse's mouth:
http://developer.amd.com/article_print.jsp?id=173
I would like to point out how the L3 cache works:
EDIT - AMD seems to think Anandtech did a GOOD evaluation of the Barcelona cache structure:Quote:
Another aspect makes the L3 cache unusual is that it is not fed from memory. Rather, it serves as a spill-over cache for items evicted from the L2 cache. So when the L3 cache loads an item into L1 cache and the cache manager can delete it from the L3 cache, room is created for more spill-over from the L2 cache. Eventually, the data item in the L1 cache will make it back to the L2 cache (when the processor is done with it) and the cycle could repeat itself. However, if the processor should need the item right away, it can find it in the L2 cache, if it has not been pushed back out to the L3 cache-and it would thereby obtain faster turnaround. AMD has not published figures on the latency of data access in the L3 cache, so it's not possible currently to know how much faster.
Quote:
A thorough, technical, and very detailed description of the Barcelona chip, by an independent authority AnandTech, contains good coverage of the cache architecture:
http://www.anandtech.com/cpuchipsets...spx?i=2939&p=1