I don't think that's exactly possible, because of the drivers. Unless they are kept in resources and loaded on the fly.
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I don't think that's exactly possible, because of the drivers. Unless they are kept in resources and loaded on the fly.
First memset version don't use an installer,Quote:
Originally Posted by Dee
but I need to use it since I added support for OS 64 bit.
It's a drawback come to TVicPort driver.
Yes, when I tried to make my own portable version I found that it wouldn't run because it gave an error about a certain DLL and TVicPort.Quote:
Originally Posted by FELIX
No worries, Felix. Thanks for the reply.
Hi,
Can someone please explain the Tref value? My memory has a Refresh Period specification of 12us. How does that relate to the values set by the Tref parameter? eg, 3120T etc...
STeve.
tREF = tREFI / tCK
tREFI = self-refresh interval in us, its usually 7.8us but some cases are higher on lower end memory ics.
ie. for 7.8us its value is 7800[ns]
tCK is the clock period,( 1us / ddr_io_frequency )
ie for 1066mhz ddr, tCK = 1000 / 533 = ~ 1.86ns to complete a clock cycle.
tREF = 7800[ns] / 1.86[ns] = 4194 clock cycles in a 7.8us self refresh interval for ddr-1066, since tCK = x[T], tREF = 4194T
Hope that explains it well enough for you mate
edit: additonal info
Self refresh exists on its own plane with no real relationship to precharge, write, read and activate timings as a method of minimizing re-fetching data externally that is lost over time as memory cells lose their charge, and with higher IO frequencies this has a substantial effect on resultant latency, ie if the hit to fetch the data from the CPU is say 60 clocks, then we've added an additional 55ns of latency for 1066mhz ddr, where instead by ensuring that the data is paged correctly in advance the latency to access and read it back is simply CAS turn around + row precharge + read preamble + burst latency + minimum wait to align data strobe with next rising edge of clock. That is best case scenario for a memory read and requires the minimal amount of time to complete, which is essentially why a Higher tREF shows a respectable drop in resultant latency, since any fetching is done while the data isn't being requested so even the worst case scenario of a hard drive read is negligible since it is being done while the data is having a lunch break! It's possible that too large an interval for self refresh may work the opposite and increase latency as memory cells begin to lose their charge before the next self refresh cycle, but theoretically unless the IC's are very poor quality they should hold their charge at least long enough for an extreme worst case scenario that may excessively delay the next self refresh cycle.
I would not have better made. :)
Also, higher value is better for tREF.
hey FELIX.
get tool, Used it for Years now :D
Any chance of Intel G41 Support ?
I can help you test if you want :)
Could you send a register dump (with cpu-z->last table->register.txt) at memset@hotmail.fr
Hi everyone,
I just downloaded MemSet 3.5 to tune my DDRII RAM because my BIOS only allows me to set CAS# latency, not the other 3 values (tRTC, tRP, tRAS, etc). The program works great when changing my timings in-windows as long as I don't do anything stuipid. However, when the program is set to startup and apply the settings when windows loads, it causes my system to completely lock-up. Even when the values are correct. It seems for some reason executing the MemSet\MemSave\MemSet.exe file at any time causes this to happen, regardless of the timings set in the program.
Any ideas why this happens? My system:
Gigabyte GA-M55SLI-S4 mobo with nForce 4 chipset
AMD Athlon 64 X2 5000+ dual core processor (2.6GHz)
nVidia GeForce 8800GTX w/ 177.92 drivers
2GB of G.Skill DDRII ram @ 800MHz (Product name:F2-6400CL4D-2GBPK)
Windows XP Pro SP2
Quote:
Originally Posted by Cornflake
In your BIOS press CTRL+F1 - it will allow you to change more timings.
Nope, already tried that. It does bring up hidden settings, but not for the RAM timings screen :(
...support was added for G41 and Q45 in this version: memset359betaQuote:
Originally Posted by Nosfer@tu
Let me know the result... :)
...could you send me a register dump (with cpu-z->last table->registers.txt)Quote:
Originally Posted by Cornflake
and the memset.ini file you add in C:\MemSet\MemSave\
Send it at memset@hotmail.fr
does any body know why i get this everytime i click spd button? ive tried 3.5.3/3,5,8/ 3.5.9 all do the same thing,thankshttp://i38.tinypic.com/1255nxz.jpg
hey felix did anyone send you a dump file for nehalems
:)
radaja
I have the same situation. Dunno why`s that.
Memset running on P5Q Pro. Notice anything wrong? :confused: Hint: the board doesn't support DDR3.
BIOS is 1306. OS is Vista x64 SP1 + updates. DRAM is Mushkin HP2-6400.
Oh, and it's a minor issue but BIOS FSB setting is 416.
With the situation above, what timings are worth experimenting with? tRD?
Voltage is currently 1.82V and I'd prefer not to go above 2.00V.
this is not a memset issue
other software like CPUz reports the same thing
its a chipset thing
-> radaja or WaterFlex: could you send a register dump (with cpu-z->last table->register.txt) at memset@hotmail.fr
-> dinos22: I already get some NHM dumps, but Intel datasheet is not available for now,
so don't expect a new beta before 2 or 3 weeks.
Done.:cool:Quote:
Originally Posted by FELIX
oh i seeQuote:
Originally Posted by FELIX
no worries :up:
im not sure how to do it. but it looks like waterflex already sent it
No. CPU-Z 1.48 correctly reports DDR2.Quote:
Originally Posted by dinos22
latest cpuz vs memset.Quote:
Originally Posted by DMF
doesn't bother me cause I know about it and everest reads it fine.
I don't know why, but ,on some system, frequency is represented a little higher.
In this case, cpu-z is right.
WaterFlex and radaja: could you make a test with this version: memset359beta
@felix, im still getting this. can you tell me how to send a dump? thank you. http://i35.tinypic.com/2gxlc1u.jpg
First run CPU-Z, click on "About", Click on "Register Dumps (.txt)" save the text where you want, and send it at memset@hotmail.fr
Hey Felix, what about X58 support? I tried using the latest version on Intel Smackover and it didn't work. Do you need a Register Dump?
-> Monstru: no Intel datasheet available for now; Don't expect a new beta before 2 or 3 weeks.
-> WaterFlex and radaja: Sorry guys, I made a mistake in last version;
I think this version will run...
thanks felix! it works now. http://i37.tinypic.com/1zvfl75.jpg
You must use normal size (96ppp) to use this software;if you want change it: on Office->Right click->Property->Parameters->Advanced->General. Choose 'normale size'.
The frequency difference doesn't bother me (much) either. But the report of DDR3 most definitely does.
Could you try with the last beta...
Are these datasheets you're looking for?
Core I7 register: http://download.intel.com/design/pro...hts/320835.pdf
X58: http://www.intel.com/Assets/PDF/datasheet/320838.pdf
...already got it. :)
man this new bate works WAY better on vista 64 bit than the last version thanks felix!
Awesome can't wait for x58 supported version.. thanks in advance :)Quote:
Originally Posted by FELIX
FELIX
Thanks, bro. Now it works fine :up:
...if some NHM owners can post somes screens of this beta (Read only version): CPU-Tweaker-beta1.zip
I need it before continuing writing...
Note that it's a new version wich support only NHM and K10 CPU (with integrated Memory Controller).
The interface is the same for both CPU, and I use WinRing0 driver now (unstead tvicport in memset).
I keep MemSet for chipsets with integrated memory controller (P35, P45...) and athlon64.
Thank for the report... :)
Thank you very much for your hard work :up: Straight boot, settings in cpuz = bios:
http://img.photobucket.com/albums/v2...Xbetatest1.jpg
=> loc.o: Could you send a registers dump at memset@hotmail.fr... thank.
thanks felix
i will do some testing today and send you a dump :up:
how do i make a dump with this CPU Tweaker software??Quote:
Originally Posted by FELIX
or do you mean CPUz :S
i'm just testing Gigabyte X58-UD5 with i920 at the moment
...if all the readings are correct, don't send any dump; otherwize, make it with cpu-z.
hi felix
both CPUz and memset are reporting the wrong CAS latency
i am just testing some corsairs which are set at CAS8 and it reports as CAS9 or CAS10
is it possible to fix that
Send. Lower multi gets more info right. If i can help let me know :up:
...a new beta:CPU-Tweaker-beta2.zip
-Read Cas# should be better.
-Fix Reading Memory size.
-Fix a XMP detection.
Great Work Hervé ;)
Just wanna thank you once again for your work on this absolutely wonderful program which I've been using instead of BIOS for quite a while now and newer versions coming along nicely.
Finnaly a tool for Nehalem? WOOOT...me goes tweaky, tweaky on my platform now :D
Felix,
Intel X38/48 possibly P45.
MCHBAR 0x23E,0x63E [4:0]
Common Performance Level Read Phase Advance Channel A, Channel B (Phase Pull in)
0x0000000000000000b = 0T phase advance
0x0000000000000001b = 1T phase advance, pull in phase 1
0x0000000000000011b = 3T phase advance, pull in phase 1 + 2
and so on.
From the divider with most active phases I could think of, 12:10.
Read Delay Phase adjust = +31T or pull in on all 5 phases. 0x0000000000011111b ( 0x1fh)
Read Delay Phase adjust = 0T / Neutral , no pull in on any phases. 0x00h
For 12:10 divider, 5 Phases / Channel. Phase 1 lowest bit, Phase 5 highest bit. 2 Phases would only set [1:0], 3 Phases would set [2:0]
0x249 PL = 8
FED14240 01001100 00052310 0E840800 00392200
0x649 PL = 8
FED14640 01001100 00252310 0E840800 00392200
Pull in 1,2,4,5 cha +27T Read Phase Delay Adjust
FED14230 00000000 00000000 00001300 001B7A89
Pull in 1,4,5 chb +25T Read Phase Delay Adjust
FED14630 00000000 00000000 00001300 00197A89
No pull in cha Neutral Read Phase Delay Adjust
FED14230 00000000 00000000 00001300 00007A89
No pull in chb Neutral Read Phase Delay Adjust
FED14630 00000000 00000000 00001300 00007A89
All pull in cha +31T read phase delay adjust
FED14230 00000000 00000000 00001300 001F7A89
all pull in chb +31T read phase delay adjust
FED14630 00000000 00000000 00001300 001F7A89
Dont know if this interests you but was just going through some mchbar dumps to figure out what values Asus AI bios settings change, and figured out this value! Each channel a/b (0x230/0x630) pair from same MCHBAR dump
0x510h[7:0], 0x910h[7:0] appear to hold Dimm 1 & 3 (A1 and B1) clock fine delay
FED14510 00009635
0x510h[15:8], 0x910h[15:8] appear to hold Dimm 2 & 4 (A2 and B2) clock fine delay
FED14910 00009434
0x511h[15:0] 0x911h[15:0] both hold another 2 delay values for a1,a2 and b1,b2 , and the following rows also hold what are possibly strobe related offset / adjustments.
which register holds the command rate value for an x38/48 mch?
Thank, all these registry values are interesting, but I don't know how I can add this settings in memset actually.
The only solution will be to change (and enlarge) the interface, but it's a hard job, and I have no time for now.Perhaps at next time...
a question: whats settings have the more impact on performance?
For command rate, it's not define:
On Asus motherboard, it's at FED140A0 bit 4
On Abit motherboard, it's at FED140C0 bit 17
felix
cas# reports properly now thanks
Gigabyte X58-UD5
just testing some more
its misreporting TRAS
set in bios 24
showing 26
also is it possible to change these subtimings. The app is not allowing me to set new changes............all the buttons are grayed out
...strange, cause tRAS is correctly reported on others motherboard.Perhaps a bios bug.
Is cpu-z report correctly the tRAS?
For timings change, coming soon with the finale release.
i will do some more testing and will report
aweseome tool herve!!! :toast:
...I have a full version ready for read and write, but never tested on NHM.
If someone is interesting to test it, send me a email address by PM.
@FELIX
YGPM.
Thanks,
;-)
You've got PM :D
just modded my board and sprayed plastic spray
will bench tomorrow and test this final version and report :up:
had to change dpi to 96 to test...but works fine on mine for main timings. changed values around. Each pic shows exactly what was set in bios for CL, tRCD, tRP, tRAS.
Other timings, tRRD set manually to 4 in bios (just make sure was at 4) says 6 in cpuz tweaker, constantly reads +2 too high. I set tRFC manually to 48 in bios cpu tweaker says 50, if set to 50 in bios it says 52. Round trip latency also reports +2 higher than what I set manually.
Of note if testing, have to set values manually b/c if at auto, just b/c auto normal value is listed to left, does not mean that is value you are at with auto. For example, tRFC on auto (value to left on x58 GB bios says 48) but cpu tweaker reads 62. Then I set manually on 48 and cpu tweaker reads 50. If set manually on 60, cpu tweaker says 62.
...have you tried to change one timing (tRAS for example) under win and checked that the change take effect with cpuz?
I fear that it is not working (registers locked in write)
Nope, I just tested if it reads correctly from what is set in bios.Quote:
Originally Posted by FELIX
I just tried making changes in windows with it, it does not work. Changing tRAS, tRCD, or tRP with cpu-tweaker does not change the value in cpuz.
...OK, PCI registers are locked. :(
I just completely terminated the software, and I learn that it don't work: too bad.
I'll speak about it with Franck, and eventually send an email at Intel, but not a lot of chance to succeed...
The link (if others users want to test it):
http://www.tweakers.fr/download/CPU-Tweaker.zip
But probably don't work.
oh :banana::banana::banana::banana: :(
looks like we are stuck with long arse bios RAM tweaking
yeah i also got +2 on Tras when i set it to 24 in bios
Felix,
Are the I7 timings held in the CPU MSR's?
-> rge: trrd,trfc and round trip latency reading fixed in this version: CPU-Tweaker.zip
-> dinos22: probably a bios bug: tRAS is correctly reading on others motherboards.
-> mikeyakame: no, timings held in the PCI configuration space, like K10.
seems tras is a weird bug
and confirmed
cant change timings with latest version
:(
Felix,
One thing we know is, OE Software like Asus TurboV and Gigabytes OC software both allow memory timings to be changed on the fly, so it's just a matter of figuring out the means they use through software and take a similar path right?
Hmm, possibly the difference in tRAS between bios and PCI register value may be due to an arbitrary minimum turnaround before an ACT command can be issued, and bios has been coded to account for this but not actually display it because it's a preamble thats default. Just throwing ideas around.
...right, perhaps registers are simply locked by a bit somewhere in the PCI space.
But you sure that these soft allow to change timings in the fly on Core i7?
Quote:
Originally Posted by DMF
Yes, that fixed it. But the FSB is still reported a little low (e.g. 421 v. 432).Quote:
Originally Posted by FELIX
Thanks!
Felix, two things... 1) Please rename your cpu-tweaker for i7... I vote for i7-Tweaker, and leave your Cpu-Tweaker same for all others. That way I not mix them up and execute the wrong one, as I just did!
I look in this thread for the < i7 tweaker and monitor this thread for your updates to the non i7 version.
...Why do you want that I rename it? CPU-Tweaker work on both CPU Core i7 and Phenom. Memset work on others.
MemSet 3.6
-Fix a bug with EPP abreviated profile detection.
-Add support for Intel Q45/G41 chipsets.
-Add support for Intel G35 chipsets.
-Add support for Intel PM45/GM45 (Mobile) chipsets.
-Add support for NVidia NForce 630i & 790i FTW chipsets.
-Fix a bug with the Save function on Intel chipsets.
-Improve reading frequency with some Intel CPU.
-K10 support has been removed in this version (Use CPU-Tweaker now).
CPU-Tweaker 1.0 beta4
Only for Processor with Integrated Memory Controller:
-AMD Phenom DDR2 & DDR3.
-INTEL Core i7 DDR3. (Timings and frequency Reading only)
http://img134.imageshack.us/img134/6...ymenii2xb8.jpgQuote:
Originally Posted by FELIX
merci!
Great work Felix, especially the CPU Tweaker is a very handy tool, now I can test RAM on nehalem with more ease. Everything going ok untill now.
I don't think you paid enough attention to Felix's post mate.Quote:
Originally Posted by Monstru
The CPU Tweaker CAN'T change the memory timings on the LGA1366 platform yet.
I didn't had time to test before I post this, bad luck :(
Felix
Just curious in which manner you are using to write the pci registers?
I think I read that you are using a ring0 driver, so if thats the case you are attempting to write the NHM pci registers while at priv level 0.
Ie. transitition from priv 3 to 0 and then back to 3 by SYSENTER/SYSEXIT instructions right? The pci registers are definitely RW flagged not RWO. If you are using WRMSR to mov the ESP, EIP, CS data to their corresponding msr offset address, then making a SYSCALL or SYSENTER, and then executing the instructions pointed to by IA32_SYSENTER_EIP msr you wrote before making the call.
If that is along the lines of the method you are using and its not working, I'm wondering if it is possible to switch to real-address mode without causing a GP exception and manually set the registers bits if its possible to use the pci offset:address in real-address mode that is. If the PCIBAR isn't locked which it shouldn't be since it's used for counters and such too, and the bios can change its values I'm thinking it may not be that it can't be done, but rather the precursors for doing it. I've read briefly through the I7 datasheets and from what I understand that there are rules setup for access control to certain address ranges and registers. If you hadn't come across this it, my understanding is on different bus interconnects there are different access rights for say pcie, qpi, dmi, smbus, etc based calls depending on what the devices on that end need priviledge to do. If the origin of the call is say QPI bus, then there are rules setup to restrict access when reading and or writing certain hw address registers or memory offset locations.
I may be understanding that wrong, but if i'm not then a theory I have is if this was true, what if a roundabout method was used to write rule restricted registers by forwarding the call as such through a bus that matches the access control to write that register, since it checks source flag to match access it might be another means which the bios does it, since Intel would have let all the bios engineers know exactly how to write the registers if protected in such a way that opening them up for write access could mean that if you write one RW reg it may be possible to change any that arent RWO or RO. This just came to mind, and thought it was worth sharing. If I come up with anything more that's worth mentioning I'll pass it over.
Intel engineers would have put in place more than 1 method of writing pci registers since we know the bios can do it and the rules for the bios doing it should be no different than your app doing it, just a matter of exposing the means if its not documented.
why is there no performance level changer for pm45 ? :confused:
:shrug:
why is there no performance level changer for pm45 ?
:shakes:
Why can't I change tCL on my Asus P5Q-E????
I can change all other values, but not the CAS Latency?? what's wrong there??
It's been said a few times already.Quote:
Originally Posted by GrossmeisterB
Chipset limitation.
if you mean memory tweaker can not change it, you are not alone...in order to make a change to CAS, the puter normally has to shutdown to effect the change or at least have a restart after making the change from the bios.Quote:
Originally Posted by GrossmeisterB
Felix,
the Intel P45 chipset's stepping report on Memset version 3.6 is seems to be wrong on one motherboard model at least.
2 of my Gigabyte EP45-UD3R's... in Memset 3.5.8 and CPU-Z, Everest, the chipset stepping is reported as an A3 step.
and starting from Memset 3.5.9 (and 3.6 final) the program reports as an A2 step (CPU-Z, Everest still reading and reporting as A3 step)
i'm just curious and wondering if you can check and advise me on this.
-> mikeyakame: simply registers are locked by a bit (probably RWO) on Core i7, comfirmed by Franck.
-> vld: I don't know where is localized Performance level registers on mobile chipsets. I can't do nothing.
-> pangingIII: as you can see in this datasheet at page 8, P45 stepping is A2, but I can make a mistake.
Currently have 3.4 installed, which has been working fine.
I installed 3.6, and it opens with "mchbar" in locked position, and I have found no way to unlock it, meaning I can't adjust any of the settings or expand to see both modules.
I'm ok with 3.4, but am curious if anyone has idea(s) about why this is happening.
Well then there is like no use for memset ;) Please try your best to find out where the performance level registers are on the p45 mobile chipset. If you need any help ask me and I can provide some info.Quote:
Originally Posted by FELIX
on rampage 2 extreme (x58) i cant change any values in cpu-tweaker. whats up with that? it wont let me apply or save.
Read the previous page m8.Quote:
Originally Posted by fitseries3
It's just 10 posts away from you.
Currently FELIX doesn't have the necessary resources to make it work ( can't write new values ) on the i7 platform.
It's in read-only mode for the time being.
Felix.
On I7 check PCI Bus DID 0x2C01h offset 0x4Ch. Register SAD_SMRAM[12] = 1, SAD_SMRAM[14] = 0. SAD_SMRAM[12] should be RO if set to 1, SAD_SMRAM[14] should be RO if set to 0.
I already read this passage from the doc,
but I don't know what it means SMM (in the docs) and if it addresses a memory space or PCI bus. :confused:
New memset version: MemSet 4.0 beta 1
-Use WinRing0 driver instead TVicPort.
-Interface is the same for all chipsets/CPUs.
-Add support for Intel Core i7 CPU (Reading only).
-Loading time was improved.
Thanks, well done :up:
I have one problem with the new MemSet 4.0 beta1 and that is it shows my memory as DDR3 0.0 MHz. Tell me that I'm not the only one having this problem.
Attachment 91225
It also disagrees with CPU Tweaker on some of the settings.
http://img392.imageshack.us/img392/6...setbetaor7.jpg
ol norton,
looks like felix has subtracted the 2T extra that cpu tweaker is reading that the bios doesn't.
felix,
pretty sure its pci as i remember it saying you address SAD by device id on pci bus, addressing devices 4-6 for memory channels would be the same method no?
Super impressed with the speed at which this is moving along. Thanks for the work.Quote:
Originally Posted by FELIX