How to set up GTL Ref Values for 45nm & 65nm

[QUOTE=vox;3363500]

Quote:

---

Originally Posted by mikeyakame

Hello mike!

So can we say that there is a relation bettewen the PCIE Frequency and the
FSB Strap To North Bridge???

ie: fsb to nb = 431 so pcie freq= 112
or fsb to nb= 466 so pcie freq=101????

if so how do we calculate it for varios values?

tks
vox

---

there is no way to calculate those kind of values. i used 112mhz for pci-e at 431 because it was the only frequency that in hd tune pro didn't appear to have erratic spikes in hard drive read speeds or access, also my gpu didnt magically drop the display out of nowhere while my system was idle.

avoid changing pci-e if you can unless you can say for certain the rest of the system is stable. at least if anomalies appear its a matter of making minor adjustments to the southbridge core voltage or sb pll voltage, if you do change sb pll voltage, change the cpu pll voltage by the same amount more to maintain the gap mainboard engineers design into the system to isolate each pll from the other and vice versa.

changing the pci-e freq more than 5mhz can wreak havoc if devices on the pci-e or southbridge don't tolerate more than a few mhz deviation from the 100mhz base clock. some hard drives will drop off the bus randomly or corrupt data if their controllers design can't work with more than 104-105mhz.

[QUOTE=mikeyakame;3363539]

Quote:

---

Originally Posted by vox

there is no way to calculate those kind of values. i used 112mhz for pci-e at 431 because it was the only frequency that in hd tune pro didn't appear to have erratic spikes in hard drive read speeds or access, also my gpu didnt magically drop the display out of nowhere while my system was idle.

avoid changing pci-e if you can unless you can say for certain the rest of the system is stable. at least if anomalies appear its a matter of making minor adjustments to the southbridge core voltage or sb pll voltage, if you do change sb pll voltage, change the cpu pll voltage by the same amount more to maintain the gap mainboard engineers design into the system to isolate each pll from the other and vice versa.

changing the pci-e freq more than 5mhz can wreak havoc if devices on the pci-e or southbridge don't tolerate more than a few mhz deviation from the 100mhz base clock. some hard drives will drop off the bus randomly or corrupt data if their controllers design can't work with more than 104-105mhz.

---

for a Q9550 and a P5Q3 Dlx is there a range like 100-105 or 100-113?

i dont have sb pll vol only cpu pll, his there a value that corresponds to it?

my specs:

Overclocker Tuner: Manual
CPU Ratio Setting: 8.5
FSB Frequency: 495
PCIE Frequency: 100 (i think this is the only value to go higher as it is! 102 blocks)
FSB Strap To North Bridge: 333
DRAM Frequency: ddr3-1585mhz the 2ª highest
DRAM CLK Skew on Channel A1: Auto
DRAM CLK Skew on Channel A2: Auto
DRAM CLK Skew on Channel B1: Auto
DRAM CLK Skew on Channel B2: Auto
DRAM Timing Control: Manual

CAS Latency: 7
DRAM RAS to CAS Delay: 7
DRAM RAS Precharge: 7
DRAM RAS Activate to Precharge: 18
RAS TO RAS Delay: Auto
Row Refresh Cycle Time: AUTO
Write Recovery Time: Auto
Read To Precharge Time: Auto
DRAM Static Read Control: Disabled
DRAM Dynamic Write Control: Disabled
DRAM Read Training: Disabled
DRAM Write Training: Disabled
MEM OC Charger: ENABLE
Ai Clock Twister: auto
AI Transaction Booster: AUTO

CPU Voltage: 1.42
CPU GTL Voltage Reference (0/2): Auto
CPU GTL Voltage Reference (1/3): Auto
CPU PLL Voltage: 1.70
FSB Termination Voltage: 1.6
DRAM Voltage: 2..5
NB Voltage: 1.4
NB GTL Voltage: Auto
SB Voltage: auto
PCIE SATA Voltage: auto
Load-Line Calibration: Enabled
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
CPU Clock Skew: AUTO
NB Clock Skew: AUTO

tks
vox

I have changed some values in my bios, and looked into this some. Am i right if i count like this:

GTL (0/1) 0.675 x vTT (1.24) = 0.837 GTL ref. Is that right?

And if it is right, i have two of those GTL:s, i suppose they are for both of the cores. But the first one has standard value of 0.63, and the other has 0.67. How come?

And also, how can i determine what GTL ref to use? I have no idea really.

Sorry for my bad english, hope u understood though..

My setup: Asus P5Q-E, E8400 and Kingston HyperX PC8500. Right now fsb 500 (1:1).

In prime95 i get rounding error after 1.5h, 0.5 expected less than 0.4. So what do u suggest i would change in my bios? The NBv is right, so is the Vcore and my memory. Could it be the GTL:s, or i have too low vtt? i have it at 1.28 now

Quote:

---

Originally Posted by clappen

mike if u could help me plz..

I have changed some values in my bios, and looked into this some. Am i right if i count like this:

GTL (0/1) 0.675 x vTT (1.24) = 0.837 GTL ref. Is that right?

And if it is right, i have two of those GTL:s, i suppose they are for both of the cores. But the first one has standard value of 0.63, and the other has 0.67. How come?

And also, how can i determine what GTL ref to use? I have no idea really.

Sorry for my bad english, hope u understood though..

My setup: Asus P5Q-E, E8400 and Kingston HyperX PC8500. Right now fsb 533 (1:1), stable for 2 hours but no more.

---

gtl 0 is for the address clock strobe input reference voltage for die 0
gtl 1 is for the data clock strobe input reference voltage for die 0

a quad core has gtl 2 and gtl 3, which are die 1 reference inputs for address and data strobes respectively.

I personally don't know why Asus offset the two values. I have a few alternate ideas for the reason behind it, but just guesses if anything.

address strobe occurs on low clock, while data strobe occurs on high clock.

i dont know how right this theory is so don't take it as more than a stab in the dark at an explanation that just crossed my mind that made a bit of sense as to why.

lower gtlref for 0 increases ringback margin on the supply voltage for the address strobe, moving the logical 0 clock valid window lower. higher gtlref for 1 increases ringback margin on the supply voltage for the data strobe, moving the logical 1 clock valid window higher. if you overlaid both waves on top of each other then the input reference voltage for each would be more tolerable to ringback on the line as the fsb frequency is adjusted outside the tuned band of frequencies, so that the common denominator of overclockers (people who change settings according to what others use) without an extensive knowledge of electronics design have more freedom to increase clocks without risking data integrity or having to figure out what the hell a gtl ref voltage is and how exactly to change it.!

those values are probably safest for most, if you increase gtlref 1 you would most likely need to increase gtlref 0 a smaller amount since ringback is usually never as bad on the low clock since the input voltages are between 0 and (gtlref - crossing threshold), where as the high clock ringback is much greater since the voltages are between (gtlref + crossing threshold) and vtt.

vox.

im pretty sure pcie sata voltage is the same as sb pll voltage, but would need to read over the p45 chipset datasheets to tell u for certain. being a mainstream chipset intel might have gone a more cost effective means and gone about this a little differently. personaly id stick to 100-104 and 110-114....my reasoning is somewhat basic. Nvidia uses a 27mhz pll reference on the g80 and newer cards (108mhz base clock is used to obtain the shader clock by 1:2 divider, and memory clock with 1:1 divider), on top of this the gt200 series cards switches the pll reference to the pci-e bus when downclocking to generate the core, shader and memory clocks (which use a 100mhz base clock) in 2d mode for power saving. if you own an nvidia gpu then its probably wise to avoid between 105-109mhz theres more chance of cross talking between gpu bus and pci-e bus when the pll source is switched back and forth. I don't know much on the pll reference ATI uses so I can't help there.

Quote:

---

Originally Posted by mikeyakame

gtl 0 is for the address clock strobe input reference voltage for die 0
gtl 1 is for the data clock strobe input reference voltage for die 0

a quad core has gtl 2 and gtl 3, which are die 1 reference inputs for address and data strobes respectively.

I personally don't know why Asus offset the two values. I have a few alternate ideas for the reason behind it, but just guesses if anything.

address strobe occurs on low clock, while data strobe occurs on high clock.

i dont know how right this theory is so don't take it as more than a stab in the dark at an explanation that just crossed my mind that made a bit of sense as to why.

lower gtlref for 0 increases ringback margin on the supply voltage for the address strobe, moving the logical 0 clock valid window lower. higher gtlref for 1 increases ringback margin on the supply voltage for the data strobe, moving the logical 1 clock valid window higher. if you overlaid both waves on top of each other then the input reference voltage for each would be more tolerable to ringback on the line as the fsb frequency is adjusted outside the tuned band of frequencies, so that the common denominator of overclockers (people who change settings according to what others use) without an extensive knowledge of electronics design have more freedom to increase clocks without risking data integrity or having to figure out what the hell a gtl ref voltage is and how exactly to change it.!

those values are probably safest for most, if you increase gtlref 1 you would most likely need to increase gtlref 0 a smaller amount since ringback is usually never as bad on the low clock since the input voltages are between 0 and (gtlref - crossing threshold), where as the high clock ringback is much greater since the voltages are between (gtlref + crossing threshold) and vtt.

---

allright! Lets say i get rounding errors in prime95 after 2h, i know my vcore is allright, so is my NBv. My gtl refs are at standard value (0.63 and 0.67), and vTT is 1.28. (gtl @ NB is auto).

But if i change the cpu gtl:s to auto, would that make any sense and get the system stable? Or should i increase/decrease those manually? If i have higher vTT, does that mean i will use lower gtl:s?

sorry for beeing noob, but i just want to learn!

Quote:

---

Originally Posted by mikeyakame

vox.

im pretty sure pcie sata voltage is the same as sb pll voltage, but would need to read over the p45 chipset datasheets to tell u for certain. being a mainstream chipset intel might have gone a more cost effective means and gone about this a little differently. personaly id stick to 100-104 and 110-114....my reasoning is somewhat basic. Nvidia uses a 27mhz pll reference on the g80 and newer cards (108mhz base clock is used to obtain the shader clock by 1:2 divider, and memory clock with 1:1 divider), on top of this the gt200 series cards switches the pll reference to the pci-e bus when downclocking to generate the core, shader and memory clocks (which use a 100mhz base clock) in 2d mode for power saving. if you own an nvidia gpu then its probably wise to avoid between 105-109mhz theres more chance of cross talking between gpu bus and pci-e bus when the pll source is switched back and forth. I don't know much on the pll reference ATI uses so I can't help there.

---

I have a HD 4870 1GB DDR5 what would be the "best" ranges for my GPU?

tks
vox

Quote:

---

Originally Posted by clappen

allright! Lets say i get rounding errors in prime95 after 2h, i know my vcore is allright, so is my NBv. My gtl refs are at standard value (0.63 and 0.67), and vTT is 1.28. (gtl @ NB is auto).

But if i change the cpu gtl:s to auto, would that make any sense and get the system stable? Or should i increase/decrease those manually? If i have higher vTT, does that mean i will use lower gtl:s?

sorry for beeing noob, but i just want to learn!

---

you could try auto it may or may not work. i've spent some time analyzing the auto values on my board and know this much at least on the Rampage Formula. If you say set vCore manually and leave vCPU_PLL on auto, it selects a default value and doesnt correct any further adjustments I make to vCore. it uses the one voltage for any value so it might just be that for auto to work properly the other settings it uses to calculate adjustments probably need to be set to auto too so it can make corrective adjustment based on the programmed tables.

if after 2 hours prime fails, you probably want to raise vtt one step first, then subract 10mv at a time first from gtlref1, then another 10mv on gtlref1, then 10mv off gtlref0, then try -10mv on gtlref1 and 0, if still no luck add 10mv to gtlref 1, and next time add another 10mv...just try different values while making small adjustments each time if you need to.

you wont get it right straight away, but with time and trial and error you'll develop a knack for doing it pretty quickly. it's not something anybody can explain and even maths only provides theoretical values of what it should be. there is a baseline to work to, and the more different combinations of settings you succeed in taming the easier it becomes to makes educated guesses at where to start on your system.

Quote:

---

Originally Posted by vox

I have a HD 4870 1GB DDR5 what would be the "best" ranges for my GPU?

tks
vox

---

find out for me what frequency ati's common pll oscillates the reference clock for the core and memory base clocks at and then I can steer you the right way. i don't have any ati cards at home to get that value for you.

whew what a thread ! exellent info in here!

Quote:

---

Originally Posted by mikeyakame

vox.

im pretty sure pcie sata voltage is the same as sb pll voltage, but would need to read over the p45 chipset datasheets to tell u for certain. being a mainstream chipset intel might have gone a more cost effective means and gone about this a little differently. personaly id stick to 100-104 and 110-114....my reasoning is somewhat basic. Nvidia uses a 27mhz pll reference on the g80 and newer cards (108mhz base clock is used to obtain the shader clock by 1:2 divider, and memory clock with 1:1 divider), on top of this the gt200 series cards switches the pll reference to the pci-e bus when downclocking to generate the core, shader and memory clocks (which use a 100mhz base clock) in 2d mode for power saving. if you own an nvidia gpu then its probably wise to avoid between 105-109mhz theres more chance of cross talking between gpu bus and pci-e bus when the pll source is switched back and forth. I don't know much on the pll reference ATI uses so I can't help there.

---

For the newer Ati 48xx cards it's 25MHz, i think. Why? Because when overclocking the card, GPU and RAM speeds seem to be at their best when they're dividable by 25. The ram will automatically scale to the nearest multiple of 25 when setting the ram speed higher than 1000MHz (example: 1130 -> 1125 or 1140 -> 1150)

This topic seems to support my asumption:
http://64.233.183.104/search?q=cache...lnk&cd=1&gl=nl

Quote:

---

Originally Posted by mikeyakame

find out for me what frequency ati's common pll oscillates the reference clock for the core and memory base clocks at and then I can steer you the right way. i don't have any ati cards at home to get that value for you.

---

do you know if GPU-Z gives that info?

can this link help? http://ati.amd.com/products/radeonhd4800/specs.html

heads up!
ax = bx + y, where a = 0.667, b = 0.635, x = Vtt
y = ax - bx = x(a-b) = x(0.667-0.635) = .32x
y = 0.32 x Vtt

Quote:

---

Originally Posted by m0da

heads up!
ax = bx + y, where a = 0.667, b = 0.635, x = Vtt
y = ax - bx = x(a-b) = x(0.667-0.635) = .32x
y = 0.32 x Vtt

---

just doing my bit for m0da's nice formula :)



heads up! (for 65nm CPU)

ax = bx + y, where a = 0.667, b = 0.635, x = vTT

y = ax - bx

y = x(a-b) = x(0.667-0.635) = 0.032x

y = 0.032 (vTT)

or

y = vTT multiplied by 0.032



heads down! (for 45nm CPU)

ax = bx - y, where a = 0.667, b = 0.635, x = vTT

ax + y = bx

y = x(b-a) = x(0.635-0.667) = -0.032x

y = -0.032 (vTT)

or

y = vTT multiplied by -0.032

I haven't read all of the explanations I asked for but, I seen you guys responded and wanted to thank you. I will read it all in a little bit, busy day. Vox if you are running those setting , I think you are going to ruin your chip man.

Wish somebody would create a little app where you can input the numbers and it does the equation for us :D

Good idea^^

Quote:

---

Originally Posted by zodden

Wish somebody would create a little app where you can input the numbers and it does the equation for us :D

---

that can be done :P

Someone give me some example correct values and I can make a quicky console program to give you the mV rating.

The program just needs to know VTT and the fab Process of your CPU right? So you input your VTT, for example mine would be 1.25, and the fab process would be 45nm. So using that formula up there I would need -40mV right?

0) 0.635
1) 0.667
2) 0.635
3) 0.667

Thats the values in order on my mobo (Maximus Formula II) so I need to set 1 and 3 to -40mV right?

Quote:

---

Originally Posted by moogle

that can be done :P

Someone give me some example correct values and I can make a quicky console program to give you the mV rating.

The program just needs to know VTT and the fab Process of your CPU right? So you input your VTT, for example mine would be 1.25, and the fab process would be 45nm. So using that formula up there I would need -40mV right?

0) 0.635
1) 0.667
2) 0.635
3) 0.667

Thats the values in order on my mobo (Maximus Formula II) so I need to set 1 and 3 to -40mV right?

---

Correct, thats how I have mine set up as well.


Something interesting btw;

I had my Q9650 @ 4GHZ (9x450) with 1.28750 vcore, I had FSBTV-1.12v, NB-1.12v, PLL-1.51, LLC enabled and all other volts on one notch up from there lowest values. It was prime/linpack stable but I couldn't lower the vcore 2 notches below this setting or it would start to become flakey. CPU GTL's were 0 auto, 1 -40, 2 auto, 3 -40.

After reading here I decided to try something. Mobo MF2

I raised my FSBTV to 1.29v (which is now above my vcore) and I raised NB to 1.2v, I left the CPU GTL's as they were and left all other volts as they were as well...................then I droped my vcore down to 1.2500v (which is about 6/7 notches down) and the system is rock solid prime/linpack stable.

I'm useless at math and remembering tech terminology but with the first settings I think things fell below the .80 - 1.0 volt margin and were around the mid .7 setting.

After changing values the margin moved up over the .8 barrier and therefore enabled me to lower vcore for some reason. Probably an incorrect assumption as to why I could lower vcore by so much but perhaps there is some validity to it as well. :shrug:

Quote:

---

Originally Posted by lowdog

Correct, thats how I have mine set up as well.

---

:banana::banana::banana::banana: I've done the exact opposite to get my stable overclock :rofl:

Maybe I can decrease my vCore tonight.

Quote:

---

Originally Posted by moogle

Someone give me some example correct values and I can make a quicky console program to give you the mV rating.

---

Quote:

---

Originally Posted by lowdog

I think things fell below the .80 - 1.0 volt margin and were around the mid .7 setting.

After changing values the margin moved up over the .8 barrier

---

I think lowdog's example shows why Cryptik's original formula in Post 1 could be more useful than a simply generating a 'y' value in mV.

In the 'long' version, multiplying 'a' and 'b' values individually by vTT, before subtracting one from another gives the resultant vREFs first :)

I've been slowly working my voltages up trying to get stable at 430x9 FSB. Been going slowly because my wife would not be happy if I had to replace the CPU :shocked:. But I finally just gave my SB/CPU PLL a jump, gave my VTT a HUGE jump (about 10 of the fine settings on this MB), pushed my CPU GTLs up to almost 800 mv -- and I'm stable! Then, just for the heck of it (since I'm on air and don't expect to get it stable), I pushed VTT and the SB/CPU PLL up some more, put the CPU GTLs a little above 800 mv and got windows to boot at 4GHz! (442x9). :cool: Now to see if I can get it stable without adding too much more VID.

I wanna clear up something... I've heard several people say over 1,36v vtt can and will damage a 45nm CPU but reading through this thread I see people use much more and advising to put vtt higher than Vcore.
So the big question that is bugging me is.... what is a safe max vor vtt?

1.36v definitely won't scratch a 45nm cpu. but there is generally no need to set vtt (actual reported value) 0.05v higher than vcc unless vcc is below 1.20v. extra vtt voltage just helps to get around certain fsb frequencies and makes gtl reference multiplier more flexible. I believe that at vcc values of more than 1.40v a vtt that is slightly higher offers voltage overshoot protection and some noise immunity but this is just based on my understanding of how its implemented from reading through lots of intel datasheets. Safely for every day on a 45nm chip as long as you stay below 1.50v vtt there won't be any kind of chip dying happening anywhere in the near future. A vcc of 1.50v and higher will wear the chip out at a higher rate if average temps are too high in general. You could probably use 1.60v vcc and 1.65v vtt all day long if you can keep the cpu temps low enough under full load ( id take a guess and say < 40c full load )

Quote:

---

Originally Posted by cheapseats

I think lowdog's example shows why Cryptik's original formula in Post 1 could be more useful than a simply generating a 'y' value in mV.

In the 'long' version, multiplying 'a' and 'b' values individually by vTT, before subtracting one from another gives the resultant vREFs first :)

---

Yes, that's one of the reasons why I chose to do the formula that way. You can see what Vref's you are getting, and then what you have to set to change them to the desired level.

It seems everyone comes at this from a different angle so just use whatever way works for you.

It seems my e8400 likes lower Vrefs, around 0.74v. If I raise the Vtt, I must lower the Vref to keep it stable, just raising Vtt and leaving the GTL's alone causes instability. Just supports the 'whatever works for your CPU' statements - try all combinations don't just raise Vref.