can not change cas latency with 965GM chipset felix
it wont even let you select anything, the drop down works but if you click on 4 or 5 or 6 or 3 it doesnt change it stays at cas5.
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can not change cas latency with 965GM chipset felix
it wont even let you select anything, the drop down works but if you click on 4 or 5 or 6 or 3 it doesnt change it stays at cas5.
you cannot change the cas latency using memset (mentioned a few times in this thread :p: )
ya used to be able toQuote:
Originally Posted by Pyr0
oh well
cpu-z may have registered a change in cas, but there was no performance benefits, meaning the change did not actually work
Please add a support for VIA KM400/400A VenID/DevID 1106/3205
If change all 06118931 to 06110532 - it all works perfectly.
Thanks FELIX! Everything works fine by the first look. Here are my results with a pair of PQI ram modules:Quote:
Originally Posted by FELIX
http://img402.imageshack.us/img402/5...msetom0.th.png
Will there be more timings to tweak in the further versions or 965 mobile chipsets are only limited to this ones? I would like to play with tRC a bit. :)
Hope you can get the Skulltrail update done soon ;)
->compiller: VIA don't provide any datasheet for their chipsets, so impossible to
add support .
->FUGGER: it's a server chipset, without most important timings (CL, tRCD, tRP and tRAS are not documented)
I'll try to update in 3.5 version.
Here is what I can see now, the version you emailed works.
Felix,
Thank you for your great MemSet. I have just migrated from Athlon64 X2 3800+ @2.6Ghz to Q6600, currently running 3.0GHz (333x9 / 333 strap) (on retail stock cooler), so excuse me for a newbee question...
... I set Command Rate to 1T in BIOS (Asus P5K vanilla). CPU-Z 1.43 shows Command Rate 2T ?! Now the interesting thing : I launch MemSet, within 2 secs CPU-Z shows Command Rate 1T !!! I exit MemSet, CPU-Z shows 2T again :confused:
To your knowledge, is this a CPU-Z bug ?
Thanks again,
Dominique
P5K v1.02G
Q6600 G0 @ 333x9 on stock air / 1.375v BIOS / 1.33v Idle / 1.27-1.23v Load
OCZ Reaper 6400 @ DDR800 4-4-4-15 1T (???)
7600GS /512 Silent + 7600GS /256 Silent
Antec Sonata III w/ Earthwatt 500W
Does 3.5 Beta work on Abit IX38 QuadGT ?
It should buddy... why dont give it a try and then feedback!!
@FELIX : not working on ABIT IX 38 QUAD GT with Memset 3.5beta
and what is the problem?
I cant use memset 3.5beta.... like crash on memset, only work double click shortcut and exit on tab in memset..:)
It's like it only shows timings, you cann't do anything else, nothing is clickable or sth.Quote:
Originally Posted by Hazzan
That's my problem on Vista x64, displays and that's it with 35beta.
Oh and put a link on your website to get/try the beta's.
Ty
...when Apply and Save button isn't show, it's cause the MCHBAR is locked in Write.
You can check it by: Open WPCRedit on PCIBus :0 Device:0 Function:0 and look at
OffSet F4, bit[0] :if it's at 1, MCHBAR have been locked in write by the bios.
And unfortunately, it's a "read only" bit, You can't write 0 in this bit.
Abit ip35pro latest beta bios. It doesn't work as usual
Felix is there ne way to open the F4 bit its set to read only on the ix38 quadgtQuote:
Originally Posted by FELIX
Shows up as MCHBAR locked in memset 3.5beta
Nice find, works well.
:) works really great on my abit nf-7s whit a-data vitesta pc4000.
I'm testing beta for now it's stable for me. next week i'll get new memory and mobo we will see :)
Good job Felix
I can run 3.4 fine, but 3.5 says "unable to execute file in temporary directory" Error 5 Access Denied" when I click on the downloaded file. Any ideas why?
I moved it to an empty folder and then it ran the setup.
Felix here's MemSet 3.5 beta on my EVGA 780i. Has it been updated for the 780i chipset or is it normal to see NVIDIA NForce 680i SLI?
Attachment 72820
->xgman: no idea, perhaps cause the executable file is not in a good folder... :confused:
->msgclb: I know this "problem", cause 680 and 780 have the same device ID, Same thing with X38 and X48:
I need to find an other way for identified these chipsets...
I have an Asus Commando + Windows XP64bit and the performance level setting doesn't seem to work! Default is 12, I set it to 6 and it doesn't make any difference in Everest Latency or Memory Read benchmark. Still stuck at ~8900MB and 59.3ns.
Any ideas? Running 490FSB 1:1 with 4x1GB sticks 4-4-4-15 timings.
Performance Level/Read Delay work with some P965 chipsets, but not all, and I don't know why. :confused:
Felix, are you trying to get Performance Level/Read Delay to work on P965 boards?
This is probly nothing, but noticed last night memset is reading mem speed differently to what it is. I don't notice this on XP, only on vista.
Minor error there.
Problem has been there for some time. But who cares :D
Hello,
I have a problem/question:
I am trying to tweak my memory timings, but I am not sure I understand why different text terms/labels are used in SPD section vs. the main section? It makes it hard to know which #s to tweak because for example Row to Row delay exist on SPD side but not in main window. Er, Im sure it exist but which one is it??
http://img299.imageshack.us/img299/7...8135552ye1.png
I am on a e6850, gigabyte p35 btw. vista 32.
It's cause I use name peculiar to each datasheet, so in spd documentation, is Row to Row Delay,
and in Intel doc. is Activate to Activate Delay;
-Write to Precharge delay = Cas# + 3 + Write Recovery time(spd)
-Write to Read (main) = Cas# + 3 + Write to Read(spd)
-Refresh Period (main) in clock = Refresh Rate(spd) in µs
->necron66: if you find a difference in memset reading frequency between cpu-z, cpu-z is right.
The best for know multiplier is to make a RDMSR, but my driver don't provide it.
Read what I said "its prolly nothing", and like I said I didn't notice it on XP, only since I use Vista, which is from hmmmm, the day I made that post.....Quote:
Originally Posted by Nosfer@tu
No worries mate :up:Quote:
Originally Posted by FELIX
felix, i'm currently looking into squeezing out my memory and found it interesting that on my ab9quadgt (p965) i get two different performance levels on the two dimms! for one dimm memset 3.5 beta reads 9 for the other it reads 10!Quote:
Originally Posted by FELIX
the only program i could get hold of by now, which allows me to check this settings is memtest. i modified the code to read all required timings off the mch!
anyway, as it's not clear to me from looking into the data sheet where to find some timings i ask you if you can help me here.
i'm looking for the following timings for the p965 chipset:
tPALL_RP (All Precharge to Activate): 252h [9:12]
Performance Level: 250h [2:5]
tWR (Write to Precharge Delay): 250h [6:10]
tRTP (Read to Precharge Delay): ???????
All Precharge to Refresh Delay: 25Bh [9:12]
Command Rate: ???????
this are the registers and bitpositions i used. could you pls check your code or documents to verify if my locations are correct?
thanks
tRTP (Read to Precharge Delay): 250h [5:2]
Performance Level: 248h [12-8]
Others is good.
For command rate, it's motherboard manufacturer dependent.
New beta version: MemSet35beta.exe
-Add support for NVidia NForce 650 Ultra & NForce 790 chipsets.
-Add some higher timings values for 965/P35/X38 chipsets.
Eventually, report me bugs... :)
eye am running 1T command rate & 3.5 beta says 2T
the last memset eye had 3.4 reported it correctly fyi
again thanks for the great tool FELIX !
Quote:
Originally Posted by FELIX
Is the Performance Level, register 248h, in any Intel documentation?
I've checked several and find no mention of register 248h....
Is there a dos version of a similar program?
FELIX - I'm trying to "translate" SPD, BIOS, and MemSet readings on a P35 as well. I fully understand why the terminology is used in MemSet and just wanted to make sure I understand a couple of items:Quote:
Originally Posted by LuckMan212I am trying to tweak my memory timings, but I am not sure I understand why different text terms/labels are used...
Quote:
Originally Posted by FELIX
Sorry if this is remedial or obvious, just like to be sure.
-Write to Precharge delay = tCL + 3 + tWR
-Write to Read Delayed = tCL + 3 + tWTR
Would that be accurate?
You mentioned (spd), but if tWR and tWTR is able to be set in BIOS that is still used instead of spd, correct?
MemSet
RAS# to CAS# Read Delay
RAS# to CAS# Write Delay
Both of these can typically be from a "RAS# to CAS# Delay (tRCD)" setting?
MemSet
Read to Write Delay (tRD_WR)
This is also referred to as tWR?
And tRC is not used at all as P35 MCH doesn't have or use it, correct?
Nice find :up:
No.Quote:
Originally Posted by JWilson
No.Quote:
Originally Posted by Spyrus
real equation is:Quote:
Originally Posted by Signal64
*Write to Precharge delay = WRITE Cas# Latency + (Burst Lengh / 2) + tWR
-Write# Cas Latency= Read Cas# Latency(tCL) - 1;
-Burst Lenght: Practicaly always = 8;
so:Write to Precharge delay = tCL - 1 + (8 / 2) + tWR = tCL + 3 + tWR
*Same for tWTR
these equation are indicate in Intel datasheet;Quote:
Originally Posted by Signal64
yes and no: some BIOS not show correctly these valuesQuote:
Originally Posted by Signal64
Yes.Quote:
Originally Posted by Signal64
No, but the best is you to read datasheet at page 135 and above... :)Quote:
Originally Posted by Signal64
Is there anyway to bypass that locked MCHBAR thingie without having to use that tool listed in first post as it's not too convenient to use as I don't understand addresses and such anyways to make it practical. Locked MCHBAR is the only thing that bothers me having switched to a Abit IP35 Pro. :rolleyes:
Compile the following ISA Option ROM source code using FASM. Inject the ISA Option ROM binary into your bios using cbrom182. Your MCHBAR will be unlocked at bootup unless you have a version of Windows that is locking it.
Code:use16 ; 16bit mode
ROM_SIZE_IN_BLOCK = 1 ; 1 means ROM size is 1 block (512 bytes)
ROM_SIZE_IN_BYTE = ROM_SIZE_IN_BLOCK * 512
ROMStart:
db 0x055, 0x0AA ; ROM Header 55,AA -> Bootable rom
db (ROMEnd - ROMStart)/512 ; ROM Size in 512byte
jmp MAIN ;<------------ jump to main (Bug Fixed)
db 0 ; checksum, to be filled in later
times (256)-($-$$) db 0
MAIN:
pushfd
push eax
push ecx
push dx
mov eax,080000048h ; (G)MCH Base Address Register
mov ebx,000000001h ; copy register data for MCHBAR Enable
mov dx,0CF8h ; set port address
out dx,eax ; send address through the port
mov dx,0CFCh ; set port data
in eax,dx ; fetch data
and eax,0FFFFFFF0h ; set data byte to zero
or eax,ebx ; increase data by new setting
out dx,eax ; send data through port data
pop dx
pop ecx
pop eax
popfd
retf ; return far to system bios routine
times (ROM_SIZE_IN_BYTE-$) db 0 ; use 00h as the padding bytes until we reach the ROM size
; The last byte (512th) will be the patch_byte for the checksum
; patch_byte is calculated and automagically inserted below
PREV_CHKSUM = 0
repeat $
load CHKSUM byte from %-1
CHKSUM = (PREV_CHKSUM + CHKSUM) mod 0x100
PREV_CHKSUM = CHKSUM
end repeat
store byte (0x100 - CHKSUM) at ($-1) ; store the patch_byte
ROMEnd:
...is it writing "MCHBAR Locked" on memset?Quote:
Originally Posted by RPGWiZaRD
If it is, your MCHBAR is locked in Bus 0 Dev 0 Fct 0 ,OffSet F4h, bit [0];
If bit[0]=1, your MCHBAR is locked, and is not possible to reset this bit under windows.
...Have you trying this code yourself?Quote:
Originally Posted by JWilson
I see that ,in this code,you enable the mchbar in Bus 0 Dev 0 Fct 0 OffSet 48h bit[0] but memset (or other soft wich need to access mchbar) always do it.
but on Abit IP35 Pro or some other board, MCHBAR is locked in write at OffSet F4h (read my post above about it). :)
It will be interesting to test your code with write 0 at OffSet F4h...
I use the code on Biostar P35D2-A7. The Intel P35 Data sheet shows register 48h, bit 0 as the MCHBAR enable bit. On the same page it does mention the F4h register, but executing the code from the bios, register 48h unlocks the MCHBAR on the Biostar P35 board. The F4h register may do the same thing after the bios code is finished executing.
http://www.lejabeach.com/pics4/P35-88.jpg
Bus 0 Dev 0 Fct 0 Offset 48h bit[0] Enable/Disable mchbar for Read and Write,
for all motherboard.
Bus 0 Dev 0 Fct 0 Offset F4h bit[0] Enable/Disable mchbar for Write only,
for some motherboard (IP35, foxcon...).
It's always possible to access Offset 48h bit[0] under Windows,
but it's not possible to write 0 (under Win) at Offset F4h after that it has been write at 1;
It's the reason that your code will be interesting...
Can we have a linux version?
Or the src code to compile it?
On my laptop with chipset P945PM i cannot set CAS5 to anything else with memtest.
Is that a problem of memset or chipset or it is locked by laptop manufacturer?
...not possible to change Cas# under Windows.
And Linux version is not expect, sorry.
On a laptop with P945 cas5 to 4 did almost nothing in latency and read bandwidth. PL was 5. I also changed pl to 6 and 4 .
On 6 i have 5ns less latency but on 4 it is the same with 5 as tested with everest. Although memset reads 4 there is no change in performance.
Is that a chipset limitation?
2 years ago I launched memset, and I just find this screen: :rofl: ...
http://www.tyrou.net/Upload/memset.png
...sorry guys for had made an so horrible tweaker. :D
It surprises me you still have such a good sense of humour FELIX :up:Quote:
Originally Posted by FELIX
hahahah good oneQuote:
Originally Posted by FELIX
i tested the latest version on 790i board
everything working perfect mate :up: (once value can't be changed but no big deal you can select it in bios anyways :D)
there any new Memsets other then 35beta?
with bios 1004 of the maximus extreme, the TRFC range use to top out at 80 within memset, now the TRFC range goes down to 110 within the bios, and cannot be displayed within memset anymore.
bios goes beyond the range of memset in bios 1004 of the maximus extreme.
I add some highers values in tRFC, tRCD, tRP timings for P35/X38 in this version: memset35beta.exe
Felix, what's the lowest register encoded Performance Level possible on P35?
Can you have PL4? (I don't know which address/bit it is)
Why do both of my RAM modules have different PL on bootup?
In 3.5 BETA (downloaded before the above linked one) when I click to only show one set of values for both modules (tick box between A and B), many times it won't change.
Also, how can we check if a value we change in Memset actually changes or if it actually changes to that value?
Thanks :)
hey, how did you do that?Quote:
Originally Posted by FELIX
I was already running 35 beta... is this a new build?
either way, it works.
now I can see the new bios values just fine.
TRFC reports all the way to 127 now.
well beyond the bios range, and definatly something new to try out.
thanks.
I think it's possible to run at PL 2 with very lower DDR2.Quote:
Originally Posted by KTE
Yes it's possible.Quote:
Originally Posted by KTE
Performance Level is at OffSet 248h bit[12-8] for Channel A and 648h bit[12-8] for Channel B.
I don't know; with my IP35-PRO, if I boot with my G.Skill PC-6400 at 266Mhz, I got PL3 on channel A and PL4 on channel B... :confused:Quote:
Originally Posted by KTE
It's the same with Read Delay Phase Adjust.
Is timings on Channel A & B are the same?Quote:
Originally Posted by KTE
I don't understand? if you change a timing with memset and click on Apply, the timing is changed immediately.Quote:
Originally Posted by KTE
You can check it with Everest wich show timing in real time.
Yes, it's a new buid wich I add some tRFC values in this morning.Quote:
Originally Posted by Kunaak
At 1.7Vmch for P35 I can run PL 2 up to 240MHz FSB on 200 Strap on the P5K3 Deluxe.Quote:
Originally Posted by FELIX
With more Chipset voltage and better cooling, and some tweaking I believe it's possible to reach ~320MHz FSB with PL2 on P35.
[ don't take it to the bank though, it's just my impression from a quick quick test some months ago ]
According to this table
http://www.anandtech.com/mb/showdoc.aspx?i=3208&p=6
Default tRD at strap should be 166 is 4, at strap 133 = 2 and at strap 100 = 0
And according to the equation here
http://www.anandtech.com/mb/showdoc.aspx?i=3208&p=8
tRC - tCL/N > 0 for 200-266MHz on 1:1 divider you can run CAS 3-5 with tRC = 6
On my laptop i can run tRC = 4 for 166 strap (fsb) and cas 4 and divider N=2:1 so there at 133-200
the equation should be tRC-tCL/N = 4-4/2>1 or 0 again.
So you need more juice but the limit of the chipset stops you
Memset 35beta doesnt work well with Skulltrail (D5400XS).
Many settings appear to be able to change, but when you reopen Memset they are back to default.
Let me know if theres anything i can do/send to help.
how can i fix this error on vista?
http://img301.imageshack.us/img301/5...taerroroi9.png
i got it fixed now :up:
expected this addr for channel b and implemented it on my modified memtest boot cd.Quote:
Originally Posted by FELIX
felix and kte, i can confirm this for my ab9quadgt too! verified memset readings with a modified memtest boot cd which reads out all memory timings on my board for both cannels and shows a performance level of 9 for channel a and 10 for channel b at the 400MHz i am currently running the fsb.Quote:
I don't know; with my IP35-PRO, if I boot with my G.Skill PC-6400 at 266Mhz, I got PL3 on channel A and PL4 on channel B.
originally thought felix you might have mixed up something when reading the pl registers on my chipset, but as my own program confirms memset readings it has to be something within bios i guess ...
What modified memtest is that than can read PL?
Is there a link?
I'm confused on EPP timings being displayed in memset 3.5 beta.
Just took a look at the EPP spec and do not see tRFC (Refresh Cycle Time) and most of the other settings listed in memset EPP display being stored in the EPP.
Can you confirm how this is being calculated?
Is it a "best guess" or a known standard?
You are right, EPP show only tCL, tRCD, tRP, tRAS, tWR, tRC and command Rate.
Other timings in SPD table come from JEDEC.
I show these timings cause I suppose that they are applicate with EPP too. :confused:
I add intel X48 detection ID in this version: memset35beta.exe
And here is new BAR_Edit v:3.0
I add a full save function in this version: now is possible to save
all registers you want (in PCI and/or memory space) in a .ini file,
and possibility to load the save values by WritSav click or at windows startup.
Probably the finale version, I don't see what I can add now. :)
Eventually, Report me bugs...
No problem with displaying the other SPD settings when viewing the EPP. It has helped me out of a problem already :)Quote:
Originally Posted by FELIX
I'm still learning how the values for something like tRFC are calculated and trying to understand. The value displayed under EPP is correct for that speed but isn't displayed the same under the normal JEDEC SPD memory speed.
So some calculation appears to be happening?
i have modified the source code of memtest at my own to quickly read out the mem timings as bios has set it up but before windows loads.Quote:
Originally Posted by Spyrus
memtest was at hand and the sourcecode is straight forward.
modified just the subroutines for the intel p965 chipset. did nothing else as it involves a lot of reading through datasheets. modifying the code is actually the smaller part of work ...
so, no download for your chipset/board. as said before it will work for p965 chipset/boards only!
I have a p965 (still): can you send it to me? ;)Quote:
Originally Posted by fgw
Felix on mobile 945PM chipset it cannot detect more than 2048 of memory
and if it is single or dual channel (shows 2048 with 2x1GB or 2x2GB)
I will ask this a different way.Quote:
Originally Posted by FELIX
Displaying the non EPP timings is ok.
How are the missing EPP timings calculated for the EPP display?
I ask because I'm seeing a possible error for the tRFC calculation.
Felix, add please support for Intel 945GME mobile chipset (Memory Controller Device ID 27 AC instead of 27 A0 for desktop version of 945).
after changing like this it works -
Comparing files MemSet3.5.exe and MEMSET3.5_945GME.EXE
000017DB: A0 AC
00001D3B: A0 AC
0000237E: A0 AC
00002B3A: A0 AC
0002A5E4: A0 AC
0002B286: A0 AC
0002C2A8: A0 AC
0002D243: A0 AC
0002E489: A0 AC
0002EFC2: A0 AC
0002F1F4: A0 AC
0003040E: A0 AC
0003118F: A0 AC
00031C0B: A0 AC
00042748: A0 AC
00042858: A0 AC
00042AE4: A0 AC
0004580A: A0 AC
00046B9A: A0 AC
0004934B: A0 AC
000496F3: A0 AC
Could you run this soft, choose DMI-BIOS in the combo, and click on dmibios.txt.Quote:
Originally Posted by Spyrus
Send the text at memset@hotmail.fr...
Read this datasheet at page 35, 36, 37, its the tRFC calculation I use, with EPP Cycle time.Quote:
Originally Posted by Signal64
Could you try this version MemSet35beta.exeQuote:
Originally Posted by Compiller
and tell me the result...
here we go ...Quote:
Originally Posted by RealTelstar
Note: display is changed for P965 chipsets only! if you run this on any other chipset you will get standard memtest displays!
besides a little reformatting of the display page, i added the following:
1) FSB:MEM divider
2) description for memory timings and including tRFC (refreshcounter) and tREF (refreshtimeout)
3) detailed memory timings for channel A
4) detailed memory timings for channel B
detailed timings for channel A and channel B include:
tCAS
tRCD_rd
tRCD_wr
tRP
tRAS
tPALL_RP
tRFC
Performance Level
tWR
tWTR
tRRD
tRD_wr
tRTP
All Precharge To Refresh Delay
tREF (REFTIMEOUT counter)
MCH ODT Latency
use mt201_fgw.iso included in mt201_fgw.zip and burn it on a CD. it will boot and run memtest.
Felix - little cosmetic addition - Your name in About box in localized version of Windows looks incorrect.
Hi FELIX, I noticed that TS Read Delay doesn’t work on 965pm/gm chipsets. I can change it all the scale but nothing happens and the performance doesn't change. As I understand it is the same for performance Level and should be massive performance booster. Maybe you can fix it? Thank you.
Quote:
Originally Posted by FELIX
I have sent you the text dump
Hi Felix,
I am using Foxconn X38A P09bios, I got the following EA Exception error, can you pls have a look. Thanks.
What is the memset version, 3.4 or 3.5?
Under XP?
Felix could you please extend the limits of tRFC and tRTW ? [ needed for 790i boards ]
Yea, that would be nice.
Im using 780i, it works right?
I have a question about MemSet. Does it just change the timings in software, and they go back to BIOS values if you restart the computer, or does it change the settings in the BIOS?
They don't change in the bios when you hit apply. Don't know about using the save button though. I've only used it to change stuff till it crashes then go into the bios and change things manually.
Axis
Problem is, memset and the bios usually have totally different names for the same setting and I can't figure out what's what :(
-> BenchZowner & Spyrus: could you try this version and tell me the result?
Thank.
Yes under 32 bit XP & 64 bit Vista, both 3.4 & 3.5beta also got this error. I am using 1gx4Quote:
Originally Posted by FELIX
Yes it works...so are you gonna update memset with my fix and others posted lately? :up:Quote:
Originally Posted by FELIX
Could you run this soft, choose DMI-BIOS in the combo, and click on dmibios.txt.Quote:
Originally Posted by leotonch
Send the text at memset@hotmail.fr...
Works like a charm Felix.Quote:
Originally Posted by FELIX
Thank you very much :yepp:
Tried the beta and latest version, i get this error in ultimate vista x64 " The driver TVicPort cannot be found "
Here is the 3.5 finale version: MemSet.exe
What news: :)
-Add support for NVidia NForce 650 Ultra & NForce 790 chipsets.
-Add support for Intel PM965/GM965 (Mobile) chipsets.
-Add support for Intel P45 chipsets.
-Add spd informations for Intel chipsets with DDR/DDR2/DDR3.
-Add some higher timings values for 965/P35/X38 chipsets.
-Add reading some frequency with AMD Phenom CPU.
-Add Intel X48 detection ID.
-Improve reading memory frequency with Intel extreme CPU.
-Improve reading Command Rate with intel P35/X38 on some boards.
Tell me if you find bug or problem...
Well thank you for this.
I'll try it on X38T-DQ6, as you already fixed the command rate issue, there was one left(that I noticed) on half coefficient cpu's such as our new Wolfies & Yorkfields
:up:
http://pix.nofrag.com/b/5/d/cb92eb0b...d578c1c0tt.jpg here was my issue and it is solved.
If I hadn't been looking to upgrade a new mobo, I would have never known about Memtest program. The Memtest program I'm familar with only checked errors on your RAM.
There's still alot of people who are using older Gateway computers and OCed them (raises hand). Some of the Socket 754 Athlon 64 Newcastle mobo's were not allowed to change their RAM timings in bios. For years I was never able to change my timings.
Could the Admin please add this to the AMD forum as a sticky?
Hi,
I am using memset 3.5 on vista and have two problems.
- trfc values are not read properly. I have four banks of ram with trfc set to 127ns in SPD, but memset reads them as 127,105,75,75. Is this is a bug? Details in attached image
- Memset sees only 1280 mb when I have 4x1gb installed and Windows sees 3070mb.
- Changes are not persistent. When I click on "Save" memset creates a startup group and creates an .ini file. Vista crashes once I get past the logon screen after that. Have to boot under safe mode to remove memset.
When I create autorun entry manually using registry, memset loads after logon but does not apply values in .ini file. Any ideas?
...fullerms I just send you a PM.
I cannot change the Cas latency value. Neither is XP nor is Vista x64. Is it normal?