did you try playing with the voltages ??
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These Gskills
http://www.newegg.com/Product/Produc...82E16820231142
lol they would never I think I got them at the wrong time they switched to samsung like less then a month before purchase
Important Note:
If you guys are aiming for a high CPU Clock testing like 4.5Ghz DO NOT USE BIOS 1003. :mad:
At first I thought my E8500 has degraded but it wasn't. With 1.35v I can pass 10 loop IBT @600x7.5 without a single problem. But with 1003 BIOS no matter how hard I tweak still a no-go although an increase of vCore might help a bit.
:shrug:
ci2kla, check the vDroop on 1001/1003 - it's almost double earlier BIOS (with LLC off). LLC on seemed ok so it might not be same problem..
btw, i found 1001 is quite nice for clocking D9JNL @ CL8.. not sure how useful that is though ;)
I had the same problem with 1003. Anything over 4.0 Ghz and was not stable, went back to 503 and no problems so far @ 4.3Ghz.
I am using G.Skill and will try those settings 7-6-5-18 1T, we'll see how that goes :up:
i beg to disagree :D you just have to find a sweet spot between NB volts and FSB Termination Voltage.. in this case NB was 1.82v and FSB Termination Voltage was 1.59v.. cpu voltage was 1.92 (i think.. lol i cant remember) swiching to 1001 bios got me 40 more mhz and allowed me to clock higher with 2 cores enable :rofl:
http://i163.photobucket.com/albums/t...400hwbotWR.jpg
Hey guys, don't want to completely be a nay sayer but 1003 has been ok for me, both with an E8600 & very shortly with a QX9650. If anything, 801 was a real dog here.:( I had to go back to work but in the wee hours of the night before catching a plane early in the morning I slotted in the quad and quickly banged out a few 3D runs just for kicks. I'm sitting here offshore at work with just a few screen shots on my laptop but managed to take FSB up to 485 before having to shut it down, throw some clothes in the bag and go. Can't wait to get home and finish off the session!!:up: I believe I had LLC enabled.
im using 1003 and im running my E8600 @4.5 gigs @ 1.29 volts 24/7 stable I dont know dude I think certain hardware doesnt agree with 1003 but saying that I also up different voltages before touching my Vcore ive found upping the vcore from say 1.3 to 1.36 might get something stable or keep the vcore at 1.30 and up the nb two notches and the pll or vtt and with 1003 it is more picky with things like that
Just got this board, anyone has a template on settings to get 4.0 stable? Will be used for gaming only.
Im using 1003 BIOS and I am running a E8600
Patriot DDR3 PVS34G1600LLK 4GB
Hello to everyone and what a great bunch of techno wizards you all are.
I need help please as I recently got my hands on a pair of DDR3 Dominator TWIN3X2048-1800C7DF 2x1 Gig and would love to know what would the ideal CPU, RAM & NB Bios seetings be for the highest stable clock.
Matching the RAM is an E8600 and a BFG 8500 512 GTS. CPU, NB & GPU are all watercooled on a Zalman XT which sits under a window and gets me great low temps. Will take pictures and post soon.
Much obliged for any help
PS. Didnt get the chance to change my sig. Doing it now.
hi dctokyo :)
unless you want higher memory clocks / memory performance, these board settings for 4x1GB could be ok or as a starting point.
Only tested with 32-bit ;) and 0403 BIOS
http://i447.photobucket.com/albums/q..._800_4x1_1.jpg
some test settings not included below (shown as xxxxx): vcore / vDIMM / tRCD / tRP / tRAS / tRFC
Code:AI OVERCLOCK TUNER =========================MANUAL
OC FROM CPU LEVEL ==========================AUTO
OC FROM MEMORY LEVEL UP ====================AUTO
FSB FREQUENCY ==============================498 / 499 / 500 (500 = lowest Everest Read)
CPU RATIO SETTING ==========================8
CPU CLOCK SKEW =============================AUTO
NB CLOCK SKEW ==============================AUTO
FSB STRAP TO NORTH BRIDGE ==================333
PCIE FREQUENCY =============================100
DRAM FREQUENCY =============================1603
DRAM COMAND RATE ===========================1N
DRAM TIMING CONTROL ========================MANUAL
CAS LATENCY ================================7
RAS TO CAS DELAY ===========================xxxxx
RAS PRE TIME ===============================xxxxx
RAS ACT TIME ===============================xxxxx
RAS TO RAS DELAY ===========================AUTO
REF CYCLE TIME =============================AUTO
WRITE RECOVERY TIME ========================AUTO
READ TO PRE TIME ===========================AUTO
READ TO WRITE DELAY S/D ====================AUTO
WRITE TO READ DELAY S ======================AUTO
WRITE TO READ DELAY D ======================AUTO
READ TO READ DELAY S =======================AUTO
READ TO READ DELAY D =======================AUTO
WRITE TO WRITE DELAY S =====================AUTO
WRITE TO WRITE DELAY D =====================AUTO
WRITE TO PRE DELAY =========================AUTO
READ TO PRE DELAY ==========================AUTO
PRE TO PRE DELAY ===========================AUTO
ALL PRE TO ACT DELAY =======================AUTO
ALL PRE TO REF DELAY =======================AUTO
DRAM STATIC READ CONTROL ===================AUTO
DRAM DYNAMIC WRITE CONTROL =================AUTO
DRAM SKEW CONTROL
DRAM CMD SKEW ON CHANNEL A = AUTO
DRAM CLK SKEW ON DIMM A1 = AUTO
DRAM CLK SKEW ON DIMM A2 = AUTO
DRAM CTL SKEW ON DIMM A1 = AUTO
DRAM CTL SKEW ON DIMM A2 = AUTO
DRAM CMD SKEW ON CHANNEL B = AUTO
DRAM CLK SKEW ON DIMM B1 = AUTO
DRAM CLK SKEW ON DIMM B2 = AUTO
DRAM CTL SKEW ON DIMM B1 = AUTO
DRAM CTL SKEW ON DIMM B2 = AUTO
AI CLOCK TWISTER ===========================MODERATE
AI TRANSACTION BOOSTER =====================MANUAL
PERFORMANCE LEVEL ==========================08
PULL-IN OF CHA PH1 =========================DISABLED
PULL-IN OF CHA PH2 =========================DISABLED
PULL-IN OF CHA PH3 =========================DISABLED
PULL-IN OF CHA PH4 =========================DISABLED
PULL-IN OF CHA PH5 =========================DISABLED
PULL-IN OF CHB PH1 =========================DISABLED
PULL-IN OF CHB PH2 =========================DISABLED
PULL-IN OF CHB PH3 =========================DISABLED
PULL-IN OF CHB PH4 =========================DISABLED
PULL-IN OF CHB PH5 =========================DISABLED
EPU II PHASE CONTROL =======================AUTO
CPU VOLTAGE ================================xxxxx
LOAD-LINE CALIBRATION ======================DISABLED
CPU PLL VOLTAGE ===========================1.51V (min)
FSB TERMINATION VOLTAGE ===================min-1.20V
CPU GTLVREF 0 ==============================AUTO / +40mV
CPU GTLVREF 1 ==============================AUTO
CPU GTLVREF 2 ==============================AUTO
CPU GTLVREF 3 ==============================AUTO
NB GTLVREF =================================AUTO
NORTH BRIDGE VOLTAGE =======================1.25V (min)
DRAM VOLTAGE ===============================xxxxx
NB DDRVREF =================================AUTO
DDR3 CHANNEL A VREF ========================AUTO
DDR3 CHANNEL B VREF ========================AUTO
SOUTH BRIDGE 1.5 VOLTAGE ===================1.51V (min)
SOUTH BRIDGE 1.05 VOLTAGE ==================1.06V (min)
CPU SPREAD SPRECTRUM =======================DISABLED
PCIE SPREAD SPECTRUM =======================DISABLED
nice to see you back buddy :)
hope to be testing same mems myself by this weekend :D unless version number is not for me...;)
Thank you cheapseats..:up:
I too will dedicate a bit of this weekend to testing the Dom C7D CL77720 RAM Ver3.1 & see how we compare.
What do you think about the 1003 Bios for high FSB?
I see you still are on the 0403 1001?
Tata
great ragheb, mine came this afternoon and are also v3.1 :) no chance to test yet but i can see big ICs under the heatspreaders....
only been using 1001 for CL8 on the cellshock kit, but i prefer 0403 for everything else.
will test corsair with 0403 first and see what happens.
_______________________
last push on timings with the JNL CS3222271:
back to 2x1GB and just scraped a single successful 32M run with 7-7-6-12 timings @ 900mhz.
tRCD and tRP are a real pain with JNL IC, and all timings as tight as possible for clocks.
for same clock in 32M, 7-7-6-12 gave a small (but pleasing) boost over 7-7-7-12, with 7-7-7-14 a touch slower again.
but only talking about 1-3 seconds difference at 4.5ghz :D
max clocks i got for this kit with 32M pass:
7-7-6-12 ___ 900mhz (1800mhz) @ 1.93V
7-7-7-12 ___ 950mhz (1900mhz) @ 1.98V
7-7-7-14 ___ 980mhz (1960mhz) @ 2.04V
0403 / vNB 1.51V set / vDIMM 1.93V set / maxmem 580 / no copy waza
http://i447.photobucket.com/albums/q...612_10m05x.jpg
I was getting good results with 503. I tried 1003 again tonight and failed IBT before 20 runs. I loaded 1001 and using the same settings passed 15 runs of IBT. I think I am going to stay with 1001 and mess around with 1003 this weekend when I have a bit more time to tweak the nb, pll a notch or two. Mebbe it is just picky with this board.
For 7/24 Use?
http://i317.photobucket.com/albums/m...A666/85615.png
Well...Firefox still cause crashes even IBT Passed 10 loop :rolleyes:
i'm at 495fsb with a q9650 but i just can't get the last 5mhz. every time i do, the system locks up and freezes everything. even pressing the reset button will take about 3-5 seconds before it actually restarts. what is causing this type of freeze instability? i'm suspecting it's my memory. i'm writing down my settings right now and i'll post it in a bit
edit: here's my bios settings that i tuned myself:
Code:Processor: q9650
OC From Memory Level Up: Auto
Ai Overclock Tuner: Manual
FSB Frequency: 500
Ratio CMOS Setting: 6
CPU Clock Skew: -200ps
NB Clock Skew: -100ps
FSB Strap to North Bridge: 333 MHz
DRAM Frequency: 1601 MHz
DRAM Timing Control: Manual
1st Information: 9-9-9-28 (all other subtimings on auto)
DRAM Static Read Control: Disabled
DRAM Read Training: Disabled
Ai Clock Twister: Auto
Ai Transaction Booster: Auto
EPU II Phase Control: Auto
PCIE Frequency: 101
CPU Voltage: 1.34375
Load-Line Calibration: Enabled
CPU PLL Voltage: 1.55081
FSB Termination Voltage: 1.39166
North Bridge Voltage: 1.51097
DRAM Voltage: 2.00131
South Bridge 1.5 Voltage: 1.55081
South Bridge 1.1 Voltage: 1.10014
CPU GTL Reference (0): +60mV
CPU GTL Reference (1): +20mV
CPU GTL Reference (2): +60mV
CPU GTL Reference (3): +20mV
NB GTL Reference: +40mV
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
OK Time for more.
I'll post my settings now with E8500 dual core to achieve 600x7.5 IBT 10 loop stable.
Processor: E8500
OC From Memory Level Up: Auto
Ai Overclock Tuner: Manual
FSB Frequency: 600
Ratio CMOS Setting: 7.5
CPU Clock Skew: -400ps
NB Clock Skew: -200ps
FSB Strap to North Bridge: 266 MHz
DRAM Frequency: 1805 MHz
DRAM Timing Control: Manual
1st Information: 7-6-5-18 tRFC 72 (all other subtimings on auto)
DRAM Static Read Control: Disabled
DRAM Dynamic Write Control: Disabled
Ai Clock Twister: Auto
Ai Transaction Booster: tRD = 8
EPU II Phase Control: Auto
PCIE Frequency: 103
CPU Voltage: 1.3625
Load-Line Calibration: Enabled
CPU PLL Voltage: 1.61
FSB Termination Voltage: 1.37841
North Bridge Voltage: 1.65
DRAM Voltage: 2.00131
South Bridge 1.5 Voltage: 1.61
South Bridge 1.1 Voltage: 1.08
DRAM Channel A CMD Skew: Advance 100ps
DRAM Channel B CMD Skew: Advance 50ps
CPU GTL Reference (0): AUTO
CPU GTL Reference (1): AUTO
CPU GTL Reference (2): AUTO
CPU GTL Reference (3): AUTO
NB GTL Reference: +20mV
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: +25mv
North Bridge DDR Reference: +25mv
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
Note: If you want to get 600FSB 4.5Ghz stable with 333 Strap you will need ot adjust CPU Skew to 300~400ps and NB skew to 100ps. At least these settings works for me.