AMD "Piledriver" refresh of Zambezi - info, speculations, test, fans

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Originally Posted by sdlvx

Come on man lets keep this technical, instead of a bunch of rumors that showed up on a blog about how everything is automated and AMD is doomed because their chips use up 20% more space and lose 20% more performance. If you can show me the places where BD's die space can be reduced by 20% and where performance can be increased by 20%, please show me.

There's plenty of solid proof that the GloFo 32nm process is borked, primarily how there's no clock or VID difference between 32nm BD and 45nm Stars, while Stars was designed for efficiency and BD was designed for high clocks and there's a tradeoff between both.

Compare TSMC's 55nm and 40nm process with 4870 and 4770 GPUs. http://www.gpureview.com/show_cards....=564&card2=612 4770 is at the same clock, yet uses almost half as much power. These are the kinds of things we should be seeing with GloFo 32nm, but we're not. I doubt BD is that messed up where it would use twice as much power as Stars. I'm not saying it should use half, they are different archs and 4770 and 4870 are the same, but for power consumption to go up pretty much shows that there's serious issues with GloFo 32nm.

Because of this, I don't see 32nm Stars being much better than BD. Explain to me why a leaky and lossy manufacturing process is going to care about what architecture it's running on. From trinity it looks like BD is good when it's not leaking and running away with power consumption at higher volts.

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Well, Stars X6 with same amount of cache as Thuban would be 269mm^2.
If Stars could hit 300 Mhz more on 32nm, you'd be at the same level of MT performance of Zambezi with 25% less cores and 15% less die size which means roughly a 25% single thread benefit as well (25% difference between 6 and 8 cores).
Stars X8 with slightly less clocks would beat FX by a margin of 20% or so, with a die size of 336mm^2 which is ~6% larger than Zambezi.

I would imagine feeding > 2 Billion transistors instead of ~900 Million would cause a bit of current jump.
2 Billion is just ridiculous, and to think that resources have to be shared with that many transistors, has me scratching my head.

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Originally Posted by muzz

I would imagine feeding > 2 Billion transistors instead of ~900 Million would cause a bit of current jump.
2 Billion is just ridiculous, and to think that resources have to be shared with that many transistors, has me scratching my head.

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You would think that shrinking the exact same die would at least use same or less power draw on 32nm than 45nm nomatter how bad it is as well.
No matter what math you do and facts you show, a lot of people in this section will disagree and show you benchmarks that utilize all 8 clusters and how they beat Thuban by 10% @ 5 Ghz vs Thuban at 4.2. Then you come back with a single thread perf slide and they all look at you with their hands over their ears and go "NA NA NA NA NA", ignoring it. Then they say, well, it must have been GloFo's fault. BD is a good chip, look, it does better than my Thuban in benchmark A and F! ...you look and tell them, "what about benchmarks B, C, D, E?" ...they look at you and say "It's because those programs don't take advantage of Bulldozer's new instruction sets! That's why...new software will take advantage of them." (Despite the fact that intel dominates the market and programs are 90% of the time optimized for intel platforms) Then you look at them tell them that AMD should have shrunk X6, including Llano's updated cores for 5% IPC increase over current Thuban, and optimized cache, maybe worked on the northbridge so it was closer to this BD northbridge (further increasing IPC) and increased Mhz. They start running out of answers and say stupid :banana::banana::banana::banana::banana: like "IPC isn't everything" and post up AIDA memory bandwidth results at 2300 ram clock or whatever. Then they argue about how BD equals or beats SB in multithreaded apps albeit at a 30% higher power draw. Thuban could have done that on 45nm, clocked high enough. Here we go blaming the manufacturing process again.

AMD could have squeezed another 8 to 10% IPC out of the current architecture had they increased L2 to 1MB, integrated Llanos revised core, added a few MB of L3 (Thuban IPC was lower than Deneb due to less L3 cache) and revised the IMC to bring the type of memory bandwidth the new CPU brings. Instead, we have this fail called Bulldozer.

I could go on with my rant, but others will still look down upon me for looking at facts.

I'll buy BD, only because I was dumb enough to buy a 990FX board before BD came from out of NDA.

I'm not gonna sit here and say what they SHOULD have done, I'm not the man in charge....AAMOF, THAT guy is no longer in charge!!
I will give my opinion, and that is BD is basically a failure with common workloads of today, and that blows cuz I've been waiting a long time for it.
I'm hopeful for a better future, but not real confident after this reach.

http://www.anandtech.com/show/5058/a...nterlagos-6200

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Originally Posted by muzz

I'm not gonna sit here and say what they SHOULD have done, I'm not the man in charge....AAMOF, THAT guy is no longer in charge!!
I will give my opinion, and that is BD is basically a failure with common workloads of today, and that blows cuz I've been waiting a long time for it.
I'm hopeful for a better future, but not real confident after this reach.

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It fails equally in server workloads.

BD does pretty nicely in server workloads like business warehousing and transaction processing. It perform in between the 6 core ( 240mm^2 ) and 10 core ( 513mm^2 ) Westmere based Xeons. Of course, it throws 630mm^2 of die size in the fight, but it performs.

Server workloads, unlike desktop ones, like a lot of cores, even if individually they are relatively weak ( In BD sense, not ARM/Atom sense ). To almost match the 10 core Xeon EX behemoth is quite an achievement in my eyes.

Beep:or wait for PIledriver, will be at 100% better than Zambezi. We can expect +100-200 MHz higher clocks and a bit higher performance per clock.

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Originally Posted by BeepBeep2

You would think that shrinking the exact same die would at least use same or less power draw on 32nm than 45nm nomatter how bad it is as well.
No matter what math you do and facts you show, a lot of people in this section will disagree and show you benchmarks that utilize all 8 clusters and how they beat Thuban by 10% @ 5 Ghz vs Thuban at 4.2. Then you come back with a single thread perf slide and they all look at you with their hands over their ears and go "NA NA NA NA NA", ignoring it. Then they say, well, it must have been GloFo's fault. BD is a good chip, look, it does better than my Thuban in benchmark A and F! ...you look and tell them, "what about benchmarks B, C, D, E?" ...they look at you and say "It's because those programs don't take advantage of Bulldozer's new instruction sets! That's why...new software will take advantage of them." (Despite the fact that intel dominates the market and programs are 90% of the time optimized for intel platforms) Then you look at them tell them that AMD should have shrunk X6, including Llano's updated cores for 5% IPC increase over current Thuban, and optimized cache, maybe worked on the northbridge so it was closer to this BD northbridge (further increasing IPC) and increased Mhz. They start running out of answers and say stupid :banana::banana::banana::banana::banana: like "IPC isn't everything" and post up AIDA memory bandwidth results at 2300 ram clock or whatever. Then they argue about how BD equals or beats SB in multithreaded apps albeit at a 30% higher power draw. Thuban could have done that on 45nm, clocked high enough. Here we go blaming the manufacturing process again.

AMD could have squeezed another 8 to 10% IPC out of the current architecture had they increased L2 to 1MB, integrated Llanos revised core, added a few MB of L3 (Thuban IPC was lower than Deneb due to less L3 cache) and revised the IMC to bring the type of memory bandwidth the new CPU brings. Instead, we have this fail called Bulldozer.

I could go on with my rant, but others will still look down upon me for looking at facts.

I'll buy BD, only because I was dumb enough to buy a 990FX board before BD came from out of NDA.

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You're so full of it its not even funny ^^

http://tof.canardpc.com/view/be737ac...6cb38d7411.jpg http://tof.canardpc.com/view/22a6bc6...97501d5c1d.jpg

http://tof.canardpc.com/view/5d11aa0...687f4dfdd6.jpg http://tof.canardpc.com/view/165eaea...0070c73d63.jpg

http://www.donanimhaber.com/islemci/...-degerleri.htm

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Originally Posted by FlanK3r

Beep:or wait for PIledriver, will be at 100% better than Zambezi. We can expect +100-200 MHz higher clocks and a bit higher performance per clock.

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Why not 200% FlanK3r ? :p:

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Originally Posted by savantu

BD does pretty nicely in server workloads like business warehousing and transaction processing. It perform in between the 6 core ( 240mm^2 ) and 10 core ( 513mm^2 ) Westmere based Xeons. Of course, it throws 630mm^2 of die size in the fight, but it performs.

Server workloads, unlike desktop ones, like a lot of cores, even if individually they are relatively weak ( In BD sense, not ARM/Atom sense ). To almost match the 10 core Xeon EX behemoth is quite an achievement in my eyes.

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It does perform, but everyone forgets about one thing when talking about servers and that is power consumption. BD fails to keep low power consumption when being utilized.
More power draw = electricity cost + the cost for more cooling.

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Originally Posted by sergiojr

It is not processor frequencies that are not linear. It is transistor frequencies, that are. But as I said before processor frequency ~ transistor frequency/ critical path. So if there is a hypothetical 4Ghz barrier for K10 on 45nm, then this barrier will be around 5Ghz for Bulldozer on the same 45 nm techprocess (I assume that Bulldozer's critical path is around 1,25 times shorter based on Llano and Bulldozer 4-core frequencies and power consumption in CPU-dependent tasks).

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Again you forget leakage, if it wasn’t any leakage in the processor then it would behave that way you say. But if you get rapidly increasing leakage at a transistor level at 4GHz then you get that no matter the length of your critical path. And since 130nm leakage problems have been a growing issue. Before leakage became a problem you could see 50-100% frequency gain each node on the same architecture. After 2GHz that has been much less so, and above 3GHz it has been really slow. In the old days you could get twice the frequency by adding stages and shortening each stage, today you simply can’t do that for the same reason a new process don’t get twice the frequency anymore. Intel discovered this the hard way with P4, their short pipelined high IPC products could almost match their deep pipelined Prescott with low IPC, for an end result of much higher performance. That’s why IPC has been so important the last 5+ years. A deep pipeline which traditionally allows much higher frequencies has lost its advantage when both experience the same increasing leakage at a transistor level.

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Originally Posted by sergiojr

It is because 32nm techprocess is currently worse the 45nm (est. 5-10%). Of course it saves costs, but performance wise it's just worse. Probably they will match with Q1 2012 Bulldozer update.

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You can’t say for sure that’s the process. Intel have an incredibly good process with their 32nm, but SB-E with roughly the same size as Bulldozer consumes roughly the same power. Intels very good process just isn’t that good when you make a 2 billion trannie chip! So, that intels process gets just as bad when they try to make a gargantuan chip themselves is an indication that the size is too big to manufacture at lower power or higher frequencies.

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Originally Posted by sergiojr

There is something like 2,6Ghz 100W non-GPU Llano
http://products.amd.com/en-us/Deskto...False&f12=True
Not a fair comparison of course, but at least it is much more then you have to backup you claim.

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And that doesn’t mean :banana::banana::banana::banana: when it’s still made to be a full Llano with the same tradeoffs in silicon and transistor types. So you have nothing that points at 32nm being that bad. You can’t use Llano as an example since you don’t know which processes it’s made on! A GPU with hundreds of shaders might consume incredible amounts of power if it’s made on a processes tuned for high frequency like a CPU. And a CPU clocked at normal frequencies despite being made on a process made for low frequencies like a GPU will also consume more power and be a very bad overclocker. Intel don’t have this problem since their GPUs is tailored from the ground up to be on the same process as a CPU, an indication of this is the record breaking frequencies it’s GPU runs at and its small size, the drawback is that it doesn’t scale to well when you make it large like a traditional GPU.

Olivion: hehe, I said not 100% more, but at 100% better. I think, Trinity will be in CPU performance a bit better than Llano (of course, top Llano clocks will be 3 GHz and Trinity I expect at 3.6-3.8 GHz without Turbo)

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B3 Revision Q1 2012

AMD FX – Series B3 revision is more than just a basic stepping:
I have direct knowledge of a possible B3 revision for the AMD FX line of CPUs. I cannot disclose performance projections at this time, but be assured AMDs processor division is working vigorously on a (B3) stepping revision with minor architectural tweaks. The base architecture will not be changed at this time.

Within the B3 stepping revision, expect minor tweaks to the following:

1) L1, L2 and L3 latencies
2) Cache Thrashing Issues
3) Modified Algorithms for Branch Prediction
4) Healthy Bump in Processor Frequency
5) Slight Frequency increase via NB Controller
6) “Total Intelligent Control” For example programs and applications should look at the module design approach and the ability for the processor to intelligently turn off and/or turn on specific cores that it believes is hindering performance for maximum performance. (May be for Socket FM2, not sure at this time).
7) Power will be improved but not my much. We will have to wait for Socket FM2 or a future B4 revision for the AM3+ platform for better power efficiency especially when Over-clocked.

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source

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Originally Posted by -Boris-

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You can’t say for sure that’s the process. Intel have an incredibly good process with their 32nm, but SB-E with roughly the same size as Bulldozer consumes roughly the same power.

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But offer vastly different performance. The point is to get as much performance per watt.

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Intels very good process just isn’t that good when you make a 2 billion trannie chip! So, that intels process gets just as bad when they try to make a gargantuan chip themselves is an indication that the size is too big to manufacture at lower power or higher frequencies.

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Westmere EX had 2.6B transistors, 513mm^2 and burns the same power as a BD and it outperforms it in more or less anything. While I agree that GF's process is not as bad as people think ( performance wise, not yield wise ) it still has some challenges to overcome.

Btw, BD isn't 2B transistors, it's actually 1.2B ( a much more realistic number, the other one left 800m transistors unexplained, 1 module = 213m x 4 = 852m for the cores and L2, add another 380 for the L3 and you end up with roughly 1.25B )

Everyone points to ~2B transistors.
Everyone I have read.
Your saying they added more cache, and cores, and the # only jumped 300?

OLiverda:looks veryinteresting, but hard to say, if can it be right...

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Originally Posted by wez

You're so full of it its not even funny ^^

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Elaborate.
You must be even more 'full of it', you insult other members as if you are better than everyone.
Back yourself up, explain how I'm so 'full of it'.

@Tomasis
You must be equally 'full of it' for thinking his post is useful.

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Originally Posted by wez

You're so full of it its not even funny ^^

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Yeah, and like your :banana::banana::banana::banana:ing support for AMD is any better. They dropped the :banana::banana::banana::banana:ing ball on BD and they'll never recover it. It's a good thing that the new CEO fired all the idiots in the engineering department. After years of waiting, AMD delivers :banana::banana::banana::banana:.

when is b3 stepping belldozers going to be released? jan 2012?

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Originally Posted by savantu

But offer vastly different performance. The point is to get as much performance per watt.


Westmere EX had 2.6B transistors, 513mm^2 and burns the same power as a BD and it outperforms it in more or less anything. While I agree that GF's process is not as bad as people think ( performance wise, not yield wise ) it still has some challenges to overcome.

Btw, BD isn't 2B transistors, it's actually 1.2B ( a much more realistic number, the other one left 800m transistors unexplained, 1 module = 213m x 4 = 852m for the cores and L2, add another 380 for the L3 and you end up with roughly 1.25B )

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My point is that even Intels power efficient 32nm gets a lot worse when making huge chips. And your calculations is wrong, no way that L3 just uses 380 million transistors. The difference between Athlon II and Phenom II is 6Mb cache and roughly 450M transistors. My math would say 852m for cores and 600m for L3, and then IMC and HTT eats a lot to. So it's safe to say that it's way above 1.2 billion transistors, more like 1.7 billion+.

AMD has so far only made 1.5 and 2 billion chips at 32nm, no wonder they both produce a lot of heat and don't reach higher clocks than they do. Intel waited almost 2 years before launching such large chips at 32nm.

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Originally Posted by -Boris-

My point is that even Intels power efficient 32nm gets a lot worse when making huge chips. And your calculations is wrong, no way that L3 just uses 380 million transistors. The difference between Athlon II and Phenom II is 6Mb cache and roughly 450M transistors. My math would say 852m for cores and 600m for L3, and then IMC and HTT eats a lot to. So it's safe to say that it's way above 1.2 billion transistors, more like 1.7 billion+.

AMD has so far only made 1.5 and 2 billion chips at 32nm, no wonder they both produce a lot of heat and don't reach higher clocks than they do. Intel waited almost 2 years before launching such large chips at 32nm.

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Propus only has one hypertransport link compared to 4 links for Deneb (which shares it's design with Shanghai) so your math is off.

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Originally Posted by cal_guy

Propus only has one hypertransport link compared to 4 links for Deneb (which shares it's design with Shanghai) so your math is off.

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Good point, but if HTT links uses so many transistors that it really matters much then BD is still far above 1.25B transistors since Savantu didn't count them in. Either way it has to be closer to 2 billion.

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Originally Posted by BeepBeep2

@Tomasis
You must be equally 'full of it' for thinking his post is useful.

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it reminds me that you are still a child :) can you act more sensible, please?

saying all time how AMD should to do, like you know better than all engineers of amd alltogether. Ironic?

It doesnt make any sense, get of the past and act in current reality. Top priority for amd is get a competitive Opteron. They fail or not, it is an opinion of everybody and it just takes time to optimize softwares and it goes quickier there in server environment. Complaining about desktop performance is understandable.

Seriously, I have no idea why people are still crying about Bulldozer. Sure it's not the fastest chip,but at least it is overall faster than Thuban(sometimes a lot ,sometimes it's even slower). The good thing is that even in this worst case scenario when both design and process have some issues,it's quite a decent product. It just needs a price correction to be a bit more competitive from price/perf. POV.
Piledriver will improve on Bulldozer,Steamroller on Piledriver etc. The curve goes to the right direction so I don't know why some people are so pessimistic... If anyone thinks that AMD could have rode K10 on sub 32nm with 4+GHz clocks and 8+ cores with no changes to the uarchitecture itself is delusional.

It's easy to understand why ppl are disappointed.

For example, just look at your past expectation coming directly from your blog :

http://tof.canardpc.com/view/53c8859...4d6d89cfb4.jpg

Do you see the difference with the reality informal ?