Did someone mention fsb?
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Did someone mention fsb?
Damn man, im jelous!!!!
So far, same voltage. 1.512v (1.31v vid)Quote:
Originally Posted by kup
I plan to go to 3.76 then reduce volts where i can.
i got a little bored and figured i'd make a few small adjustments.
running a pass of memtest86+ atm roughly 50% complete.
495mhz fsb, 1190mhz ram, 5:6 divider 333mhz bclk, 1.55v vNB, pl 7, 1.64v vCPUPLL, 1.42v vTT, 2.24v vDIMM, dram controller ref -30mv, 5-5-5-16-45-5-2N, 0.62x CPUGTLREF, 0.57x NBGTLREF, ai clock twister = stronger, dram static read enabled, cha clk skew = -250ps, chb clk skew = -200ps, pci-e = 102mhz, vSB = 1.10v, vSB_SATA = 1.60v, cpu multi @ 6x till i certify mem subsystem stability then i'll make couple of adjustments and change it to 7x.
i'll update this once I have some results worth adding.
update: failed at 94% in modulo 20, so made a few small changes and rerunning that test. i'm still surprised it made it through 42mins. changes : vTT -> 1.44v, dram controller ref -> -20mv, cpu gtlref -> 0.63x, vNB -> 1.57v
seems those changes did the trick, running block move test again just to make sure the changes don't effect timings
I will give those settings a try and see how it goes on mine.
Isn't that NBGTL a little low? My settings are very similar to yours.Quote:
Originally Posted by mikeyakame
yeah apparently if i like to be able to soft power cycle then 0.57 is too low! had to increase it to 0.60x for sake of soft rebooting otherwise it gave me no problems.
just some preliminary figures so far, i havent really got any more adjustment in most of the memory timings, they are pretty spot on for these sticks as is.
edit: now the fun begins to tune the voltages so that there is crosstalk on the pci bus, yay for that. i have a good idea what to do to prevent it unfortunately its blind assumptions and educated guesses!
knocked another 0.2ns off memory latency by loosening up some of the tertiary timings, tWTPD. tALL_PRE_to_REF. tALL_PRE_to_ACT and tWR_RD_DR, these seem to positevely effect the bandwidth of the system with slightly more relaxed values. trying to figure out a happy balance between the nb and the sb, voltages are getting very near to each other so i'll see what can be reduced and what can take more voltage to distance them a little more. with the limited gtl ref adjustment i'm trying the higher vTT route with minimal gtl ref multis, it may just work.
edit: back to memtesting guess a few little changes here and there add up to far too many without bothering to run tests!
Awesome job man! PLEASE post your bios settings/voltages/gtls you used to achieve this. They should give me a great baseline for my FSB goals with this 9650.Quote:
Originally Posted by Zucker2k
yeah PLz post yer settings if u would !Quote:
Originally Posted by nugzo
vCPU_PLL is sitting around 1.78-1.79v for the time being time for fun
edit:
appears the cpu has hit an fsb wall around 480ish cause no matter what, there is two outcomes from heavy load onset, first is system lockup, the second one which after a few hours of tweaking I was able to consistenly produce has an outcome of < 30 secs before prime95 throws rounding errors, with 1.82v cpu pll i was able to push it out to about a minute which delays the onset. once i managed to isolate all the different voltages I could do normal tasks and run windows...unfortunately this is useless for anything besides screen capturing low latency everest shots! it wasn't all a waste as I managed to get 4 sticks of ram which were walling at 1150mhz out to 1190mhz at 5-5-5-16 and 2.26v.
My latest attempt for 500MHz FSB has failed as usual. I updated to the beta 0501 BIOS, and I can get 495MHz fine and linpack stable, but at 500MHz the system BSODs at the windows loading screen, regardless of voltages I use. Voltages for 495 were 1.531 on the CPU (with LLC), 1.69 on the NB, 1.6 on PLL, 1.38 on VTT. Admittedly, all DRAM settings and GTL settings have been left at auto, I don't have the patience to mess with them. Maybe if I did 500MHz or higher would be possible, but oh well.
can u post the link to the beta agin as the i got from an earler post says it not the right size ?Quote:
Originally Posted by 003
Thanx in advance .....
I got it from rapidshare, from this link:
http://rapidshare.com/files/15175657...rmula-0501.rar
I just downloaded it today.
thanx oo3 didn't realize it was rar file & had to D/l the utilty for it
I'm gonna sell my Q9450 the Q9650 is great !
Just a quick question. I have a E8400 E0, if I buy a new rampage will I need another cpu to flash this board to get it to start?
any of you guys using powerchip based 2gb dimms find the sticks overclocked better on either colour dual channel pair? white (a2/b2) or blue (a1/b1). i'm running a pair of gskill pi 1100s on the white slots now and couldn't for the life of me get them to pass memtest at 1200mhz! i'm going to try the blue pair later on tonight and see if I can manage it. Not sure whether its the sticks, the 266 strap the divider I want lies on, or the bios memory tables aren't all that great for powerchip ics.
Thank you. I'm aware of the official bios revision support. Doesn't answer my question, its likely to ship with an earlier bios than 407. I've had boards that allowed me to flash to the latest bios even when the cpu wasn't recognised correctly. What I want to know is will an E0 chip post on a new board so I can flash it.Quote:
Originally Posted by mikeyakame
Quote:
Originally Posted by nugzo
Sorry it took me so long, I've been quite busy. So here it is...Quote:
Originally Posted by bigslappy
Rampage Formula
Q9550 C1 @ 8.5x495
G.Skill 2x2GB PC2-8500 (1:1); kit couldn't handle DDR2 1188 [jk] :down: [/jk]
I ran these same settings on bioses 308 (333 strap), 403 (400 strap), and 501 (333 strap) and there all stable. I chose 308 because it gave me about 200MB more read speed because of higher TRFC. I highly recommend 0308.
Bios 0308
Overclocker Tuner: Manual
CPU Ratio Setting: 8.5
FSB Frequency: 495
PCIE Frequency: 110
FSB Strap To North Bridge: 333
DRAM Frequency: DDR2 990
DRAM CLK Skew on Channel A1: Auto
DRAM CLK Skew on Channel A2: Auto
DRAM CLK Skew on Channel B1: 250/300
DRAM CLK Skew on Channel B2: 350
DRAM Timing Control: Manual
RAM Timings:
Primary:
5-5-5-15-3-52-6-3
Secondary:
8-3-5-4-6-4-6
Tertiary:
14-5-1-6-6
DRAM Static Read Control: Enabled
Ai Clock Twister: Stronger
AI Transaction Booster: Manual
Common Performance Level: 8
CPU Voltage: 1.4875
CPU PLL Voltage: 1.50v (1.580v Real)
NB Voltage: 1.650v (1.680v real)
DRAM Voltage: 1.840v (1.90v real)
FSB Termination Voltage: 1.50v (1.38v real)
SB Voltage: 1.050v
SB 1.5v: 1.50v
CPU GTL Voltage Reference: x067
NB GTL Voltage Reference: x067
Load-Line Calibration: Enabled
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
Goodluck.
Next, I'll post my current settings for 24/7 @ 8.5x475, 4040Mhz and DDR2 1140 on my G.Skills (Max mem Linpack Stable).
yes it will, if its an older bios it will just say unknown chip but will work regardless. then you can flash the bios.Quote:
Originally Posted by fornowagain
gah tRD phase pull-ins are evil stuff. though I did manage to figure out something useful before I corrupted half my registry and wasted my night repairing my vista install!
for delayed dram clk skews, phase pull-ins on a/b1-> increment the dimm1/2/3/4 fine clock delay, and delay decrements it.
for advanced dram clk skews, phase pull-ins on a/b1-> increment the dimm1/2/3/4 fine clock delay, and advance increments it.
50ps seems to be equivalent to -+1t.
if all 4 dimm fine clock delay are not aligned, no read delay phase adjust clocks are added, if there is correct alignment then by pulling in phases the read delay phase adjust clocks are incremented, and mch data strobe is advance skewed with respect to DRAM data strobe.
you can use a phase pull-ins along with dram clk skews to adjust the dimm fine clock delay, but they are damned touchy and more likely you'll corrupt the cmos or your OS if you arent careful! so not for the weak at heart.
in a few days once I run my system through a bunch of tests to get 480-485fsb stable 24/7 properly, i'll work out exactly what the result of pulling in specific phases has in regards to data strobe skewing values. this time i wont be trying it with common pl of 7 at 486fsb on 333mhz strap, i'll be sticking to something like performance level of 8 or 9 since neither are too tight on this strap.
PL 8, phases pulled in. Advanced 300/350 A1/B1Quote:
Originally Posted by mikeyakame
Thanks :up:Quote:
Originally Posted by mikeyakame
I have a problem trying to set up my raid after i enter the intel matrix storage utility and set it up i also have to go into the bios under sata configuration and select raid instead of ide
the thing is that my os is running from a single raptor disk
So when i selct raid it recognizers my raid drives boots up my os from the single drive but computer crashes instead when i select ide it doesn't detects my raid drives and os boots up normally
Anyone who can help...
Thanks