Quote:
he processor runs all of its internal components—the CPU cores, memory controller, and I/O—in a decoupled fashion, so one can tune their respective frequencies and voltages independently. This isn't a new idea, Kumar stressed, but Intel's implementation is new in that it uses a synchronous interface between those components. Most past implementations have asynchronous interfaces, he claimed, which result in both higher latency and indeterminism—"if you test five different systems, you will get five different results." Because of the synchronous approach, Nehalem's memory-to-cache latency is allegedly "drastically smaller" than that of the competition.
How the heck they did it, I don't know -- the science of process technology, I can read and understand, architectural details I have been able to accumulate a great deal understanding (much with Kanter's help and reading a lot of Hennesy) and I am always eager to learn more, but circuit level implementations -- frankly, I am clueless -- I can sketch out a 6T transistor SRAM cell or some simple 4T inverters or a NOR gate circuit, but ask me to string it together or throw in a PLL or a power gate -- all you will get is a dumb look :)
