How to set up GTL Ref Values for 45nm & 65nm

Ok, so if I understand what I have read here and I probably do not, but still. I am using a QX9650 on a Maximus Formula with Rampage Bios 410. My current vcore is at 1.41v and my VTT is at 1.38ish. My GTL's are currently on auto. From this thread I have gathered:

1 - My VTT should be higher than my Vcore, i.e. VTT at 1.45v and Vcore at 1.38v.

2 - GTL ref should be set at .63 for cpu and .67 for NB since I cannot enter a "Y" number.

Did I get this right or am I missing something?

Thanks,

Utnorris

Edit: Currently at 416x10

I find around 0.62 or 0.63x NB GTLREF for that vTT to be about right. CPU 0.63 or 0.65x I find is adequate. vTT around 1.40-1.42v at sensor for that vCC should be on the mark for those GTLREF's. You can always add or subtract a little vTT and tweak the multiplier up or down to find the sweet spot. For the MF/RF that's all we can do to make balanced adjustments.

mikeyakame

I'm reading that to help with ringing, Intel connects the clock signal to a pull-up of VCore for one clock cycle on 0->1 transitions -- then it is removed and the signal settles to VTT. (Seems like this will help rise rate also.)
(http://edgeofstability.com/articles/.../gtl/gtl3.html)

If VTT is already ~Vcore, this won't have much effect?
Seems like it'll have reduced noise margin because it'll have more ring?

Quote:

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Originally Posted by CryptiK

As I said in the first post, most people start with 0.667x Vtt for 65nm and 0.635x Vtt for 45nm, however intel state use 0.667x for both processes, so I'd simply advise anyone to start with 0.667x, and work from there. Some have found lowering it to work best, others need to raise it.

As Mikey said, try to aim for around 0.80v, so that means as you raise/lower Vtt, you must adjust the GTL Ref multiplier to maintain the desired target voltage. If you have a BIOS that has the fixed multiplier and the Y value, use the formula and add or subtract the appropriate Y value to give the desired output voltage.

EDIT - I also use the Orthos calculation error frequency to tune GTL Refs, it seems to be the best way of doing it.

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Cyrptik and Mikeyakame,

I knew little about how these settings actually functioned before I got my P45 chipset motherboards. Previously I'd been using the AMD socket 939 platform. I certainly could tell however that adjusting these settings affected the extent and stabilty of my overclocks and I've spent quite some time through plain old "trial and error" arriving at the stable overclocks that I have acheived so far.

Thanks for sharing information on how these settings work and how they are interelated. I hope to take the knowledge gained from this thread to continue and improve my overclocking results.

I have a question Mikey. From what I have read, increasing Vref is required when the low level input signal crosses VIL (max) and as such this increases VIL (max) and prevents the input signal crossing it as it remains in the valid VIL range. If we raise Vref too far, it creates the problem that the high level input may cross VIH (min). My question is can this situation (the crossing of VIH (min)) be corrected by raising Vtt? What relationship does Vtt have with Vcc and Vref in terms of it's ability to aid stability and how does it relate to VIH (min) and VIL (max)? In essence, how does increased Vtt really aid stability? I have read a bit about this but I'd just like your opinion on it.

I ask as I have not been able to achieve much by playing with my GTL's other than getting 4005 MHz stable at one notch lower vcore than was previously required. However if I raise the speed to 4050 MHz, I have found it impossible to get it stable using the same vcore as 4005 MHz, and that raising Vtt above 1.16v, even when adjusting the GTL's to compensate to give the same output ref voltage (eg: ~0.8004v) causes the system to become less stable, and rather than erroring in Linpack, it will either just reboot or bluescreen. I'm just trying to understand the reasons for this situation.

I think I have proven what I thought to be true, in that adjustment of GTL's will not net much of a significant gain in stable FSB or overall CPU clock, but can provide a final stability to an almost totally stable clock, or in my case, allow slight lowering of vcore for a given stable clock speed.

@PolRoger - no problem at all, I just saw a lack of any mainstream discussion of this issue and simply shared what little I knew. Mikey's knowledge of electrical engineering relating to processor/motherboard function dwarfs mine, however, and I in turn am glad people with his knowledge base have contributed also.

Quote:

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Originally Posted by CryptiK

...
I ask as I have not been able to achieve much by playing with my GTL's other than getting 4005 MHz stable at one notch lower vcore than was previously required. However if I raise the speed to 4050 MHz, I have found it impossible to get it stable using the same vcore as 4005 MHz, and that raising Vtt above 1.16v, even when adjusting the GTL's to compensate to give the same output ref voltage (eg: ~0.8004v) causes the system to become less stable, and rather than erroring in Linpack, it will either just reboot or bluescreen.

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For me, setting GTL Ref was required to get above 420 MHz FSB -- I couldn't find a combination of other settings that would do it. (May be because I'm running a quad -- air cooled -- and I'm being a little conservative because it's $$$ to replace.)

One thing to try here is the cook-book approach that I stumbled-on while trying to understand how all of this interacts: Find the min GTL Ref and the max GTL Ref that'll meet some criteria (eg., boot windows; run linpak 1 cycle; prime for 10 minutes) and split the difference. If you have individually settable NB and CPU GTL Refs, do them separately. If that doesn't work, then GTL alone won't help...

(I just had a d'oh that my NB is 65nm and my CPU is 45nm so I need to use different GTL Ref values. I'm happily priming the next step now that I'm setting them appropriately).

Quote:

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Originally Posted by davidk21770

mikeyakame

I'm reading that to help with ringing, Intel connects the clock signal to a pull-up of VCore for one clock cycle on 0->1 transitions -- then it is removed and the signal settles to VTT. (Seems like this will help rise rate also.)
(http://edgeofstability.com/articles/.../gtl/gtl3.html)

If VTT is already ~Vcore, this won't have much effect?
Seems like it'll have reduced noise margin because it'll have more ring?

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Correct it does have a weak pull up driver but it does very little at high voltage, and i've found its more effective to rely on vTT acting as a limiter rather than the pull up driver tied to vCC. This seems to minimize transient overshoot from the pull up drivers inability to control the fluctuations at decent voltages above VID(max). Signal noise is expected at higher vCC and can't really be avoided no matter how hard we try. All we can do is adjust the area above the points where the slew rate is determined on the waveform (the points the slew rate is determined should split the ringback threshold range and the valid logical 0/1 range) and try to make sure that by doing what we are doing for that base clock frequency that all the criteria for validity meets what is expected. We can't know for certain but we can blindly figure it out by linpack, prime95, and other apps. All criteria meet when there is no errors or unpredictable behaviour.

I think I understand now what the DFI settings actually refer to. GTLREF Pull Up resistor resistance (ohms). By changing the resistance of the pull up resistor you effectively change GTL Ref voltage provided Icc_gtlref (current) is locked to a constant value. Typical is 124ohm, so to reduce the voltage you would increase the resistance or the value, and to decrease you would reduce the value.

> 0.667 * 1.20 (gtlref multiplier * vtt = gtlref voltage)
ans = 0.8004

> 0.8004 / 124 (gtlref voltage / resistance = gtlref current)
ans = 0.00645484

> ans*112 (gtlref current * 112ohm resistance = reduced gtlref voltage)
ans = 0.722942

this seems to make sense at this time of night! I havent really looked properly at an older DFI bios so If somebody wants to clarify this for me. I just worked it out by quickly looking at the values and finding a value on the datasheet somewhat close to it for agtl+ buffer specs.

This is all I can throw into the pot for the moment, I've been playing The Witcher for too many hours and my head is full of alchemical ingredients and other irrelevant stuff! lol I need some sleep I think! I'll edit this post up in the morning now it's 3.30am and I don't have the mental capacity to think this one all the way through!

Quote:

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Originally Posted by mikeyakame

Thanks for the support!

Now with your question. From my understanding the hole at 455-475ish requires a lot of GTL reference voltage to overcome the extremely small area under the curve that exists at nominal voltage. Your method of fine tuning GTL Ref voltage via Prime95 is spot on, and honestly thats exactly how I do it too. Adjust the multiplier based on calculation error frequency. The later the calculation error occurs the closer to ball park the GTL Reference voltages / multipliers is to nominal for that FSB and CPU frequency.

I've played with a DDR2 P5Q deluxe and it wasn't fun and games, it was one of the most unpredictable and poorly behaved chipsets I've encountered (p45 I mean), but it's by no means not without possibility of being tamed. Just really really irritating for the most part. I'd hate to be dealing with the DDR3 version, but its not so much Asus' fault (except for the horrible memory support) but rather Intel being stuck writing bios code to support speeds way above design specs due to user demand.

At 450MHz on the P5Q I know I was using 0/2 = 0.73x, and 1/3 = 0.715x for a 65nm chip with around 1.34v vTT, might have been 1.36v but its been a while. Perhaps try starting around there and see how that goes, I know this seems quite high but the idea is to move the crossing point where the rising and falling edges of bclk0 and bclk1 meet way above where they nominally should be, to a region where a valid logical 1 can be determined.

It would raise the value of vIH (input high), also raising vOH(output high), and since vIL(input low) and vOL(output low) can exist anywhere from 0.3v below the crossing threshold to 0v for a logical 0 there is plenty of area to determine the switch to ground for a logical 0. Raising vIH on the other hand means from my understanding that since ringback will always occur and at the point of the FSB hole you can shift the ringback margin inside the crossing threshold where it won't interfere in determining a valid logical 1. The excessive ringback occurs due to the amplitude of the voltage? required for those base clock frequencies from what I understand. I still have some gaps but I guess I try and do my best to explain it so it makes sense! Hell even I get confused explaining electrical theory sometimes! It's brain racking!

Any questions just shoot and feel free to drop ideas, theories and knowledge we can use to correlate all the data! The more gaps we fill the better we can get the understanding across to more people!

Thanks again for the kind words!

Edit: I also find PCIE freq of around 101-103mhz or 110-114mhz to work better at above 400FSB too. Not sure why exactly but its possible it's something to do with the way the frequency is divided from the base clock and multiplied from the analog PLL clock generator.

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Hi,

let me add my share of experience in stabilizing a P45 on the P5Q3.

I am using four DDR3-1600 1GB CL9 Corsair Dominator DHX modules, which are not certified to run in two pairs on this board. However I did not expect them to run at 1600, I hoped they would be good enough to run a bit above 1333.

I found that ASUS has most likely screwed up the memory defaults. The defaults shown after setting the board to manual memory timings are 5-5-5-15-5 ... Sorry? That's for DDR2, people. Has ASUS gone into mental ibernation? AUTO would only set the first four timings when reading them off the SPD, but the 5th timing is being overlooked.

Major RAM makers state that the fifth timing (tRRD, RAS to RAS delay) should be set to something around 8-10, so it seems to double like the other DDR3 timings. And matter of factly, the default of 5 is impossible to get primestable. It errors out after app. 10 seconds. 8 works fine tho.

Performance level must be set to around 9-11, any less and the board doesn't post.

And thirdly, tRFC (Row refresh cycle). ASUS defaults to 60, but at least 82 is often needed. I really recommend to check out the SPD programming with memset and then double this value. The Corsairs are programmed to 41.

Some other little tricks seem to generally apply to Intel chipsets.

Using four RAM modules requires usually 0.04V more on the Northbridge to accomodate the higher load on the data lines. No wonder. More inputs connecting to an outputs needs more current.

(How is one supposed to know what who doesn't have a backgound in electronics...and many forums are crammed with such people)

As for the other voltages you mentioned, they don't seem to be available int he BIOS. I suspect you are referring to a few additional lands on the CPU itself.

I could for sure modify them, however, I remember what it was like on the P5W DH when people started finetuning GTL references with trimmers. It must have been a PITA, since you do not exactly know where to go. Boot system, test, shut down. Twist a lil, boot test....

Ugh, no thanks. Tho I love the experimental approach which led eventually to board makers adding this function to the BIOS in later boards.

Anyway...let's see where this goes! feel free to send me a private message if this is going too far off topic.

:yepp:

So how does one know when to set the GTL's to positve, or negative voltage?? Is there a "laymans" way to "cipher" this stuff???

I know that my MFII has +/- settings, it was unstable at the - settings, so i went +, and it leveled out....

Settings:

FSB: 467
strap:333
Mem OC Charger: Enabled
AI Twister: strong
PL:8
Pull in's: enabled
PCIE:101
CPU V: 1.51875
PLL: 1.59275
FSBV: 1.32525
DRAM: 2.11800
NB: 1.43125
SB: 1.5000
SB 1.1: 1.10000
GTL's:
0 +10
1 +60
2 +10
3 + 60

Any input is appreciated....:cool:


Runninn Q6600GO BTW......

Screwtech02 - for your Vtt, I would start with:

GTL (0) +50mv
GTL (1) +10mv
GTL (2) +50mv
GTL (3) +10mv

This gives you a target Vref of around 0.89v

K man, i will give em a try.....

Quote:

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Originally Posted by CryptiK

Screwtech02 - for your Vtt, I would start with:

GTL (0) +50mv
GTL (1) +10mv
GTL (2) +50mv
GTL (3) +10mv

This gives you a target Vref of around 0.89v

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I changed em around a bit

(0) +10
(1) +60
(2) +10
(3) +60

Still stuck at 3.75, PL8....:shakes:

I dont get this either, im like the man above, i hate math, and i have never learned me advanced formulas

and all boards do NOT have Mv, most boards do got the multiplier type, and i dont get how to figure this out...

so if i got a 1.16 VTT , what do i use if u calculate it, and how? i really tried to understand, but im stupid or something.

No one said all boards have the mv setting. Only some do, other have multipliers and DFI's have something different again.

Intel state a GTL multiplier of 0.65 - 0.69 be used. Most use 0.667 to start with.

This can be made more complex but basically you want to aim initially for around 0.80v Vref, so if you have 1.16 Vtt, to find the correct multi to give you ~0.8v you go:

0.8v divided by 1.16v = 0.689v so you you'd choose the closest multiplier you have to 0.689.

Say you then raised the Vtt to 1.25v. To maintain the Vref at ~0.80v you'd go:

0.80 divided by 1.25v = 0.64v, so you'd choose the closest multiplier you have to 0.64.

Make sense?

You also want to keep the Vref under ~1.0v max.

Ok, thanks for that explanation, helped me actually understand it in an easier way :)

but my board doesnt have any vref setting, so dont know what to set. or are NB GTL vref? if i understand it correct?

but i still dont get totally what you mean, there are on most boards, now a setting of 0/2 and a setting fof 1/3 , and then the NB GTL

and i dont quite get which one you mean i would adjust?

Checked a site now, and as i get it if youre on a quad, 0-2 are DIE 1 , and 1-3 are DIE 2, but if on a DUAL, and thats 1 DIE , then 2-3 dont count right? thats how i get it as they explained.

Vref is the voltage that you get from the GTL Ref x Vtt.

so in the first example above,

0.8v is the target Vref
1.16v is Vtt
0.689x is the GTL Ref

So:

GTL Ref (the multiplier) x Vtt = Vref

When you have 0/2 and 1/3 set both to the calculated multiplier.

Ok thanks, have now set both to 0.690

omg :) soon i will change to rampage extreme, and there the values are in Mv, time to learn this crap hehe...
as im pretty good in the OC, but DONT get this GTL at all.
appreciate you expleanation, looks like its easier to calculate it on multiplier boards than on those with Mv?

and the NB GTL then? how do u calculate that? :P

The boards with mv are a bit weird IMO it would be easier to just have the multipliers. That's just the way it is though. Working out the mv is not hard though don't worry.

You calculate the NB GTL the same way as for the cpu, it is based off Vtt as well.

Well the NB VREF works out for me, like this;

1.28vtt x 0.670 = 0.8576

1.34 x .640 = 0.8576

(1.34 being my NB voltage and .640 being my NB gtl setting).

So, that explains why I can't lower my NB Voltage without being stable, as my cpu needs the 1.28vtt to be stable at 480fsb.

@CryptiK TY, I finally got it pumped into my Old brain how it all works, it was a bit Hazy before, but very Clear now. It's a Beitch getting Old :)

So according to my calculation, I can't drop my NB volts until I get my VTT lower. So far that isn't happening, so best I just leave it alone!

EDIT; After playing with my calculation I was wrong above, if I change to 1.32v for the NB and run a GTL of 65 it gives me the same VREF,(close enuff). Sheesh/ need more coffee here!

Larry

An engineer I am not, that would be my Daughter. I have read and read this thread and took a few notes and this is what I have come up with as a start. If I want to use 1.45 vcc I should set vTT about .2 higher so let's say 1.47vTT. With that vTT the GTLref would work out to .54mv using the 0.80/vTT formula. I should also set PLL at 1.67 using the Vcc x 115% formula, and set vNB to the same. NBGTLref would be -.29mv using the 1.2 x.63 minus the 1.47 x .63 formula. Broken down it would be like this:

If vCC = 1.45 then:
vTT = 1.47
PLL = 1.67
cpuGTL = .54
NBGTL = -29
NBv = 1.67

Did I get this right as to getting a starting point?

what is really the target in mv? to be more exact? is it 0.8 ? or 0.9? or 0.85?

it differs with pretty much in GTL settings, if its 0.8 or 0.85 ..so wich? :)

Like i said earlier, how do you tell between needing positive, or negative settings????:confused:

Quote:

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Originally Posted by CryptiK

No one said all boards have the mv setting. Only some do, other have multipliers and DFI's have something different again.

Intel state a GTL multiplier of 0.65 - 0.69 be used. Most use 0.667 to start with.

This can be made more complex but basically you want to aim initially for around 0.80v Vref, so if you have 1.16 Vtt, to find the correct multi to give you ~0.8v you go:

0.8v divided by 1.16v = 0.689v so you you'd choose the closest multiplier you have to 0.689.

Say you then raised the Vtt to 1.25v. To maintain the Vref at ~0.80v you'd go:

0.80 divided by 1.25v = 0.64v, so you'd choose the closest multiplier you have to 0.64.

Make sense?

You also want to keep the Vref under ~1.0v max.

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ok i understand (doesnt work for me) but what with NB GTL?