TechReport on Barcelona

http://techreport.com/articles.x/13176

Table at the bottom of that page, and from my quote above, the cache latency is affected by the northbridge speed as it is incorporated into the package itself.

I may be wrong, please correct me if i am :)

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Originally Posted by terrace215

Of course. There's a slow L3 in the way on the K10. That's the trade off.

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No, not of course. The L3 adds a L3 eviction and write back penalty on an L3 miss (in addition to L1 and L2), but the improved DRAM prefetchers, buffers and crossbar should be making up for it. It looks to me like 40 cpu clock cycles are being eaten up.

There's no website bias in SPEC scores.

http://www.techarp.com/article/AMD/B...ec_results.png
http://www.techarp.com/showarticle.a...tno=443&pgno=3

That tgdaily article forgets to mention the fact that the Xeon is clocked 233Mhz higher. Meaning that Barcelona is pretty good, especially being benched on such a new platform. For instance, the IMC wasnt overclocked.

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Originally Posted by DoubleZero

There's no website bias in SPEC scores.

http://www.techarp.com/article/AMD/B...ec_results.png
http://www.techarp.com/showarticle.a...tno=443&pgno=3

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Given the spec rate numbers are so much better than the old Opteron, I think the latency is being traded for bandwidth, but the techreport 1 GB cache+mem sandra bench (11.5 gb/sec) is about 2/5th what my overclocked 3.08 GHz Allendale does. So I don't see the bandwidth..and the spec rate isn't translating into great app performance. I still think somethings screwy, BIOS, drivers or L3 cache.

Interesting thread at pcper, apparently not many barc samples about.. limited to non desktop apps?

http://forums.pcper.com/showthread.php?t=445374

I guess this means no reviews of barc on games other than the anand preview for a bit going forward.

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Originally Posted by Richie P

From what I understand, what Jacky was getting at with the cache latencies being reduced at a high clockspeed is actually correct. When going to RAM, the processor has to go through all the cache levels of the processor, including the 'slow' L3.

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from what i've read the l3 cache is a spilloff cache, and the memory controller feeds the l2, so the CPU isn't held up by the l3 latency (which would result in a pretty bad performance hit).

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Originally Posted by Richie P

The latency of the L3 cache is proportional to a speed (not sure on the terminology) that is increased when the clockspeed is raised. Therefore, with figures quote on the Tech Report site, the cache latecies are 23ns on the slower 2.0Ghz chip and 19ns on the faster (2.5Ghz) chip.

Therefore, increasing the clockspeed could result in what would seem a higher IPC.

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cache latency (seconds) = latency (clocks) * duration of a clock (seconds)

and duration of a clock (seconds) = 1/frequency (to get seconds per cycle instead of cycles per second)

so latency (clocks) = latency (seconds) / (1/frequency) = latency (seconds) * frequency

using 23ns @ 2ghz, 19ns @ 2.5ghz:
(23*10^-9)*(2*10^9) = 46 clocks
(19*10^-9)*(2.5*10^9) = 47.5 clocks

latency in clockcycles increased going to 2.5ghz, there's no way you'll get better than linear scaling... that was a myth

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Originally Posted by hollo

from what i've read the l3 cache is a spilloff cache, and the memory controller feeds the l2, so the CPU isn't held up by the l3 latency (which would result in a pretty bad performance hit). cache latency (seconds) = latency (clocks) * duration of a clock (seconds)

and duration of a clock (seconds) = 1/frequency (to get seconds per cycle instead of cycles per second)

so latency (clocks) = latency (seconds) / (1/frequency) = latency (seconds) * frequency

using 23ns @ 2ghz, 19ns @ 2.5ghz:
(23*10^-9)*(2*10^9) = 46 clocks
(19*10^-9)*(2.5*10^9) = 47.5 clocks

latency in clockcycles increased going to 2.5ghz, there's no way you'll get better than linear scaling... that was a myth

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Thank you!!!! I don't think people really understand this concept.

Guys.... processors do not understand time, they are digital -- they know 'tick-tick-tick', the temporal spacing of 'tick-tick-tick' is what you and I understand.... IPC will not get better by simply raising clock speed.... not possible.

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Originally Posted by JVguest

No, not of course. The L3 adds a L3 eviction and write back penalty on an L3 miss (in addition to L1 and L2), but the improved DRAM prefetchers, buffers and crossbar should be making up for it. It looks to me like 40 cpu clock cycles are being eaten up.

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There is a penalty for having L3 cache if the miss goes straight through and requires access to memory, no way around that.... you will spend the extra time snooping the L3 that normally would not have occured if L3 was not there.... so it gets in the way a little.... the net benefit should be positive though so long as the compounded latency is much less than a call to main memory for all the hits.

Well I must say, I'm not entirely surprised, but still disapointed that AMD couldnt come through with barcelona. I was hoping for atleast 1:1 performace clock for clock with core2, but that doesnt seem to be the case.

Unified core and lower power consumption will not win my heart when I design a new system.

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Originally Posted by Richie P

Not correct.

From what I understand, what Jacky was getting at with the cache latencies being reduced at a high clockspeed is actually correct. When going to RAM, the processor has to go through all the cache levels of the processor, including the 'slow' L3. The latency of the L3 cache is proportional to a speed (not sure on the terminology) that is increased when the clockspeed is raised. Therefore, with figures quote on the Tech Report site, the cache latecies are 23ns on the slower 2.0Ghz chip and 19ns on the faster (2.5Ghz) chip.

Therefore, increasing the clockspeed could result in what would seem a higher IPC.

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I think you need to read more about CPUs , somebody explained it nicely : http://www.xtremesystems.org/forums/...&postcount=107

I'll add this because hollo fails to account for the RAM latency :

Assuming RAM latency 40ns

At 2GHz we have total latency 63ns or 126 cycles.
At 2.5GHz we have a total latency of 59 or 147.5 cycles.

All of a sudden a cache miss isn't as minor as some think.You spend 17% more clock cycles time waiting for memory.As a result IPC is lower.

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Also, TG Daily slamming AMD with a pro-Intel bias? Well I'll be damned... :shakes:

EDIT: Also, after more careful reading,

And correct me if i'm wrong, but the motherboard doesn't support split power planes, so the memory controller would have been running at 1.6Ghz. Based on that fact alone, we should see improved performance from the new mobos.

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The servers tested were supplied by AMD and used split power planes mobos.

Savantu, how is 40 ns out of 59 cycles only 17% slower? Anyway, typically L2 latency is 15 cpu cycles on core 2/K8 while going to main memory is 150+ cycles. It's 10 times slower going to main memory, fortunately with branch prediction and caches it doesn't happen often. Main memory access can be generalized as 10x slower than cache. A cache miss always causes a major slowdown, but AMD minimizes that with IMC.

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Originally Posted by JVguest

Savantu, how is 40 ns out of 59 cycles only 17% slower? Anyway, typically L2 latency is 15 cpu cycles on core 2/K8 while going to main memory is 150+ cycles. It's 10 times slower going to main memory, fortunately with branch prediction and caches it doesn't happen often. Main memory access can be generalized as 10x slower than cache. A cache miss always causes a major slowdown, but AMD minimizes that with IMC.

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I'm not sure we're talking about the same thing ; I'm not comparing memory vs. cache access time , but how costly is a cache miss in clock cycles while running at different frequencies , hence lower IPC at higher frequencies.

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Originally Posted by MaxxxRacer

Well I must say, I'm not entirely surprised, but still disapointed that AMD couldnt come through with barcelona. I was hoping for atleast 1:1 performace clock for clock with core2, but that doesnt seem to be the case.

Unified core and lower power consumption will not win my heart when I design a new system.

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It is the case actually, it's a lower clocked cpu vs a higher clockec cpu and it wins often so...

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Originally Posted by BeardyMan

It is the case actually, it's a lower clocked cpu vs a higher clockec cpu and it wins often so...

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Yes, the 2.33GHz Clovertown does win often against the 2.5GHz Barcelona in Techreport's review.

nice, techrepot really does nice articles!

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Originally Posted by accord99

Yes, the 2.33GHz Clovertown does win often against the 2.5GHz Barcelona in Techreport's review.

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Opteron 2350 2.0Ghz vs Xeon L5335 2.0Ghz

1)Sandra Cache and memory bandwith
*11534 vs 5179
higher is better
Opteron 2350 2.0Ghz


2)Cpuz memory access latency
*91 vs 95
lower is better
Opteron 2350 2.0Ghz


3)SPECjbb
*88949 vs 87099
higher is better
Opteron 2350 2.0Ghz


4)Valve VRAD map build time
*121 vs 107
lower is better
Xeon L5335 2.0Ghz

5)Cinebench
*12623 vs 14129
higher is better
Xeon L5335 2.0Ghz

6)POV ray rendering
*77 vs 80
lower is better
Opteron 2350 2.0Ghz


7)Merimatch benchmark 8 threads
*372 vs 379
lower is better
Opteron 2350 2.0Ghz


8)Folding @ home
* 4 wins vs 2
Opteron 2350 2.0Ghz


9)The panorama factory
*23.05 vs 20.41
lower is better
Xeon L5335 2.0Ghz

10)PicColor
8.09 vs 10.11
higher is better
Xeon L5335 2.0Ghz

11)windows media encoder
*543 vs 510
lower is better
Xeon L5335 2.0Ghz

12)Sisoft sandra
*296230 VS 335126
higher is better
Xeon L5335 2.0Ghz

13)power consumption
* 2 wins vs 0
Opteron 2350 2.0Ghz


Is it me or is 7 more then 6...:rolleyes: :D

I wouldnt even look at 1+2+12.

Also for folding, almost all WUs are gromacs. The bench also takes old outdated WUs in place without SSE support. x87 is dead in 64bit too. Kinda like you also see a K8 beats a K10 in x87 tho 2.5 vs 2.6Ghz.

But all the rest, yes.

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Originally Posted by BeardyMan

Opteron 2350 2.0Ghz vs Xeon L5335 2.0Ghz

1)Sandra Cache and memory bandwith
2)Cpuz memory access latency

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These are characteristics of the platform, not benchmarks of performance.

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6)POV ray rendering
*77 vs 80
lower is better
Opteron 2350 2.0Ghz

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There are two POV tests. The L5335 is faster in the second. I'd call this a draw.

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8)Folding @ home
* 4 wins vs 2
Opteron 2350 2.0Ghz

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There are only 4 tests, with L5335 winning in the most important gromacs cores. Considering Tinkers and Amber units are hardly processed anymore the averaging score is suspect and it's a draw at best for the Opteron.

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12)Sisoft sandra
*296230 VS 335126
higher is better
Xeon L5335 2.0Ghz

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I wouldn't even bother with synthetic tests like these.

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13)power consumption
* 2 wins vs 0
Opteron 2350 2.0Ghz

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Not a test of speed.

By my count, the Opteron 2350 wins 2 tests, the Xeon L5335 wins 6 and there's a draw in 2 with the Sisoft test excluded.

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Originally Posted by Shintai

I wouldnt even look at 1+2+12.

Also for folding, almost all WUs are gromacs. The bench also takes old outdated WUs in place without SSE support. x87 is dead in 64bit too.

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Shintai it seems you and other don't get the point :)
It's not about it wins there and there and it gets pwned there and there..

it's about AMD being back with a nice and good competitive cpu.
Many l seem to trash it while i just prooved that it's uncalled for :)

If but i doub't it really, K10 scales on a different way other cpu's do, then i see them take more wins at 3.0ghz... but that can be wishfull thinking :D

K8 beating K10 is pretty sad yes, but aren't there test were P4 beats a C2D as well ....

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Originally Posted by accord99

T

Not a test of speed.

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LOL weight your words carefully :)
Power consumption is very very important in teh server market.. or do you think electricty is free :D

SmartASS it doesn't matter really :)
It seems youre reading selective and only what you wanne read.

This is what i stated in a previous post

It's not about it wins there and there and it gets pwned there and there..

it's about AMD being back with a nice and good competitive cpu.
Many seem to trash it while i just prooved that it's uncalled for


period :)

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Originally Posted by LOE

SmartASS - the sandra score shows actual performance the same way memory bandwidth does, even less

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Umh no...

It shows what the chip is actually capable of if its units are used to full extent.