Reading comprehension is a B!tch isn't it?
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http://www.xbitlabs.com/images/cpu/a...0/platform.jpg
http://www.septor.net/specs/amd/img/AMD8151BlockL.jpg
http://www.hothardware.com/articleim.../blockdiag.png
especially when memory doesnt have anything to do with hypertransport.....
doesnt look like the memory controller is connected with a hypertransport bus
GREAT!
That just makes my argument THAT MUCH STRONGER.
Core to core communication doesn't use HT either on 1 socket systems. So THERE GOES THAT THEORY.
If the memory bus isn't sharing HT bandwidth, then that what ON EARTH do you possibly expect to consume >12.8GB/s of bandwidth?
Are there genuine gripes here or are people just mad AMD is getting smoked? :welcome:
Still waiting on YOUR proof that HT2/3 is needed to overcome some mythological bottleneck.
I'll HAPPILY admit that having the memory bus on the HT bus was an error on MY PART. But still doesn't INVALIDATE the point that on a SINGLE SOCKET SYSTEM, there is bandwidth to spare on the HT bus.
That is the SINGLE POINT you have trouble grasping (that poor reading comprehension thing again - bites you in the arse every time).
I'm pissed, for one, that K10 only comes up to par with an architecture that has been out 16 months now. It means we are all going to get d!cked over at the cash register when we buy high-end equipment.
GoThr3k just has this unfounded idea that HT3 is magically going to make K10 a faster CPU. HT3 doesn't do SQUAT unless you are in a multi-socket system.
QFT
however NB speed in K10 has a HUGE impact on performance and if i understand it correctly ht link speed + NB speed is the same on HT3 the HT link speed does have a significant impact on performance with K10 (not due to limited I/O bandwidth more due to a higher NB+L3 frequency -> more effective prefetchers and lower latency L3 cache
LinkQuote:
Split power planes. Feeding the memory controller and the core from different power rails is not a direct improvement to the memory subsystem, but it does allow the memory controller to be clocked higher than the CPU core.
So modifying the NB speed is more an energy efficiency thing than an OC feature.;)
Kyosens latency (1800mhz)
some more posts ago this user said that his IMC runs at 1400 mhz-note the higher latency
and as we know K10 IMC speed = NB speed
NB communicates to the CPU via HT, it's been this way since HT1.
But the L3 talks to memory, not the NB.
Sure you aren't looking at memory latency? Those latencies are horrible for a cache (even L3).
EDIT - I was referring to the first link which talks about ns time, fyi. The second one clearly shows cycles (which at 52 cycles is not pretty also).
mstp2009 lets wait for the 19th/20th i think then there is plenty of information available to discuss stuff like this. :)
kyosen got 43 cycles with 1800 mhz on the L3 cache:
kyosen's screenie
still not pretty but it shows what i mean ;)
Ah, ok it was not mentioned in the article what stock clock the phenom has. Thank you for the clarification.
Ok, from an extreme perspective that has an impact. :rolleyes:
I thought about a more efficient memory sytem at lower cpu clocks.
yes HT 3.0 is not so usefull for single socket, but don't forget, HT 3.0 motherboards come with split plane, and increase the memory controler frequency. ;)
It's a new serial cache. It's a bit different from old cache but it's as fast even the high cycles latency.
Brisbane use the same cache for L2 ( K10 for L3 ). It's high latency but it's as fast. :yepp:
both B1 check cpu-z screens.
as L3 cache seems to handle cache traffic between the cores (L2) and serves as a buffer between the CPU and the IMCs there should be some more % achieveable by increasing NB freq...
and we still don't know if the IMC runs in ganged or unganged mode (unganged allows the IMC to write and read at the same time opposed to read/write only in old K8 IMC, at least that's how i understand it after reading kyosens thread), if the IMC runs ganged there is a chance that K10 can get a higher IPC than yorkfield (but i don't count on it :rolleyes: )
IIRC doesn't the L3 cache and IMC scale their MHz/GHz speed differently depending on the CPU multiplier and the relative frequencies of the cores?
There was some complex BS going on w/ K10 that made it pretty decent (on par w/ C2Q) at certain frequencies, and absolutely SUX at others.
I will show you guy the Retail version test with GP9600, like Cinebench score will announce soon.
you would know about the Phenom default performance.....
the new CPU-Z Version can show NB speed and correct memory speed and timing...
here...version CPU-Z Version 1.41.4 preview
http://img232.imageshack.us/img232/3...0400pr8.th.png