been trying to break 4.0GHz stable for a few days now, 4.0 is stable just cant get anything higher, I also cant get 500 FSB stable on any multi.Quote:
Originally Posted by kwalker
How are you running your GTL's?
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been trying to break 4.0GHz stable for a few days now, 4.0 is stable just cant get anything higher, I also cant get 500 FSB stable on any multi.Quote:
Originally Posted by kwalker
How are you running your GTL's?
GTL's set at auto for now.Quote:
Originally Posted by Grnfinger
the only thing I'm skeptical of is pll voltage at auto.
If I remember my electronics phase lock loop is a function on the motherboard that compares frequency input to output.
if there is a variation the pll circuitry sets it straight and voltage is the trick.
weather or not this implementation is on the motherboard or a function of the CPU evades me but I cant see such a device being on die.
I'll let you know what smokes first:D
1.50 PLL is good up to 480FSB for me anyways, after that I set 1.525.Quote:
Originally Posted by kwalker
I'm not running anything on auto except for Mem OC charger ( no idea what that does yet)
and the Mem Read Training is also set to auto for I have little information regarding this option.
I'm more interested in CPU Clock Skew and NB Clock Skew, and how they play in terms of performance vs stability.
Running stable at 1.35 vcore I feel my chip has alot of headroom and would like to fully max the 24/7 setting.
With advice/exchange of ideas and some other bios setups to compare I'm sure 4.2GHz is possible for 24/7 use.
Besides I just recieved a nice kit of Mushkin ram that does 1250MHz so I would like to max my fsb and break 10k in Everest.
500 FSB is doable 24/7 on this board with a decent 45nm quad (E0)Quote:
Originally Posted by Grnfinger
I bet with the help of a few of us here we can get the others to cooperate as well. :cool:
I'm working on the other functions of this board as well and though I have an Idea what clock skew is I am having a difficult time digging up schematics that don't date back to the stone age :D.
Its all memory bandwidth related and has to do with controlling how data or electrical signals arrives at different devices in a circuit at different intervals of time.
Not such a good thing as frequency's increase and temperature/current starts to degrade the signal timing
lets just call it fine tuning of a pulse modulated circuit for lack of better terminology.
What kit is this Grn? 2x2Gb?Quote:
Originally Posted by Grnfinger
Mushkin XP2-8500 2x2GB kitQuote:
Originally Posted by ChaosAD
going to test them tonight after my kids are in bed.
Hey can you post some of your settings.Quote:
Originally Posted by barong
I am running my memory linked 1:1 @ 540.0 mhz.
The only voltage that is not on auto is CPU PLL, that is at 1.55volts.
CPU is running 8x multiplier.
Thank you very much for stepping up to the plate and creating the ISO of the Maximus DVD for me. :clap: :clap:Quote:
Originally Posted by Grnfinger
My pleasure:up:Quote:
Originally Posted by SiGfever
Glad to be able to help
Guys here is a little template for listing your settings when asking for assistance. I will do an Excel spreadsheet later so that you can track four-five different overclock settings at a time.
PHP Code:Ai Overclock Tuner: Manual
OC From CPU Level Up: Auto
Ratio CMOS Setting: 8.5
FSB Frequency: 375
CPU Clock Skew: Normal
NB Clock Skew: Normal
FSB Strap to North Bridge: Auto
DRAM Frequency: DDR2-999MHz
DRAM CLK Skew on Channel A1: Auto
DRAM CLK Skew on Channel A2: Auto
DRAM CLK Skew on Channel B1: Auto
DRAM CLK Skew on Channel B2: Auto
DRAM Timing Control: Manual
1st Information:
CAS# Latency: 5 DRAM Clocks
DRAM RAS# to CAS# Delay: 5 DRAM Clocks
DRAM RAS# Precharge: 5 DRAM Clocks
DRAM RAS# Activate to Precharge: 15 DRAM Clocks
RAS# to RAS# Delay: Auto
Row Refresh Recycle Time: 55 DRAM Clocks
Write Recovery Time: Auto
Read to Precharge Time: Auto
2nd Information:
Read to Write Delay (S/D): Auto
Write to Read Delay (S): Auto
Write to Read Delay (D): Auto
Read to Read Delay (S): Auto
Read to Read Delay (D): Auto
Write to Write Delay (S): Auto
Write to Write Delay (D): Auto
3rd Information:
Write to PRE Delay: Auto
Read to PRE Delay: Auto
PRE to PRE Delay: Auto
All PRE to ACT Delay: Auto
All PRE to REF Delay: Auto
DRAM Static Read Control: Disabled
DRAM Read Training: Enabled
MEM. OC Charger: Enabled
Ai Clock Twister: Moderate
Ai Transaction Booster: Manual
Common Performance Level: 12
Pull-in of CHA PH1: Disabled
Pull-in of CHA PH2: Disabled
Pull-in of CHA PH3: Disabled
Pull-in of CHB PH1: Disabled
Pull-in of CHB PH2: Disabled
Pull-in of CHB PH3: Disabled
PCIE Frequency: 101
CPU Voltage: 1.30
CPU PLL Voltage: 1.51325
FSB Termination Voltage: 1.11325
DRAM Voltage: 2.01200
North Bridge Voltage: 1.11325
South Bridge 1.5 Voltage: 1.51325
South Bridge 1.1 Voltage: 1.11325
CPU GTL Reference (0): Auto
CPU GTL Reference (1): Auto
CPU GTL Reference (2): Auto
CPU GTL Reference (3): Auto
NB GTL Reference: Auto
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto
CPU Configuration:
Ratio CMOS Setting: 8.5
C1E Support: Disabled
Max CPUID Value Limit: Disabled
Intel Virtualization Tech: Disabled
CPU TM Function: Disabled
Execute Disable Bit: Disabled
Load-Line Calibration: Enabled
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
can someone post bios setting to run 8 x 525 /530 stable ,need help here
this is mya setting failed in orthos blend at 15 minutes, need help
PHP Code:Ai Overclock Tuner: Manual
OC From CPU Level Up: Auto
Ratio CMOS Setting: 7
FSB Frequency: 500
CPU Clock Skew: Normal
NB Clock Skew: Normal
FSB Strap to North Bridge: Auto
DRAM Frequency: DDR2-999MHz
DRAM CLK Skew on Channel A1: Auto
DRAM CLK Skew on Channel A2: Auto
DRAM CLK Skew on Channel B1: Auto
DRAM CLK Skew on Channel B2: Auto
DRAM Timing Control: auto
DRAM Static Read Control: Disabled
DRAM Read Training: Disable
MEM. OC Charger: Enabled
Ai Clock Twister: Moderate
Ai Transaction Booster: auto
PCIE Frequency: 100
CPU Voltage: 1.325
CPU PLL Voltage: 1.5000
FSB Termination Voltage: 1.25
DRAM Voltage: 2.15
North Bridge Voltage: auto
South Bridge 1.5 Voltage: auto
South Bridge 1.1 Voltage: auto
CPU GTL Reference (0): Auto
CPU GTL Reference (1): Auto
CPU GTL Reference (2): Auto
CPU GTL Reference (3): Auto
NB GTL Reference: Auto
DDR2 ChA Reference Voltage: Auto
DDR2 ChB Reference Voltage: Auto
North Bridge DDR Reference: Auto
CPU Configuration:
Ratio CMOS Setting: 7
C1E Support: Disabled
Max CPUID Value Limit: Disabled
Intel Virtualization Tech: Disabled
CPU TM Function: Disabled
Execute Disable Bit: Disabled
Load-Line Calibration: Enabled
CPU Spread Spectrum: Disabled
PCIE Spread Spectrum: Disabled
I have 2 stable setups I will post after work today,Quote:
Originally Posted by SiGfever
3.825GHz
3.9GHz
Will post a 4.0GHz once I tweak some settings.
Have there been any significant clocks with a Q6600 with this board, or should i get a 94/9550???? :confused:
How will this board do to improve my overclock versus a P5K-E with a Q6600 @ 3.825GHz (9x425) @ 1.504v? Will the 16 Phase CPU Power improve things at all? I'm looking for something close to 4GHz Folding Stable...
need help i can pass orthos blend but when im trying 3dmark06 my pc always restart , please help
I'll toss my Q6700 in and run a few FSB tests for you if you like.Quote:
Originally Posted by kup
My Q9550 runs 3.825GHz MIIF @ 1.35v
Maximus X38 needed 1.35 for 3.6GHz if that helps you any.
You need to post your bios setup b4 anyone can help you, hard to make suggestions when there is nothing to look at.Quote:
Originally Posted by barong
Do the new BIOS 1307 improve OC ?
I canīt run more than 489 Mhz FSB run Bench Stable with my Q9550 (901 BIOS)
So only 4158 Mhz (@1,4vcore) are possible to run through WPrime1024 and 3DMark
Iīve got problems to get my Q9550 Prime Stable over 3825 Mhz and 450 Mhz FSB - but I can bench 4158 Mhz with 1,4V :(
I want 3950 Mhz with 1,275V - but after 2 Minutes Small FFT everytime one Core get out.
Voltages are:
VCore 1,275V
PLL: 1,5265
FSB: 1,17950
NB: 1,35V
GTLs Auto,
I tried a lot of GTL combinations, but nothing was sucesfull
GTL's are the key to stability on this board.Quote:
Originally Posted by Seewolf
I'messed around for while trying to get the chip stable, dialed in the correct GTL's and its rock solid.
I dont really see any difference with 1307 from 701 or 802 I do believe its to add more memory compatability.
High FSB and running GTL's on auto I doubt you will ever get 4.0 stable
Hey Grn let us know when you have a template for 4GHz stable. Do you even think its possible with a Q9450? I messed around with it a little bit more today and got it to 3933MHz but it only passes 8 out of 10 tests in linpack. :down:
Quote:
Originally Posted by Grnfinger
Grnfinger, is there a "easy" way to calculate the gtl's for the board, or do you need to be a "rocket scientist"???? :D
I am looking forward to this setup, I have a Q9550 also.Quote:
Originally Posted by Grnfinger
3.825GHz 10 loop Linpack and Prime 8 hours stable
Extreme Tweaker
Ai Overclock Tuner : Manual
OC From CPU Level Up : AUTO
CPU Ratio Control : Manual
- Ratio CMOS Setting : 8.5
FSB Frequency : 450
CPU Clock Skew : Normal
North Bridge Clock Skew : Normal
FSB Strap to North Bridge : 333
DRAM Frequency: DDR2-1081
Dram Clock Skew CH1 A1 : Advanced 300ps
DRAM Clock Skew CH1 A2 : Advanced 300ps
Dram Clock Skew CH1 B1 : Advanced 300ps
Dram Clock Skew CH1 B2 : Advanced 300ps
DRAM Timing Control: Manual
CAS# Latency : 5
RAS# to CAS# Delay : 5
RAS# Precharge : 5
RAS# ActivateTime : 15
RAS# to RAS# Delay : 3
Row Refresh Cycle Time : 55
Write Recovery Time : 6
Read to Precharge Time : 3
Read to Write Delay (S/D) : 8
Write to Read Delay (S) : 3
Write to Read Delay (D) : 5
Read to Read Delay (S) : 4
Read to Read Delay (D) : 6
Write to Write Delay (S) : 4
Write to Write Delay (D) : 6
Write to PRE Delay : 14
Read to PRE Delay : 5
PRE to PRE Delay : 1
ALL PRE to ACT Delay : 5
ALL PRE to REF Delay : 5
DRAM Static Read Control: Enabled
Dram Read Training : AUTO
MEM OC Charger : AUTO
Ai Clock Twister : Stronger
Transaction Booster : Manual
Common Performance Level [8]
Pull-In of CHA PH1 Disabled
Pull-In of CHA PH2 Disabled
Pull-In of CHA PH3 Disabled
Pull-In of CHA PH4 Disabled
Pull-In of CHA PH5 Disabled
Pull-In of CHB PH1 Disabled
Pull-In of CHB PH2 Disabled
Pull-In of CHB PH3 Disabled
Pull-In of CHB PH4 Disabled
Pull-In of CHB PH5 Disabled
PCIE Frequency : 101
CPU Voltage : 1.35
CPU PLL Voltage : 1.50
FSBT : 1.33850
DRAM Voltage : 2.12
North Bridge Voltage : 1.39150
South Bridge Voltage 1.5 : 1.5
South Bridge Voltage 1.1 : 1.1
3.9GHz Stable
Extreme Tweaker
Ai Overclock Tuner : Manual
OC From CPU Level Up : AUTO
CPU Ratio Control : Manual
- Ratio CMOS Setting : 8.5
FSB Frequency : 459
CPU Clock Skew : Normal
North Bridge Clock Skew : Normal
FSB Strap to North Bridge : 333
DRAM Frequency: DDR2-1103
Dram Clock Skew CH1 A1 : Advanced 300ps
DRAM Clock Skew CH1 A2 : Advanced 300ps
Dram Clock Skew CH1 B1 : Advanced 300ps
Dram Clock Skew CH1 B2 : Advanced 300ps
DRAM Timing Control: Manual
CAS# Latency : 5
RAS# to CAS# Delay : 5
RAS# Precharge : 5
RAS# ActivateTime : 15
RAS# to RAS# Delay : 3
Row Refresh Cycle Time : 55
Write Recovery Time : 6
Read to Precharge Time : 3
Read to Write Delay (S/D) : 8
Write to Read Delay (S) : 3
Write to Read Delay (D) : 5
Read to Read Delay (S) : 4
Read to Read Delay (D) : 6
Write to Write Delay (S) : 4
Write to Write Delay (D) : 6
Write to PRE Delay : 14
Read to PRE Delay : 5
PRE to PRE Delay : 1
ALL PRE to ACT Delay : 5
ALL PRE to REF Delay : 5
DRAM Static Read Control: Enabled
Dram Read Training : AUTO
MEM OC Charger : AUTO
Ai Clock Twister : Stronger
Transaction Booster : Manual
Common Performance Level [8]
Pull-In of CHA PH1 Disabled
Pull-In of CHA PH2 Disabled
Pull-In of CHA PH3 Disabled
Pull-In of CHA PH4 Disabled
Pull-In of CHA PH5 Disabled
Pull-In of CHB PH1 Disabled
Pull-In of CHB PH2 Disabled
Pull-In of CHB PH3 Disabled
Pull-In of CHB PH4 Disabled
Pull-In of CHB PH5 Disabled
PCIE Frequency : 101
CPU Voltage : 1.3875
CPU PLL Voltage : 1.53975
FSBT : 1.33850
DRAM Voltage : 2.1
North Bridge Voltage : 1.39150
South Bridge Voltage 1.5 : 1.5
South Bridge Voltage 1.1 : 1.1
CPU GTL Reference 0 : +30mv
CPU GTL Reference 1 : +20mv
CPU GTL Reference 2 : +20mv
CPU GTL Reference 3 : +30mv
North Bridge GTL Reference : AUTO
DDR2 Channel A REF Voltage : AUTO
DDR2 Channel B REF Voltage : AUTO
North Bridge DDR Reference : AUTO
Load Line Calabration : Enabled
CPU Sread Spectrum : Disabled
PCIE Spread Spectrum : Disabled
Some volts on 3.9 are a tad high, no tweaking time yet.
Will post a 4.0GHz stable setup later tonight, I have a Q6700 to test for kup first.
Cool. Cheers Grn!
your gtls need adjusting.Quote:
Originally Posted by electricl
your chip might do 4.0GHz depending on volts/temps.
what FSB / multi and current gtls?