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Just curious, maybe the Intel insiders can enlighten. :p: When will Intel finally catch up to GF and AMD on immersion lithography? Are they going to be able to impliment it for 32nm? AMD has had it since 45nm, I wonder if Intel are having trouble following their lead.
when is GF going to have strained silicon? immersion lithography is expensive.Quote:
Originally Posted by flippin_waffles
http://download.intel.com/pressroom/..._Bohr_32nm.pdfQuote:
Originally Posted by flippin_waffles
This is what I could find after a quick google -- page 7.
Don't confuse immersion lithography as a 'lead', immersion techniques is just that a new technique to enable printing the minimal size necessary. You get what you get, whether you print it with dry, immersion, or a hyperfine atomically sharp pencil, it doesn't matter -- it is simply a chosen technique to do what is necessary to meet the requirements. Immersion litho by itself does nothing to improve the performance of the device, it's just a printing technique.
I would think it is considered better engineering if you can make older lithography work as opposed to having to turn to something more complex. I think (and someone correct me if I am wrong), Intel used double patterning in 45 nm rather than try immersion.
GF (AMD) have used strained silicon since 90 nm.Quote:
Originally Posted by Chumbucket843
Strained silicon is in AMD CPUs ever since they rolled out 90nm products(and even some 130nm) :rolleyes: .Maybe read up before asking?Quote:
Originally Posted by Chumbucket843
Immersion litho is expensive and double pattering intel uses is not? Btw,intel will use immersion lithography for its 32nm hk node.
That's the: Let the journalists do the lying trick..:) more often used by Otellini..Quote:
Originally Posted by terrace215
(By journalists inadvertently omitting just the "little detail")
Journalists wrote for years that: "Intel will not implement 64 bit (in Prescott)"
They were "telling a lie", quoting Otellini but in fact, Otellini never said it,
there was always a "little detail" in the exact wording which they overlooked.
Moore's law doesn't need HKMG at 45nm but see how Otellini again likes
to play with the press: (In this case even good old Mike Magee got fooled)
Quote:
Originally Posted by Otellini
Regards, Hans
:) I would suspect is it a wash, think about it (I am sure you have thought it through, but for the benefit of others), double patterning means you have to send it through twice. To get the same output means double the equipment, so if immersion is over 2x more expensive then I suspect immersion would be more expensive, but if it is less than 2x more expensive (over a single pass dry) then double pass is more expensive... I don't know the answer to that one.Quote:
Originally Posted by informal
It should suffice to say, it is expensive.
Yeah I always assumed they were close when it comes to total cost. But without the data from both players we will never know which one is more expensive :).Quote:
Originally Posted by JumpingJack
Quote:
Originally Posted by JumpingJack
Oh you mean like making 45nm work withougt HKMG? Seems to me Intel was bloviating about how impossible it was without it, and AMD was so far behind without it. But like you say, it shows how leading edge AMD's engineering team is. Good point..
No correction needed :)Quote:
Originally Posted by JumpingJack
But I think it is worth noting Intel uses double-pattering only for selected features/layers of the die. I've read somewhere (most likely RWT, article by DK) that only 2 steps of printing layers require same step repeated.
I think you are missing my original point, immersion lithograghy is simply what AMD/IBM chose as the enabler for them, Intel re-engineered current techniques which was the enabler from their prespective.Quote:
Originally Posted by flippin_waffles
The real point is, it does not matter if you use immersion lithography, dry lithography double passed, or pre-printed toilet paper, what ever gets to the transistor density required of that node is what they do after weighing all the alternatives, economics, and time-to-market. Implementing immersion lithography at 45 nm for IBM/AMD did not give them any kind of a lead, they are still a year behind Intel bringing forward 45 nm, and will likely be at least that for 32 nm, immersion lithography did not do anything to close that gap. This is not debatable, it is simply a fact, AMD shipped their first 45 nm processor roughly 1 year after Intel. AMD will hit the cross over about 1 year after Intel.
This is not to take away from the engineering accomplishment of enabling 45 nm, it was a remarkable accomplishment. High-k has nothing to do with enabling printing 45 nm -- 1/2 pitch metal 1 lines, it has everything to do with enabling gate oxide scaling again, and creating better performance. Intel chose to get performance using this material at 45 nm, why? Because they figured out before anyone else how to make it work.
This is also not to take away from IBM/AMD engineering, they simply had to either make due with SiO2 or decided against putting resources toward a high-k process, therefore they had to engineer other ways to hit performance goals ... which obviously they did a good job, the 45 nm tech is 10x better than the 65 nm (a botched techology in my opinion).
I don't think amds 65nm was that bad,it just it didn't fit phenom.
Just look at the P4, especial at the 90nm ones. And then look at the P-M. Same process, different architectur with quite a huge difference.
Sure its important to have the right tools at the right time so you can design your process to fit your architectur, but if your whole architectur is botched not even the best process in the world can help you.
Also neither SOI nor HKMG is required to "enable" 45nm, its just that without this additions you can't achieve certain characteristics (e.g. power consumption (leakage), clock speed, transistor density etc.).
TSMC isn't using SOI or HKMG for ther 40nm (45nm) node at all, but you will have trouble if you wan't to produce a CPU on this process that has to reach the same characteristics the the CPUs form amd/intel.
Well, maybe botched is not such a good word, probably -- not the best foot foward -- they did have problems... it lowered power some, but they could not get the clockspeed up (Agena, Brisbane, or otherwise). Their L2 latency suffered a hit as well , though AMD claimed they were 'reserving' for future L2 expansion, it of course never came to pass. The L2 latency hit is probably a good clue, I think AMD ran smack dab into a problem with wire delay in the interconnect network as evidenced by the delay hit in L2 for Brisbane and timing issues on Phenom B2. Hence the concentration on ultra-low K for 45 nm -- and they delivered, that one innovation I think is why their 45 nm came out as good as it did (that, and getting it smack dab right on Deneb/Shanghai design).
EDIT. But you make a good point on the architectural implications. It is even evidenced in Lynnfield vs Nehalem, Nehalem chews alot of power, I was quite surprised actually, but same clock and turn off the QPI links and bing, you are back to Yorksfield power levels on a Nehalem platform (minus QPI). It is very difficult, if not impossible, to deconvolve the process contribution and circuit design to make good apples to apples compare. This is why you typically see the CV/I metric used to judge the capability of a process techology, independent of any architecture. The upshot is a great process will look crappy if the architecture is horrid (90 nm on Prescott for example), where as a great process can look just ugly without a great architecture.
Jack
well it wasn't bad, but it wasn't stellar...Quote:
Originally Posted by Hornet331
not sure, thik it was Hans who've pointed out that AMD cooperated with Motorola on their 90nm tech that proved to be awesome... for 65nm tech they've opted to cooperate with Chartered, and it was what it was... now with 45nm AMD is on board with IBM, and this tech rocks... 32nm and beyond is all done in coop with IBM, and their alliance!
BTW
if this come true, it'll be a bombshell: ARM goes arm2arm with GloFo:
http://www.tgdaily.com/content/view/44102/118/
Quote:
Originally Posted by Mike Magee
are you sure?Quote:
Originally Posted by Hans de Vries
i dont think mike would be that much out of the loop and fall for it that easily... there are many people out there who dont exactly call him a great guy, but everybody respects him for his ability to sort and filter information at a very high rate, boiling everything down to the information that matters within a blink of an eye :D
i think mike knew the catch and he wrote it on purpose to give amd a nudge :D
your comparing intel vs amd 65nm, not the same thing...Quote:
Originally Posted by Hornet331
i too agree that amd 65nm didnt really work very well for them... hard to tell if its mfc process or arch related... but if you consider that 65nm barely gave them any clockspeed headroom and barely dropped power compared to 90nm, at least the initial 65nm from amd seems to have not been working very well at all :)