AMD talks up its first Fusion chip

gpu does not connect by hypertransport.


http://www.theregister.co.uk/2010/02..._chip_preview/

Quote:

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According to Sam Naffziger, a senior fellow at AMD, the Llano chip will use a 32 nanometer silicon-on insulator process and will have an on-chip DDR3 main memory controller as well as four cores and a DirectX 11 compatible GPU on the die. Naffziger would not divulge the feeds and speeds of the graphics unit, but he said that the GPU is a derivative of the current Radeon HD5000 series and that it will not link to the cores through a HyperTransport link. Instead, it will use a more direct link on the die. The architectural specifics of that link are not being discussed today at ISSCC.

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Regor would be the closest thing to compare per/core performance to obviously.

Quote:

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Originally Posted by vietthanhpro

Hypertranport 3.1: 3.2Ghz
-> HyperTranport 4.0 : 6.4Ghz.:D

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Hi Vietthanpro,


I probably should have said 6.4 Gb/s (=HT3.1) anything above that
is speculation. I could believe higher speeds on a MCM (multi chip module)

There is a lot going on in the industry to get to higher serial
communication speeds. For instance some recent news:

Engineers explore life beyond 10 Gbit links
Designers rally around 25G, but next step still a mystery
http://www.eetimes.com/news/design/s...2700195&pgno=1

Altera to offer partial reconfiguration at 28-nm
28-Gbps transceivers, embed hard IP also on slate
http://www.eetimes.com/news/latest/s...leID=222600544

Regards, Hans

Quote:

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Originally Posted by Firestrider

is dual channel ddr3 going to be enough bandwidth for both the gpu and cpu?

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That's the big mystery question... How do they solve the bandwidth needs.
I somehow thrust the ATI engineers that they made sure that that's ok.

Maybe on a part of the die which hasn't been shown in public yet. or
maybe in cooperation with the DRAM industry + rival NVidia. It's possible
to put main memory in GDDR5 using TSV (Through Silicon Via's) die stacks.
Elpida is already supplying DDR3 TSV die stacks with 8 memory chips in a
package. The 9th chip is the interface chip which can in principle be
replaced by a GDDR5 interface chip.


Regards, Hans

Quote:

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Originally Posted by Hans de Vries

That's the big mystery question... How do they solve the bandwidth needs.
I somehow thrust the ATI engineers that they made sure that that's ok.

Maybe on a part of the die which hasn't been shown in public yet. or
maybe in cooperation with the DRAM industry + rival NVidia. It's possible
to put main memory in GDDR5 using TSV (Through Silicon Via's) die stacks.
Elpida is already supplying DDR3 TSV die stacks with 8 memory chips in a
package. The 9th chip is the interface chip which can in principle be
replaced by a GDDR5 interface chip.


Regards, Hans

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http://prohardver.hu/dl/upc/2010-01/...to_p.thumb.jpg

http://prohardver.hu/dl/upc/2010-01/...xm_1.thumb.jpg

128-bit, 512MB GDDR3 (E4690 MXM) :)

Is it possible that those "HT links" are single channel GDDR controllers?

Is the Fusion Memory Controller supposed to be implimented on Llano also, or just Bulldozer derivatives? I'm looking forwared to details on that FMC, but that info probably won't be released for a while.

Quote:

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Originally Posted by Hans de Vries

Later die pictures showed more GPU area so the die for so far is ~205mm^2

http://chip-architect.com/news/Llano_comp2.jpg

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Could you distinguish the HT ports from PCIe Lanes/ports ?
AMD earlier said that Fusion parts will come with PCIe Gen 2, only. So there should not be any Hypertransport at all.
http://xtreview.com/images/amd%20cguo%2002.jpg

There are also no NB chipsets mentioned in the table from above, only a SB part (Hudson).

Thus the ports that you named HT2 & HT3 are probably PCIe connectors that could be used for a dedicated graphic card (2x x8).
Another link will be probably used to connect to the southbridge, ATIs ALink is nothing more then a relabeled PCIe.

The last link could be used for anything else, PCIe x1 Slots, onboard chips, etc.

Furthermore the square die area below HT2 and HT3 and above HT4: Could that be the PCIe logic ?

cheers

Quote:

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Originally Posted by Opteron146

Could you distinguish the HT ports from PCIe Lanes/ports ?
AMD earlier said that Fusion parts will come with PCIe Gen 2, only. So there should not be any Hypertransport at all.
http://xtreview.com/images/amd%20cguo%2002.jpg

There are also no NB chipsets mentioned in the table from above, only a SB part (Hudson).

Thus the ports that you named HT2 & HT3 are probably PCIe connectors that could be used for a dedicated graphic card (2x x8).
Another link will be probably used to connect to the southbridge, ATIs ALink is nothing more then a relabeled PCIe.

The last link could be used for anything else, PCIe x1 Slots, onboard chips, etc.

Furthermore the square die area below HT2 and HT3 and above HT4: Could that be the PCIe logic ?

cheers

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You are right Opteron146 according to the presentation.
The PCIe lanes have moved from the chip-set to the CPU/GPU die.
The Llano compilation is already updated.


Regards, Hans

Did anyone see Flipp'n_Waff's response to Kyle...? lol hilarious.

Quote:

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Originally Posted by Hans de Vries

You are right Opteron146 according to the presentation.
The PCIe lanes have moved from the chip-set to the CPU/GPU die.
The Llano compilation is already updated.


Regards, Hans

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An even higher res Llano shot can be found at
http://www.pcgameshardware.de/aid,70...fikkarte/News/:
http://www.abload.de/img/amd-fusion-llano-vierk62mn.jpg
(Thanks to Opteron@Planet3dnow! for the copy - the same as Opteron146 here?)

This might be interesting for core comparisons, for example to find out, what this is (APM? more TLBs? or related to dynamic cache resizing?):

http://info.nuje.de/core_llano_compared.jpg.

Quote:

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Originally Posted by Dresdenboy

(Thanks to Opteron@Planet3dnow! for the copy - the same as Opteron146 here?)

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Klar, wer sonst :yepp: ;)

Quote:

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Originally Posted by Xoulz

Did anyone see Flipp'n_Waff's response to Kyle...? lol hilarious.

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lol omfg i just saw it lol, here is a link, check out the comments.


http://blogs.amd.com/fusion/2010/02/...ovation-isscc/

Kyle is just being his "natural" self... He just can't help making a fool of himself,even publicly in front of some AMD's VPs. :shakes:

Quote:

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Originally Posted by Dresdenboy

An even higher res Llano shot can be found at
http://www.pcgameshardware.de/aid,70...fikkarte/News/:
http://www.abload.de/img/amd-fusion-llano-vierk62mn.jpg
(Thanks to Opteron@Planet3dnow! for the copy - the same as Opteron146 here?)

This might be interesting for core comparisons, for example to find out, what this is (APM? more TLBs? or related to dynamic cache resizing?):

http://info.nuje.de/core_llano_compared.jpg.

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Nice find! There's one slightly bigger version over there:

http://www.pcgameshardware.de/screen...o-Vierkern.jpg

Regards, Hans

Quote:

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Originally Posted by god_43

lol omfg i just saw it lol, here is a link, check out the comments.


http://blogs.amd.com/fusion/2010/02/...ovation-isscc/

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it's funny that moderator closed one eye on Flippin's sincere advice :D

Quote:

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Originally Posted by Hans de Vries

Nice find! There's one slightly bigger version over there:

http://www.pcgameshardware.de/screen...o-Vierkern.jpg

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Haha, same error as over @P3D, there is just a small "No Deeplink" message.
But it seems that I got a downsized picture last time, or PCGH changed the pic in the meantime.

Anyways, here's the pic:
http://www.abload.de/img/amd-fusion-llano-vierkeeh0.jpg

@Dresdenboy:
I'll change it over at P3D, too.
One idea for the changed area: Maybe some changes in the cache controller, due to the 8T cache cells (K10 had 6T) ?

cheers

Alex

Amidst all this technical talk, can someone please explain whether or not the on-die GPU for Llano and other fusion products will benefit the average user who already has a GPU? If so, how? Will the CPU distribute workloads to the GPU? I've heard that GPU is better at calculating/computing certain jobs than CPUs (ie all that GPGPU stuff).

Well geez, I remember having a discussion with Kyle on [H], where his argument was that the Phenom II chip was a pile of crap and that the headroom for O/Cing was worthless because it never added any value to the chip and wouldn't help AMD sell any. It's not what customers wanted. How crazy is that, on an enthusiast website no less! And I especially liked his Eyefinity review where he had boxes and boxes of intel processors piled up in the backround in plain site. I'm sure that added some good advertising dollars. :D It's pretty clear which brand he prefers at the moment, but come on, still harping on the move from 45nm to 32nm for Bulldozer? How old is that. Anyway, I really didn't expect it would get approved. :D

BTW, I was reading the comments on Dresdenboy's blog. Any truth to that one about the much improved front end here?

Quote:

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Originally Posted by flippin_waffles

BTW, I was reading the comments on Dresdenboy's blog. Any truth to that one about the much improved front end here?

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I guess he was referring to the discussion @amdzone:
http://www.amdzone.com/phpbb3/viewto...0d27&start=500

No proof, just a patent.

Quote:

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Originally Posted by Opteron146

@Dresdenboy:
I'll change it over at P3D, too.
One idea for the changed area: Maybe some changes in the cache controller, due to the 8T cache cells (K10 had 6T) ?

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BTW, yesterday I looked for any reference to 8T cache cells in the reports and didn't find anything or overlooked it. IIRC, this subtopic has been announced for this ISSCC.

Quote:

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Originally Posted by Dresdenboy

BTW, yesterday I looked for any reference to 8T cache cells in the reports and didn't find anything or overlooked it. IIRC, this subtopic has been announced for this ISSCC.

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Yes, it was mentioned earlier in an eetimes article:

Quote:

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Much of AMD's paper will focus on circuit techniques the company is using to lower power consumption and leakage of the core. For example, the core's L1 cache uses 8T memory cells to support low supply voltages.

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http://www.eetimes.com/rss/showArtic...leID=221900830

I guess they just forgot that in the telephone conference. IMO, there are still no real ISSCC articles.

Quote:

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Originally Posted by Opteron146

@Dresdenboy:
I'll change it over at P3D, too.
One idea for the changed area: Maybe some changes in the cache controller, due to the 8T cache cells (K10 had 6T) ?

cheers

Alex

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Does 6T mean six transistors per cache cell? So Llano's cache might need more space for the same amount, but on the other hand need less energy?

P.S. Dann bist du wohl auch der Opteron der im Luxx sein "Unwesen" treibt, was? :P

Quote:

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Originally Posted by Oliverda

http://prohardver.hu/dl/upc/2010-01/...to_p.thumb.jpg

http://prohardver.hu/dl/upc/2010-01/...xm_1.thumb.jpg

128-bit, 512MB GDDR3 (E4690 MXM) :)

Is it possible that those "HT links" are single channel GDDR controllers?

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I would like to see Graphics GDDR5 memory in the package yes :^)
If they still hide some of the lower part of the die, then this may be
the reason. The extra memory interface would be very easy to spot.

The other solution, the better one in the long term, is to raise the
128 bit IMC to GDDR5 speeds. This would currently limit the main
memory size. Fermi will use up to 2GB per 128bit databus in the 2nd
half of this year. However, this could rapidly increase with the use
of TSV stacked dies. I guess 4GB to 8GB of GDDR5 main memory
would be enough for 2011.


Regards, Hans

Quote:

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Originally Posted by FischOderAal

Does 6T mean six transistors per cache cell? So Llano's cache might need more space for the same amount, but on the other hand need less energy?

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The blocks containing the L1 data and instruction cache are some 10%
wider relatively compared to the 45nm layout because of the larger 8T
cells. Intel uses 8T cells for the L1 caches at 32nm at well.

The extra room is used for the extra logic Mathias was talking about.


Regards, Hans

Charlie Demerjian has his Llano article up with a lot of new details:
http://www.semiaccurate.com/2010/02/...nm-llano-core/

My thoughts are here:
http://citavia.blog.de/2010/02/11/mo...tails-7987376/

There is still room for surprises.. ;)