AMD "Steamroller/Excavator" -info, speculations and experience

I dug out a Jaguar HC24 video presentation and posted it on AT forum. FUDzilla saw it so they re-posted it as news :D. But they cerdit me,sort of :P :

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We already reported that AMD plans to introduce E-series and X-series chips, with the X4 5110 pegged as the top quad-core SKU. It’s a 25W part manufactured in 28nm, but we still don’t know the clocks. Thanks to forum member over at Anandtech who unearthed an interesting Q&A video, we now have some official info. However, rather than answering any questions, the video raises a few new ones.

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some more little stuffs from internets on kabini...

http://wccftech.com/amds-flagship-es...faster-bobcat/

http://www.fudzilla.com/home/item/29...-hd-8000-cards

kaveri

http://www.fudzilla.com/home/item/29...2014-is-kaveri

ps this is from fudzilla lol ;)

Kaveri will show up in 2H 2013, Steamroller cores + GCN + HSA

Officially updated roadmap by AMD:
http://phx.corporate-ir.net/External...F8VHlwZT0z&t=1

http://cdn2.wccftech.com/wp-content/...13-roadmap.jpg

Any ideas when richland will show up in desktops?the stilt should know :D

there was only this one slide?...I hope, enthusiast desktop will be stil alive....

this is very interestig, thanks to Del422 from Czech forums for it....
http://www.evga.com/forums/tm.aspx?m...e=1&print=true

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Originally Posted by FlanK3r

this is very interestig, thanks to Del422 from Czech forums for it....
http://www.evga.com/forums/tm.aspx?m...e=1&print=true

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This man "seronx" Is everywhere

Interesting theory's that's for sure.

thats alot of extra PCI express lanes

AMD Kaveri sockets info - welcome FM3:
http://www.planet3dnow.de/vbulletin/...d.php?t=410680

Thanks FlanK3r for the info :up:

So Kaveri isn't fm2 compatible?

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Originally Posted by tbone8ty

So Kaveri isn't fm2 compatible?

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FM2 socket is already severely chocking on GPUs found in TN/RL, 2x 64-bit MCTs simply cannot provide enough bandwidth with DDR3.

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Originally Posted by The Stilt

FM2 socket is already severely chocking on GPUs found in TN/RL, 2x 64-bit MCTs simply cannot provide enough bandwidth with DDR3.

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oh RL richland seem you've had some new toy

Why does FX still have a crossbar ? :| it's ancient

Today some info about AMD Jaguar only...But very detailed :)
http://www.techpowerup.com/180394/AM...Quad-Core.html

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Originally Posted by FlanK3r

AMD Kaveri sockets info - welcome FM3:
http://www.planet3dnow.de/vbulletin/...d.php?t=410680

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So does that imply a new socket for steamroller or is the new socket needed because of the added gpu? time will tell I guess.

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Originally Posted by Darakian

So does that imply a new socket for steamroller or is the new socket needed because of the added gpu? time will tell I guess.

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Another question is if a socket am3+ version will be produced (no graphics). I can't imagine the server socket having the built in graphics. Maybe the enthusiast line will be merged with it.

Socket fm3 with 10 cores would be a nice bone.

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Originally Posted by trueblue

Another question is if a socket am3+ version will be produced (no graphics). I can't imagine the server socket having the built in graphics. Maybe the enthusiast line will be merged with it.

Socket fm3 with 10 cores would be a nice bone.

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If FM2 is any indication then fm3 will have at most half the cores of the high end desktop chip on whatever socket it ends up on. 10 cores on fm3 with a gpu would be pretty awesome though. I really just want to know if my am3+ system has any life left in it though.

http://tof.canardpc.com/view/b78f902...691f41922b.jpg

http://phx.corporate-ir.net/External...F8VHlwZT0z&t=1

Thanks to Gipsel from B3D

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Originally Posted by FlanK3r

this is very interestig, thanks to Del422 from Czech forums for it....
http://www.evga.com/forums/tm.aspx?m...e=1&print=true

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These circuitry blocks can be the same for PCI-E, UMI (link to southbridge) and DDI (digital display interfaces - DP and HDMI). They could very well serve other unknown purposes besides the most obvious.

Interesting
http://www.brightsideofnews.com/news...ets-gddr5.aspx

I can see this in lapto being a neat system.

I wanna see a ben heck ps4 laptop ;)

but PS4 is Jaguar core (kabini) and this is Kaveri (APU SR)

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Specifically the document lists 800 MHz QDR and 850MHz QDR (3200MHz and 3400MHz) clocks which would result with 51.2 GB/s and 54.4 GB/s of system memory bandwidth. Compared to current 25.6 GB/s with the DDR3-1600, this is quite the performance bump. The surprises don?t end there - Kaveri will support DDR3 up to 1250 MHz DDR (2500MHz) ? it specifically adds 2400MHz and 2500MHz modes over Trinity, which officially supported up to 2133MHz. Nevertheless GDDR5 would provide a tangible bandwidth improvement and might be the smarter choice given that DDR3 above 1866MHz starts to get prohibitively expensive.

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wow !! 50 GB/s vs 25 GB/s is awesome but isn't problem for cooling memory Chip ? because 50 GB/s is high and can releases so much heat.

Heat is not a problem with GDDR memory. Capacity is. Only 4GB max. is not much in 2013+.

There is good article from czech VIP user no-x:
http://translate.google.cz/translate...je-radic-gddr5

AMD Kaveri bear two memory controllers: DDR3 and GDDR5 - analysis

i can see it as a possibility as a stop gap solution until ddr4 becomes more widely available

heck AMD will have a 2 major players coding for it so why not

question is whats in the steambox?

Attachment 0

Recently, we exclusively unveiled that Kaveri, successor to the current "Trinity" high-end APU (Fusion A8 and A10 family) features a GDDR5 memory interface. This time we will talk about architectural enhancements of AMDs upcoming mainstream APU Kaveri as well as enhancements of the Steamroller cores which will also make their way into servers and high-end desktop systems in 2014. The information comes from a "Preliminary BIOS and Kernel Developer's Guide for AMD Family 15h Models 30h-3Fh Processors" (you can find a similar document here, dated January 2012) document, available to interested developers.

Store to load forwarding optimization
Dispatch and retire up to 2 stores per cycle
Improved memfile, from last 3 stores to last 8 stores, and allow tracking of dependent stack operations.
Load queue (LDQ) size increased to 48, from 44.
Store queue (STQ) size increased to 32, from 24.
Increase dispatch bandwidth to 8 INT ops per cycle (4 to each core), from 4 INT ops per cycle (4 to just 1 core). 4 ops per cycle per core remains unchanged.
Accelerate SYSCALL/SYSRET.
Increased L2 BTB size from 5K to 10K and from 8 to 16 banks.
Improved loop prediction.
Increase PFB from 8 to 16 entries; the 8 additional entries can be used either for prefetch or as a loop buffer.
Increase snoop tag throughput.
Change from 4 to 3 FP pipe stages.

http://www.brightsideofnews.com/news...-unveiled.aspx

And looks for 3CU/6C APUs! ( Or maybe 4CU/8C too?) Nice one, CPU with 2500 MHz DDR3 IMC, iGPU with GDDR5 (for the highest model). Im looking forward and for FX SR too :)

Flanker thanks for posting the relevant news mate :). I'm still reading it, looks interesting. Will comment later :)

edit:
Wow ,BSN found some massive gold mine of info,some of which he haven't seen before :).
What Flanker quoted above was unknown before.

The document lists the following changes to improve instructions per clock (IPC):

Store to load forwarding optimization <- big improvement(store handling sucked in BD/PD)
Dispatch and retire up to 2 stores per cycle <- same as above
Improved memfile, from last 3 stores to last 8 stores, and allow tracking of dependent stack operations. <-complements above
Load queue (LDQ) size increased to 48, from 44. <-solid improvement to load subsystem
Store queue (STQ) size increased to 32, from 24. <-complements above mem. store subsystem changes
Increase dispatch bandwidth to 8 INT ops per cycle (4 to each core), from 4 INT ops per cycle (4 to just 1 core). 4 ops per cycle per core remains unchanged. <-massive improvement in MT workload
Accelerate SYSCALL/SYSRET. <- I have no idea how much faster this change makes the syscall/sysret,probably noticeable improvement
Increased L2 BTB size from 5K to 10K and from 8 to 16 banks. <-solid improvement
Improved loop prediction. <- solid improvement (don't know how good though)
Increase PFB from 8 to 16 entries; the 8 additional entries can be used either for prefetch or as a loop buffer. <- prefetch was already solid in BD/PD, making it better cannot hurt
Increase snoop tag throughput. <-no clue
Change from 4 to 3 FP pipe stages. <- don't know what to think of this. It's listed as improvement so less stages is good(shorter pipeline usually means better IPC).

why dont they use ddr4; or gddr6? 3 and 5 are kind of old right now eh?

Ddr4 isn't exactly out yet, now will be when it launches, so that would make for some useless chips and boards. I'd think kaveri's successor will jump on the ddr4 wagon asap, probably with a new socket.
I'm hoping kaveri is offered on fm2, otherwise I will wait for ddr4 to upgrade. A 6 core apu sounds nice though...

i have a feeling SR will be AMD's comeback

GDDR5 will be ideal for iGPU. I heard, performance of this new iGPU will be as HD 7750, so very good. DDR3 have limited bandwith, with theoretical DDR4 will be the same at beginning (first DDR4 could have Broadwell in Q2/Q3 2014).
APU Kaveri will be very interesting, but what about Steamroller FX?:) Any news?

Good find Flanker and nice analysis informal :up:

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Originally Posted by informal

Increase dispatch bandwidth to 8 INT ops per cycle (4 to each core), from 4 INT ops per cycle (4 to just 1 core). 4 ops per cycle per core remains unchanged. <-massive improvement in MT workload

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Looks to me more like extracting additional inctruction-level parallelism, not thread-level parallelism.

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Originally Posted by informal

Change from 4 to 3 FP pipe stages. <- don't know what to think of this. It's listed as improvement so less stages is good(shorter pipeline usually means better IPC).

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Lower latency means same max theoretical IPC, but lower branch misprediction penalty, less waiting for the result of previous operations - should be a nice increase in real-world apps. Also this seems unusual - so far most architectures evolved from shorter to longer pipeline, not the other way.

About the memory controllers: I hope the MC can work in both modes (DDR3 and GDDR5) and selects one mode at boot, similar to how Deneb had DDR2/DDR3 controller. Another possibility is selecting modes during packaging (blowing on-chip fuses), in which case SKUs will be locked to one or other type of memory, probably GDDR5 for mobile and ULV chips and DDR3 for desktop. I hope it's the previous, but the latter seems more likely.

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Originally Posted by G.Foyle

Good find Flanker and nice analysis informal :up:


Looks to me more like extracting additional inctruction-level parallelism, not thread-level parallelism.

Lower latency means same max theoretical IPC, but lower branch misprediction penalty, less waiting for the result of previous operations - should be a nice increase in real-world apps. Also this seems unusual - so far most architectures evolved from shorter to longer pipeline, not the other way.

About the memory controllers: I hope the MC can work in both modes (DDR3 and GDDR5) and selects one mode at boot, similar to how Deneb had DDR2/DDR3 controller. Another possibility is selecting modes during packaging (blowing on-chip fuses), in which case SKUs will be locked to one or other type of memory, probably GDDR5 for mobile and ULV chips and DDR3 for desktop. I hope it's the previous, but the latter seems more likely.

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Yep I think that IMC will work in dual mode,just like graphics cards can work with cheaper DDR3 and GDDR5 :). AMD is doing the same thing with new Kaveri, the downside of this approach is somewhat more die area in the IMC department(and more complexity). As for FP unit and latency, you are probably right,but I wonder if BSN didn't just misunderstand the document(that we cannot see) in which AMD lists the changes in FP unit as "trimmed down" FlexFP with 3 pipelines(as they call it). What it basically says is that they axed one "MMX" pipeline(128bit) which was used for common SSE if I recall correctly,and they will use the other 2 FMACs to help the execution of those same ops now(this is my interpretation- SSE ops would therefore be executed on all 0-1-2 pipes instead of only pipes 2 and 3 as before) . Max. FP throughput would still be unchanged ,except for instruction latency changes of course, since only 2 128bit FMACs would be used for a total of 16 fp ops per cycle per module which is the same max. as PD(8 single prec. fp ops per FMAC when FMA is used).

Whatever the case is when it comes to FP, I have no doubt that it will be noticeably faster than PD is today. AMD lists some various numbers ranging from ~20% to 30%,which I think is in the line with the changes they made to the core. Add in the fact that we will have 3 module Kaveri as mainstream APU in Q4, it can easily be the case that 3M 3.8-4.2Ghz Kaveri will be on par with 4M 8350 in MT workloads and massively ahead in ST ones(~30%). This should be enough to invalidate the FX8xxx in the short term until the new FX9x comes,based on a 5M SR in 2014 (which is what I hope they will do since this is what the server segment will have in store ,a 5M ~3.5Ghz parts for single socket and 10M MCM 2.5-3Ghz parts for multisocket segment).

Great info's finally!

What an amazing upgrade this would be for those running 7700 cards and budget FX cpu's. A 2 for 1 :)

Initially much would hinge on drivers no doubt. No matter what sounds like tremendous bang for the buck! Great overall arch moving forward.

Some good newz here :

http://www.xtremesystems.org/forums/...-2013-XBitLabs

I believe, we will see SR FX later...Yes, good news +1 ,-)

3M/6T FM2 compatible Kaveri APUs branded as Opterons in 2013? :)

I think, we will see in 2014 classic AM4 socket or something bigger than FM2.

I've read Kaveri will support DDR4. Multiple sources say that there might be a new socket (FM3), but yeah, should still be compatible with FM2.

http://gamingio.com/2013/03/amd-kave...ry-controller/

Hot news from Ars technica concerning Kaveri.

http://arstechnica.com/information-t...ear-in-kaveri/

Fudzilla:

Chipmaker AMD is getting all enthusiastic over Heterogeneous Systems Architecture (HSA) as its cunning plan for the future.
Recently it has been talking to Ars Technica about something else dubbed "heterogeneous Uniform Memory Access" (hUMA) which is its take on HSA. HSA involves developing systems with multiple different kinds of processor, connected together and operating as peers. Normally it is CPUs and GPUs.

Armed with another set of acronyms AMD talks about splitting workloads between a CPU and a GPU, and the creation of a general purpose GPU (GPGPU). But a GPGPU is awkward for software developers, some of whom might think that GP stands for guinea pig and others are not happy that the CPU and GPU have their own pools of memory.

HUMA is AMD?s way around this problem. Using HUMA, the CPU and GPU share a single memory space and the GPU can directly access CPU memory addresses, allowing it to both read and write data that the CPU is also reading and writing. It is also cache coherent so the CPU and GPU will always see a consistent view of data in memory. If a processor makes a change then the other processor will see it.

We will first see HUMA in the chip codenamed Kaveri. It mixes up to three compute units using AMD's Bulldozer-derived Steamroller cores with a GPU. The GPU will have full access to system memory. It should be out in the second half of the year.
It appears likely that the chip AMD is designing for the PlayStation 4 later this year will also be a HSA system.



And...


-Much easier for programmers
-No need for special APIs
-Move CPU multi-core algorithms to the GPU without recoding for absence of coherency
-Allow finer grained data sharing than software coherency
-Implement coherency once in hardware, rather than N times in different software stacks
-Prevent hard to debug errors in application software
-Operating systems prefer hardware coherency - they do not want the bug reports to the platform
-Probe filters and directories will maintain power efficiency
-Full coherency opens the doors to single source, native and managed code programming for heterogeneous platforms
-Optimal architecture for heterogeneous computing on APUs and SOCs.

looks good for APU future systems.

Could it be soldered GDDR5 for notebooks and DDR3 DIMMs for Desktops? I don't believe RAM manufacturers will make a DIMM module just for one platform, that never went well on the past.

Also, can GDDR5 even be socketed on a DIMM? Just asking.

If you've kept yourself informed up to now, then no need to read the link by djohny. Nothing new.

No offense intended, just trying to save people some time.

Interesting info about next high performance chip. Thanks to yuri.cs from CZ forum for the link :)

http://www.rage3d.com/articles/hardware/amd_worldcast/

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Originally Posted by Andi64

Could it be soldered GDDR5 for notebooks and DDR3 DIMMs for Desktops? I don't believe RAM manufacturers will make a DIMM module just for one platform, that never went well on the past.

Also, can GDDR5 even be socketed on a DIMM? Just asking.

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AMD has their own memory now. I wouldn't be surprised if we saw Radeon branded GDDR5 DIMMs but I wouldn't expect it.

Kaveri will have significantly more memory bandwidth than any APU (or CPU with IGD) in the past.
How it is done? There is only one real way to do it.
Take a look at the memory prices and you're likely to figure it out.

The cost is not much higher (if any) and the high bandwidth will be available for the normal users too.
The solution should be good thru atleast couple of generations.

While GDDR5 would offer some serious bandwidth, it is not the most desirable solution for a desktop or notebook system as the memory might need to be expanded or replaced.

This is just pure speculation, of course.
;)

Im looking forward for SR FX, if it will be ready in Q1 2014, Il be shocked :)
http://www.hardwareluxx.de/community...or-955355.html

only the clocks seems very high....if is it true...

PS: nice joke :D
http://www.ocaholic.ch/modules/news/...p?storyid=6786

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Originally Posted by FlanK3r

PS: nice joke :D
http://www.ocaholic.ch/modules/news/...p?storyid=6786

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seems legit :rofl:

ASRock Crosshair VI Extreme :-D....Or HD 8970 dx11 :). I think, it is somethig from this hacking: http://www.hackingtricks.org/hacking...t-the-results/

Such high stock vcore looks funny too.

http://www.crucial.com/promo/DDR4.aspx

Excavator:
http://www.planet3dnow.de/photoplog/...hp?n=24314&w=o
http://www.planet3dnow.de/cgi-bin/ne...?id=1368122313

AMD today officially announced its China headquarters in Beijing Raycom Infotech Park and IEEE Bei ******* pter Excavator details of the specific architecture of the next generation. According to AMD's AMD AMD Excavator history of innovation largest architecture, the first of its the cluster modular architecture used since the inception of the bulldozer speculated that multi-threaded SPMT technology. In addition, the first comprehensive integration of the improved version of the next generation GCN Computer Unit, and reconfigurable technology arithmetic unit can be re-constitute in each CU 64 FMA can only support the Scalar Unit the four support 256bit AVX complex vector or eight 256bit Add / the MUL operation of the unit is directly connected to a module. At the same time, IEEE Bei ******* pter test results announced by AMD with the IEEE Society on a 28nm process Excavator processor Beta SPEC. Although only using the 28nm process, the frequency only 4G, but just a 4M8C4CU a simplified version, but its performance has been quite a lot
Speculated that the strong reconfigurable ability makes its application adaptability lead to high floating point performance reasons. Introduction of SpMT did not lead to the integer performance data have greatly improved, but we found very few relate to a large number of uncertain process integer on this processor performance even leading E3-1230 V2 9 times.

http://i.imgur.com/8wUzM6T.png

Speculated that multi-threading technology (Speculative Multithreading, SpMT) is developed speculatively execute multiple threads to thread-level parallelism, superscalar processor performance. By additional hardware units, such as thread synchronization unit (Thread Synchronization Unit, TSU), the thread context Sheet (Thread Context Table TCT) and thread memory history table (Thread Memory History, TMH), extends the transactional memory system to improve instruction set based on the wave scalar system the structure (the Wave Sealar ISA) to achieve WaveCache simulator's performance. It also proposed a new two thread-level transaction commit mechanism. Finally, six from the SPEC, Media and Mibench test procedures set true test procedures to assess speculated that the performance of multi-threaded WaveCache (SpMT WaveCache). The experiments show that the the SPMT WaveCache than 2 to 3 times the performance superscalar system structure is an effective method for the development of dynamic data flow computer performance


http://diybbs.zol.com.cn/11/11_106489.html

Thanks FlanK3r :up:

So Excavator is APU design only ?

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Originally Posted by Olivon

Thanks FlanK3r :up:

So Excavator is APU design only ?

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Yeah I think it is. For server parts it will feature more x86 "modules" but they might share the same GPU or we will just have one 4CU/8T/GCN "unit" as base unit and AMD will use it like lego for future server parts (gluing 3 or 4 of these on one die). Good news is that FINALLY the Fusion design is going to pay the due dividends.

In server then the GCN unit essentially becomes a "coprocessor" so to speak?

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Originally Posted by xVeinx

http://www.crucial.com/promo/DDR4.aspx

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DDR4 is quite pointless, unless they reach frequencies higher than DDR-3000.
According to Micron their DDR4 parts will operate up to DDR-2400 at the launch.
No doubt they will be much more expensive than DDR3 at that point.

Kaveri will require atleast DDR-2666 DRAM (in 2x 64-bit or 1x 128-bit configuration) in order to fully saturate the GPU, even at stock frequencies (estimated). Even at that speed, the memory bandwidth (MB/s per PPI) would be 20-70% lower than on AMD NI / SI discrete cards.

I would assume there is plenty of overclocking potential too, so the bandwidth would soon become a major issue again.
Raise the GPU frequency by 20% from the stock and you'll need ~DDR-3200 for the same MB/s per PPI.

In other hand... A 4x 64-bit / 2x 128-bit configuration would provide the same bandwidth at half of the frequency http://www.harley-davidsonforums.com...icon-think.gif

All of this is pure speculation of course ;)

yes, is long time for SR FX or Excavator...Maybe he thought DDR4 for Excavator. Btw, someone from AMD helped you or still not much good support :(? Dont give up with TCIK :(....

I meant for kaveri, actually. I'm no expert of such matters obviously :p:, but I thought that the timing of the release might coincide with products that actually used it. Kaveri has me intrigued; I'm still reading and trying to understand the arch however :).

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Originally Posted by xVeinx

http://www.crucial.com/promo/DDR4.aspx

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The DDR-4 chips sorting looks fun. It may look like it was impressive, but that's how current Quad Rank DDR-3 server modules looks like, here and here. I doubt you're going to see that in your regular Desktop machine.

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Originally Posted by FlanK3r

AMD today officially announced its China headquarters in Beijing Raycom Infotech Park and IEEE

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Officially launched at April 1st?

http://translate.google.com/translat...p%2F2244746760

Hans

haha, OMG.... :) So...back to reality :)

Nice find Hans :D

not all news are fake news..:)

one interesting (and seems legit) is here:
http://www.xtremesystems.org/forums/...-Devil-May-Cry

If that is Kaveri, that would make it the first public demonstration of it running on socket FM2. Something most only speculated on, and others claimed without disclosing a source (like me).

I don't know if they could make quad channel to work on existing FM2 motherboards, however if they can't it is game over for FM2 anyway. Obviously you cannot have GDDR5 on existing FM2 motherboards.

If Kaveri has a 512SP GPU operating at 800MHz, the PPI would be 409.6 (512 * (800/1000)).

The 7660D in Trinity, which has PPI of 307.2 (384 * (800/1000)) can already over saturate the memory bandwidth provided by the 2x 64-bit DRAM interface at DDR-2133.

HD 7970 GHz Edition = 133.9MB/s per PPI (288000 / 2150.4)
7660D / DDR-2133 = 111.1MB/s per PPI (34128 / 307.2).
7660D / DDR-2400 = 125MB/s per PPI (38400 / 307.2)
Kaveri / DDR-2133 = 83.3MB/s per PPI (34128 / 409.6).
Kaveri / DDR-2400 = 93.7MB/s per PPI (38400 / 409.6).

Even at DDR-2400 the GPU on Kaveri would be seriously bottle necked.
There is no other way out than using either GDDR5 for the GPU or 4x 64-bit (quad channel) DRAM.

As to GDDR5, that ability is geared to tech specific, or, embedded solutions (as pointed out in the article referenced by Flank3r). PS4 for instance. We truly yet to fully understand all the benefits of CPU and GPU sharing both physical and virtual memory, including bandwidth behaviors. But the GPU will likely always be the bottleneck for APUs, even with GDDR5. AMD would really have to gain some clout if they could force the market to make such a leap in memory standard.

Remember, while a new socket is certain, an upgrade path is important too. For many current Trinity owners, it's good for them to know there will be options should their current APU die. If they can't afford APU+MOBO+RAM, they can just get an APU, and later get MOBO+RAM.

For enthusiasts.... Newegg just listed the AMD A4-4000 Richland APU for $49.99USD shipped, $5 cheaper than the A4-5300 Trinity.
http://www.newegg.com/Product/Produc...82E16819113343

Motherboard FM2+ for Kaveri

http://wccftech.com/asus-shows-a88xm...kaveri-apus-2/

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Originally Posted by FlanK3r

Motherboard FM2+ for Kaveri

http://wccftech.com/asus-shows-a88xm...kaveri-apus-2/

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if you only could buy one :P

Can someone post the Steamroller die shots, with the comparisons shots too?

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Originally Posted by FlanK3r

Motherboard FM2+ for Kaveri

http://wccftech.com/asus-shows-a88xm...kaveri-apus-2/

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With exception of the new FM2+ socket, it looks identical the F2A85-M PRO. :p:

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According to the latest AMD server roadmap, there will not be a Steamroller based CPU with more than 4 cores and the high performance segment will only see a piledriver refresh code named Warsaw on 32nm with only benefit being lower power consumption.

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http://linustechtips.com/main/topic/...cpus-from-amd/

sad if true :(

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Originally Posted by Evantaur

http://linustechtips.com/main/topic/...cpus-from-amd/

sad if true :(

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if this is the prelude of shifting towards HUMA and compilers could really make use of APU, perhaps 4 SR cores could have the performance of FP in 8 or even 12 core Piledriver..?

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Originally Posted by Evantaur

http://linustechtips.com/main/topic/...cpus-from-amd/

sad if true :(

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Originally Posted by haylui

if this is the prelude of shifting towards HUMA and compilers could really make use of APU, perhaps 4 SR cores could have the performance of FP in 8 or even 12 core Piledriver..?

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I can't believe you both think that's true. (it's debunked in that link =| )

Those are Sever road maps.

honestly it looks like Steamroller will be out in desktop first for once instead of launching severs first like they've been doing.

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Originally Posted by demonkevy666

I can't believe you both think that's true. (it's debunked in that link =| )

Those are Sever road maps.

honestly it looks like Steamroller will be out in desktop first for once instead of launching severs first like they've been doing.

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Well, AMD always uses one die across the board.So it seems there will be no SR for AM3+,only desktop variants of these warsaw cores.
And yes SR will be first to desktop, but in kaveri form, so only 4 core APU for socket FM2.Thats disappointing .Well its intel time after AM3+ it seems, however if thats all true intel will do even less for even more in high end desktop :-/

Yes, its some server roadmap...I hope, SR FX still come in 2014, AMD must to see enthusiast of brand. Maybe only 1-2% of AMD people but we are the people who have choice between i5/i7 and AMD FX. And therefore we take FX...

If not, all this people will have only one choice for main PC. Intel i5/i7 :(. APU maybe as second PC

SR may well be APU only. We need more openCL apps for that to be a good thing.

http://www.techpowerup.com/187726/as...-fm2-apus.html

asus FM2+ mobo

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Originally Posted by tbone8ty

http://www.techpowerup.com/187726/as...-fm2-apus.html

asus FM2+ mobo

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http://www.asus.com/Motherboards/A88XMA/

They up on website too. I hope kaveri is indeed Q4/13 at latest.

It is "officially" delayed till 2014 now according to VR Zone who got hold of internal documents.,

http://wccftech.com/rumor-amd-phenom...-compatbility/

How this For a crazy fake amd cpu

yes, some bull*hit

so FM2+ still running dual channel ddr3? Dont see how we can expect big iGPU gains at higher resolutions without moving to quad channel ddr3 or ddr5. For the average user, its going to be way cheaper to buy a full set of 4 DDR1600 sticks then it is to buy 'botique' ddr2133+ sticks.

Is it possible to have quad-channel enabled on FM2+ chips, while retaining dual-channel on FM2 chips using the same motherboard? Speculating ofc.

i can see the kaveri fm2+ boards having pci-express x16 gddr5 memory boards...that be kinda cool if possible...

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Originally Posted by Miwo

so FM2+ still running dual channel ddr3? Dont see how we can expect big iGPU gains at higher resolutions without moving to quad channel ddr3 or ddr5. For the average user, its going to be way cheaper to buy a full set of 4 DDR1600 sticks then it is to buy 'botique' ddr2133+ sticks.

Is it possible to have quad-channel enabled on FM2+ chips, while retaining dual-channel on FM2 chips using the same motherboard? Speculating ofc.

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The IMC is on the APU so the motherboard it is not an issue.
Currently the DCTs are either configured to 1x 128-bit (ganged) or 2x 64-bit (unganged) mode.
So 1x 256-bit or 4x 64-bit is not an issue either ;)

Quote:

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Originally Posted by Miwo

so FM2+ still running dual channel ddr3? Dont see how we can expect big iGPU gains at higher resolutions without moving to quad channel ddr3 or ddr5. For the average user, its going to be way cheaper to buy a full set of 4 DDR1600 sticks then it is to buy 'botique' ddr2133+ sticks.

Is it possible to have quad-channel enabled on FM2+ chips, while retaining dual-channel on FM2 chips using the same motherboard? Speculating ofc.

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Quote:

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Originally Posted by The Stilt

The IMC is on the APU so the motherboard it is not an issue.
Currently the DCTs are either configured to 1x 128-bit (ganged) or 2x 64-bit (unganged) mode.
So 1x 256-bit or 4x 64-bit is not an issue either ;)

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Not to forget your recommendation stilt at muropaketti that pretty much confirmed quad channel (assuming you know it) :toast:

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Originally Posted by The Stilt

The IMC is on the APU so the motherboard it is not an issue.
Currently the DCTs are either configured to 1x 128-bit (ganged) or 2x 64-bit (unganged) mode.
So 1x 256-bit or 4x 64-bit is not an issue either ;)

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Boom! :D

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Originally Posted by The Stilt

So 1x 256-bit or 4x 64-bit is not an issue either ;)

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What do you think would be theoretically better for gaming? With one 256-bit interface we would have much higher bandwidth, but four 64-bit interfaces should technically give the same total bandwidth between them all and allow for a greater amount of memory requests by different things simultaneously right? but each individual request would be a bit slower?

Currently all of the AMD CPUs & APUs use 2x 64-bit (unganged) mode by default so I see no reason why it would change.
Unganged DCTs are more flexible and possibly could be powered down in low power states.

Ganging up the DCTs would reduce the congestion in certain rare scenarios.
In case of 4x 64-bit DCTs these scenarios will never occur due the monstrous bandwidth.
At DDR-1600 and above the bandwidth will never be fully saturated anyway.

If we assume that the SR will indeed feature a quad channel dram interface, of course ;)

For Quad Channel, I suppose you will need at least 128 more Pins for the bigger bus width, after all, the big switch from Socket 754 to 939 during 2004 was supposed to be just to get Dual Channel in. This amount remained pretty much the same during the last decade, even thorough FM2 also throws 16 PCIe Lanes too. I don't know a lot about pin budget, because most are supposed to be power and ground anyways, but I seriously doubt that they can fit Quad Channel in the current Socket (FM2+ included). If Steamroller were to get Quad Channel, I would suppose you should expect a new Socket (Which Kaveri isn't for). Either that, or they seriously overprovisioned on pins 10 years ago, if Kaveri manages to do it on FM2+.

Is there any chance SR will still use AM3+ ?
If that isn't the case I probably go grab a FX-8300 before Christmas as my AM3+ platform Final upgrade.

I would love to see APU w/6Core but looks like AMD won't be able to make one :(

If you count on any significant performance boost AMD must abandon AM3+ socket. Otherwise it will be another fail.

Wysłane z mojego GT-N7000 za pomocą Tapatalk 4

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Originally Posted by radier

If you count on any significant performance boost AMD must abandon AM3+ socket. Otherwise it will be another fail.

Wysłane z mojego GT-N7000 za pomocą Tapatalk 4

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On what basis. Its totally zero post if u dont base ur opinion in anything.

Every significant jump in performance of modern CPU's (Intel/AMD) was based on new platform.

Backward compatibility is a myth. If you buy CPU strong enough it will keep up for at least 3 years (vide C2D, SB). Buying :banana::banana::banana::banana:ty CPU and hoping for massive boost after upgrade to newer model over the same platform is a joke.

Wake up !

Quote:

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Originally Posted by radier

Every significant jump in performance of modern CPU's (Intel/AMD) was based on new platform.

Backward compatibility is a myth. If you buy CPU strong enough it will keep up for at least 3 years (vide C2D, SB). Buying :banana::banana::banana::banana:ty CPU and hoping for massive boost after upgrade to newer model over the same platform is a joke.

Wake up !

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Are you just trolling or what ?

Core 2 duo was on the same socket that had, Prescott,Cedar Mill Smithfield and Presler Pentium D. Before Core 2 duo was even made.

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Originally Posted by demonkevy666

Are you just trolling or what ?

Core 2 duo was on the same socket that had, Prescott,Cedar Mill Smithfield and Presler Pentium D. Before Core 2 duo was even made.

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Intel politic at that time was to force you to purchase a new Chipset for every new Processor release, so for Intel side guys you needed a new platform even if they shared the same Socket. Pentium D Smithfield required a new Chipset, it wasn't supported on earlier LGA 775 Pentium 4 Prescott Motherboards. So did Core 2 Duo, you needed yet another new LGA 775 Motherboard to use it, not Pentium D ones. If you look it that way, there is absolutely no difference if they share the same Socket if you ended up needing to purchase a new Processor and Motherboard together anyways. Only advantage was that at least Motherboards were backward compatible, so you could do a two-stage upgrade if you wanted to buy a new Motherboard Core 2 Duo compatible to use with your current Pentium 4/D THEN switch to a Conroe after saving more money.
Only AMD had Sockets that spawned several generations. Athlons XP Bartons were capable of booting and work even on 266 MHz Bus Socket A Motherboards without BIOS support. Socket 939 Dual Core K8 also were drop-in replacements to first generation Socket 939 Motherboards. Heck, even in Socket AM2, there were first generation Motherboards released before Barcelona that could even work with Phenom II X6 Thubans, and they did were capable of massive differences assuming you still were using a AM2 Dual Core K8. Backwards compatibility works, is just that few manufacturers would want that you can keep using the same Motherboard and put a new Processor because they need to spend money in BIOS devs to keep improving support yet they miss to sell new products. And both Intel and AMD are their partners. They also make and sell Chipsets to them, too, so the entire ecosystem is based on force you to change platform as often as possible, not single components.

@demonkevy666

Learn the difference between socket and platform. :rofl:

The majority of important performance things are in the CPU itself now anyway, so really the CPU is the platform. The chipset on the motherboard is pretty much just for I/O these days since memory controller, HT link bus, and PCI-E bus are all in the CPU.