Yea, I'm actually content with 3.2ghz on my E6400. I could probably push it a little higher with more voltage, but I just don't really want to run it balls out for 24\7 :p
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Yea, I'm actually content with 3.2ghz on my E6400. I could probably push it a little higher with more voltage, but I just don't really want to run it balls out for 24\7 :p
same here my E6300 is prime stable with high and medium fan speed at 3.6GHz but all i need out of 24/7 is 3.2Ghz..........that's plenty
My question, sorry if this has already been posted... how does the strap set in relation to the multi...
Meaning, say im running e6400 at 7x, 399fsb, am i still on the faster settings, OR, am i at the strap made for 400+ (unless i misunderstood FCG, the chipset should be running at 456 or so)...
What i mean, does the strap set for your FSB or NBCC.
Ah this info makes me feel better about crapping out at 424x8. I have Corsair 6400 (C5, the cheap stuff) and that's a 22mhz overclock at stock voltage (1.9.)
But from this I take it I should be able to boot into windows at 424...I got a big ol' BSOD even with a RAM voltage bump to 1.95. BTW, I leave SpeedStep enabled, as you can see...Doesn't make a bit of difference. Might as well leave it on and save some electricity.
Nice for cheap cooling - Arctic 7 Freezer Pro. And I can hit 3.2 on stock voltage (1.35 droop to 1.32).
http://img215.imageshack.us/img215/2...erclocklt8.jpg
sluzbenik you using this asus mobo?
your RAM maybe reaching the limit have you tried 2:3 divider on RAM to see how high it will reach
Yeah I have a p5b deluxe. I haven't played much with the dividers because they were so troublesome.
I actually just booted into 320x8 with 4:5 dividers, it seems stable, unlike the last BIOS. However when I set to 4:5 in BIOS and hit exit, it froze. I had to power off and unplugged to let Asus CPR do its thing but then it booted straight to Windows with the new ratio anyway...Strange.
Seems likely 422 is my max...Will bumping the voltage on these help? If i'd known I would be able to do 3.2ghz with stock vcore I woulda bought better RAM! I had no idea this chip would OC so well...
Trying to replicate or test out this but on P5W DH with E6700.Quote:
Originally Posted by Tony
I ran 1:1 with 4-4-4-10 timings for all tests.
Booted at the following 4 settings:
- @10x400fsb = 4000mhz
- @10x402fsb = 4020mhz
- @10x420fsb = 4200mhz
- @10x400fsb clockgen to 420.3fsb = 4203mhz
Ran Super Pi 32M and then in same windows session ran Everest Ultimate Edition v3.01 twice.
Super Pi v1.50 32M test
@10x400fsb = 4000mhz vs @10x402fsb = 4020mhz
http://fileshosts.com/intel/Asus/P5W...in22s359ms.png
vs
http://fileshosts.com/intel/Asus/P5W...in18s110ms.png
@10x420fsb = 4200mhz vs @10x400fsb clockgen to 420.3fsb = 4203mhz
http://fileshosts.com/intel/Asus/P5W...in45s578ms.png
vs
http://fileshosts.com/intel/Asus/P5W...in44s203ms.png
Everest Ultimate Edition v3.01
Ran each setting twice:
@10x400fsb = 4000mhz
http://fileshosts.com/intel/Asus/P5W..._bandwidth.jpghttp://fileshosts.com/intel/Asus/P5W...bandwidth2.jpg
@10x402fsb = 4020mhz
http://fileshosts.com/intel/Asus/P5W..._bandwidth.jpghttp://fileshosts.com/intel/Asus/P5W...bandwidth2.jpg
@10x420fsb = 4200mhz
http://fileshosts.com/intel/Asus/P5W..._bandwidth.jpghttp://fileshosts.com/intel/Asus/P5W...bandwidth2.jpg
@10x400fsb clockgen to 420.3fsb = 4203mhz
http://fileshosts.com/intel/Asus/P5W..._bandwidth.jpghttp://fileshosts.com/intel/Asus/P5W...bandwidth2.jpg
Not much difference, 4203mhz results probably slightly faster due to extra 3mhz clock compared to 4200mhz.
Maybe P5W DH has different points at which bootstrap changes and it ain't at 400fsb or 420fsb ?
eva the best way to find out quickly where the points are Tony and Kris are talking about is to basically boot to 1.65 memtest from say 300MHz in 10MHz increments and fix all the memory timings particularly TRAS & TRFC as they affect bandwith a lot and TRFC on DS3 was default auto in bios and some of the bandwith changes were enourmous until i realised what was causing this
anyway it would be interesting if you could do what i suggested
300MHz boot with memtest.....reported bandwidth
310
320
330
.....
460
(just memtest all the other testing would take 10xdays to complete lol)
same as all the other 965 mobo users......
Edited for OT content
guess that would be alot quicker too... brb :D
Memtest86+ v1.65 doesn't seem to show memory bandwidth it mistakes L2 cache bandwidth for memory bandwidth as i don't think this is correct
E6700
10x
390fsb = 25,519MB/s
400fsb = 26,172MB/s
430fsb = 28,106MB/s
440fsb = 28,759MB/s
450fsb = 29,412MB/s
460fsb = 30,064MB/s
could this bootstrap change somehow be bugging the p965 pci-e to 1x as opposed to 16x for most boards? because it only bugs after a certain fsb.. and it is starting to happen alot(or actually be noticed because it made no sense before) and it would be nice to select my bootstrap anyway because i obviously cant game well at 1x and 500+fsb....
and there she is....Quote:
Originally Posted by bachus_anonym
you're getting the tighter chipset latencies set at the lower 1066 strap while overclocking your NBCC to very high levels even at the next strap up (1333). the difference as you can see is incredible....43s for only a "10Mhz" delta. if we could do the same @ 427 you would be floored with the change! 427 may be possible when giving the NB a lot more volts...
-FCG
@Kris
I think its time we hit them with the excel spreadsheat of all the NBCC Vs CPU FSB etc, im sure it will answer a ton more questions.
@ALL
Its clear to me the 975 and 965 should act the same way, if the boards had similar bios files i actually think they would act just the same but obviously they don't. 965 seems to have increased overclocking headroom on the higher straps. You have already seen from Bachus post 10fsb difference with clockgen gains you a full 43'secs worth of speed which is nothing short of incredible, this means we would have seen close to 2 mins gain at 427 if his rig was stable ;)
AMD overclocking has us all working with 3 parameters, HHT, LDT and Ram speed, Intel is NO DIFFERENT, people who though it was should plainly see it is not now, also all those who complained they could not do 1:1 with OCZ (or other brand) memory you now know why, and all those who recieved an RMA count your self as real lucky, as which ever company who supplied your ram may not be giving RMA's now this info has gone live. You all need to learn the effects the chipset clock and latency has on the ability to overclock and work around it.
So the strap is set by the FSB and not the NBCC frequencies?Quote:
Originally Posted by freecableguy
The strap is set by the BSEL pins, this does not mean bios can not manipulate it though.
Quote:
Originally Posted by Tony
Yeah, from what this thread is saying the strap changes according to FSB, well what if you are running on a lower multiplier and fsb and nbcc are not equal, does the strap change when nbcc goes over 400 or when FSB goes over 400... Hope this question isnt too hard to understand, ill try and word it better if you need.
Quote:
Originally Posted by Revv23
I think the answer to this question is fairly obvious: the strap changes based on the NBCC, not the FSB.
How do we know this? Well, the NBCC is set when the system boots....when the default multiplier is detected, when the BSEL pins report the current default strap for the detected CPU, and when the currently selected multiplier (via BIOS) is set.
This in turn determines the correct strap for the NBCC which forces the setting of associated MCH latencies. The only other way to change the strap, insofar, once the system is running is to change the multiplier in Windows (CrystalCPU, C2MM, etc.). Simply changing the FSB (ClockGen, SetFSB, etc.) causes the FSB to increase - raising the overall NBCC overclock and raising final DDR2 speeds - but does not modify the strap/associated latencies.
Bachus has shown this simply by booting at 400FSB, entering windows and using ClockGen to change to 410FSB....he then achieved a 43 second drop in SPI 32m over booting straight in at 410FSB!
Since Bachus is using an E6600 with a multiplier of 8x:
(9/8)*400 = 450MHz NBCC w/400Mhz FSB (1066 strap?)
(9/8)*410 = ~461Mhz NBCC w/410MHz FSB (1333 strap?)
but...
(9/8)*400 = 450Mhz NBCC w/ClockGen to 410 FSB yielded the 43s drop in SPI 32m...
I think we can probably assume that one of the inflection points for setting the next higher strap on the Asus P5B Deluxe is in the 450 - 461MHz range.
-FCG
Quote:
Originally Posted by freecableguy
thank you for clearing this up for me. :toast:
Quote:
Originally Posted by freecableguy
hummm I tought that the strap change was occuring between 399 to 400, because there's a huge change when people using the default multi of the processor cross that limit...
so with an E6400:
8/8 = 1 x 399 = 399 NBCC
8/8 = 1 x 400 = 400 NBCC = strap change
EDIT: I see, probably there's a change in 399 to 400 and another change between 450-460... so everything is correct...
The strap on the MCH is changing at 400fsb, its being reset to the 1333 strap which should start at 333fsb but Asus choose to allow an overclock on the chipset all the way to 399fsb.
Once it hits 400 the chipset is strapped onto 1333 but its internal latency is locked to the 1066 strap. This makes 400fsb possible due to the lower NBCC with good memory performance. The only issuse is the NBCC is already higher due to 400fsb and not its base 333, so when using clockgen you are on the 1333 strap but with the tighter latency...memory performance is completely linear this way from 267fsb but you will struggle to get much over 410fsb it seems stable.
So this means with a lower NBCC we need an extra value in bios for the NB Latency which would allow for some quite spectacular memory performance but you would need to keep an eye on the NBCC as even a moderately high clock could dial in instability.
Ofcourse Asus could be real clevor with the next bios upgrade and change the strap at 333fsb instead of 400 but leave it on the 1067 latency all the way to 400fsb where they then just change the latency to the 1333 setting. It would give those wishing to use higher multipliers on the CPU an awesome injection of memory speed from ddr667 and up on 1:1.
T
@Tony & FCG,
Here's something for you guys to scratch your head over :)
I ditched 4:5 ratio and decided to go for 1:1. As you can see, I can Clockgen from 400MHz to 450MHz and beyond that. I should have known better, as 4:5 needs some work anyway. But results are very interesting, don't you think?
Code:
Boot @ below (DDR2-533 ratio, 1:1):
420x8 426x8 432x8 444x8 450x8
15:16.391 15:03.422 14:51.141 14:26.969 14:15.218
Code:
Boot @ 400x8 (DDR2-533 ratio, 1:1) and raised using ClockGen to:
420x8 426x8 432x8 444x8 450x8
15:27.062 15:12.750 15:00.031 14:34.296 14:24.125
UPDATE1: Another set added, booted at 375x8 and then raised:
Code:
Boot @ 375x8 (DDR2-533 ratio, 1:1) and raised using ClockGen to:
420x8 432x8 450x8
15:26.140 15:00.219 14:24.375
UPDATE2: ...one more set added, booted at 350x8 and then raised:
Code:
Boot @ 350x8 (DDR2-533 ratio, 1:1) and raised using ClockGen to:
420x8 432x8 450x8
15:26.172 15:00.547 System crashed!
No loss in performance here... Even more confusing, better with straight boot :confused:
One of my General conclusions is, that dropping multiplier below default appears to be not a good idea and one should aviod that. Higher NB strap or it's internal latencies at higher NBCC or whatever it is that happens, must really impair memory performance. Otherwise, I can't explain how 450x8 DDR2-900 8-3-3-3.0 can be slower than 400x9 DDR2-800 8-4-4-4.0 :confused:
Strange indeed...
This thread will answer many questions though! :up:
These are my findings. I believe that the 1333 strap is set at 380 mhz fsb if using the 1:1 ratio. The reason is if I set fsb to 380 or higher I get a double restart on the board. If I set it to 379 or lower it restarts normally. This is using bios 0614. Hope this helps.
Setting fsb to 379 or lower could be beneficial to people running water cooling so you don't have to worry about your pump double starting.
Maybe You check x7 multi ? egz 7x514 1:1 (or You Did it)Quote:
Originally Posted by bachus_anonym
Very strange mobo
My Bad Axe is simple :D
Strap 1067 and all work like it should (4:5 and 2:3 div too)
SETUP
9x440 from bios
http://simon.webideal.ca/Bench/9x440%2032m.JPG
9x440 (9x400 bios, 400 -> 440 clockgen)
http://simon.webideal.ca/Bench/9x440...20clockgen.JPG
Bachus, what happens when you boot at 399? It seems the higher strap is already applied at 400 1:1
hummm I dont understand now, for one guy (bachus_anonym) when using memo 1:1 it will act the same if using 440 from boot or clockgen, for the other guy (Supertim0r) with the memo at same 1:1 it works like we tought, much performance improvement when using 440 by clockgen... very strange... could you try setting 395 in the bios and repeating the test going to 440 with clockgen?
yeah, we had the same ideia at the same time :)Quote:
Originally Posted by Vapor
I think I did in my first post in this thread... Let me double check...Quote:
Originally Posted by yotomeczek
Quote:
Originally Posted by adamant415
I'm actually finishing 32M runs at 375MHz BOOT and raised to 420, 432, 450... I will update my post asap :)Quote:
Originally Posted by Vapor
UPDATE1: Another set added - Booted at 375x8 and then raised. I have updated my previous post for better comparison.
Code:
Boot @ 375x8 (DDR2-533 ratio, 1:1) and raised using ClockGen to:
420x8 432x8 450x8
15:26.140 15:00.219 14:24.375
UPDATE2: ...one more set added, booted at 350x8 and then raised. Again, I have updated my previous post for better comparison.
Code:
Boot @ 350x8 (DDR2-533 ratio, 1:1) and raised using ClockGen to:
420x8 432x8 450x8
15:26.172 15:00.547 System crashed!
As you can see, EXACTLY same thing as booted @ 400x8 and clockgen'd...
See, key seems to me a multiplier, as I mentioned above. I see the same behaviour at x9 as Supertim0r (advantage of booting at 400 and rasing then) but as soon as I drop multi to x8, the whole theory goes down the drain :(Quote:
Originally Posted by fscussel
you want a specific test ?
I haven't tested with different voltage than auto (vfsb, nb, sb, mch are all auto)
by the way, is there any basis for nbcc being (def mult/actual mult*fsb) besides sandra information?
did a quick test.. 1st part bootup speeds, 2nd part - multi changed to 6x.
http://alpha.frontier86.ee/~markku/975/sansan.jpg
bachus,Quote:
Originally Posted by bachus_anonym
This would make sense if the NBCC is, in fact, determined by the multiplier. If we see a strap change @ 400fsb with default multi. Then the NBCC changes strap at 400MHz. But since you are using a multi of 8, your NBCC is 400*9/8 = 450. We would expect to see the strap change at a NBCC of 400 = 9/8*FSB. This would mean a strap change around 355FSB.
Another thing. I could not replicate your results, bachus. Here were my findings:
Boot @ 450x8 1:1 4-4-4-10
32M results: 15:17.437
Boot @ 400x9 1:1 4-4-4-10
32M results: 14:57.297
Boot @ 400x8 Clockgen to 450x8 1:1 4-4-4-10
32M results: 14:37.469
Boot @ 350x8 Clockgen to 450x8 1:1 4-4-4-10
Hard Lock
Boot @ 350x8 Clockgen to 432x8 1:1 4-4-4-10
32M results: 15:10.xxx
Boot @ 350x8 Clockgen to 444x8 1:1 4-4-4-10
32M results: 14:49.078
Boot @ 355x8 Clockgen to 444x8 1:1 4-4-4-10
32M results: 14:50.469
... and @dr_sharpQuote:
Originally Posted by Supertim0r
Just curious, are you guys able to guys boot @ 400x9 (e.g. 4:5, not 1:1) and clockgen to around 445-450x9 without system locking up, instead of straight boot @ 445-450x9? Provided your CPU and RAM is up for 4GHz/DDR2-1120, naturally. I'm still on a stock cooler, and 3.65GHz is all I can bench at at this moment, so I can't try it myself yet...
Thanks :toast:
be nice if emc2 was still around i bet he would scope this out for us if you know what i mean.
My ram is up to par but my cpu max out around 430x9 :(Quote:
Originally Posted by bachus_anonym
I can't clockgen from 400, only boot 445x9 4:5Quote:
Originally Posted by bachus_anonym
Man, that sucks, if you can do 445x9 with 4:5 only with straight boot! :(
it freeze past 415ish clockgen
I can't find Youre 7x514 1:1 :confused:Quote:
Originally Posted by bachus_anonym
here you go, under EDIT part :), and yes, time sucked :(Quote:
Originally Posted by yotomeczek
Are you planning phase change soon :D ? You're waiting the 775 adapter ?Quote:
Originally Posted by bachus_anonym
I have an ideia, why don't someone write to ASUS and ask them about this, it would be easier. Dunno if they will answer tho...
here is something to try:
Anyone with a 6800XE and P5B deluxe try the folowing. Set the various downclock multipliers and see if the NBCC is altering. We have a feeling the 6800XE is a little different to normal Conroes in that each multiplier is a default multiplier, so it never overclocks the NB on a lower ratio.
Just theory...we need someone to test if they can.
T
Just a question i asked earlier, how to see the NBCC?Quote:
Originally Posted by Tony
but what about that :confused:
@ fcg: hey dude.... care to answer one doubt of mine?
(pic from hexux)
I see that they are running the X6800 @ 500 x 6.
So does it mean the NBCC is at
500 * 11/6 =~ 917 Mhz (x 4 = 3667 Mhz fsb :confused: )
Please clarify.
Regards,
Karan
ps: is the multiplier change of X6800 different? i am trying to go over the thread, please point me to the post if i have missed it.
kidoman - I believe that every multiplier on the X6800 is a "default" multiplier - you can raise FSB as high as you want while changing the multiplier and it never overclocks the NB (NBCC always equals the FSB). This is one of the subtle differences that XE chips possess.
i was wondering why my run was a bit slow >>>>Quote:
Originally Posted by bachus_anonym
your RUN with Conroe
http://www.clockmehigh.com/cooler/sc...4_32M_BOOT.png
MY RUN WITH ALLENDALE
http://img243.imageshack.us/img243/3...e6300esmy0.jpg
hmm this is interesting.....Quote:
Originally Posted by freecableguy
so to set FSB records, best would be a golden X6800 @ 6x.
I wonder when someone will pair that with a 965 C2 chip.
620 ~ 630 should be doable I guess.
- Kidoman
Probably memory timings. Same fsb and multi I get 15:20ish @ 5-5-5-15 and 15:00ish @ 4-4-4-10.Quote:
Originally Posted by dinos22
no you don't understand i am not directly comparing BA and my results as he has a conroe and i have an allendale.............i am saying that our scores are similar relative to those things.....................BUT the times should be much faster than what they are.........Quote:
Originally Posted by dr_sharp
OK, I get it LOLQuote:
Originally Posted by dinos22
...very great work!
It will interesting to compare a register dump at fsb:395 and other at fsb:405
Perhaps possible to find internal Latency with this...
thats the next task, ultimately we need the option in bios though really.
vozdraQuote:
Originally Posted by FELIX
if you tell us what you need exactly and how we can provide that do tell so that we can get cracking :D
yes for sure :toast: bigtoe modded ones are always special :)Quote:
Originally Posted by Tony
yeah wpcredit tweaks maybe? (is that the app or am i thinking of something else?)
Maybe this will be the birth of an 965 tweaker, it would sure help the cheap boards go far without having to depend on bios support...
well we've got FELIX involved so this is a VERY good sign :banana:Quote:
Originally Posted by Revv23
it's not sure for the result,but we can try... :)
So made 2 registers dumps (cpu-z->last table->register.txt),
one at fsb:398 and one at fsb:402, don't change other,and send it at :
memset@hotmail.fr
I have no time to see that this evening,but I try for tomorrow...
Nice finding so far guys :)
Let me ask something. Does this Latency Issue occurs on every i965 / i975 based motherboard?
Asus seem to go a very special in changing the strap on certain FSBs but what about the other motherboards like the P5W oder the Gigabye P965 ones?
Would be nice if someone could tell me somethign about it.
Done! Check your email, please.Quote:
Originally Posted by FELIX
Felix, you have another register dump from me.
if you need more help, I am always willing to do what I can.
Quote:
Originally Posted by Tony
Quote:
Originally Posted by freecableguy
Awesome info .... :toast: .
one question: when does the NBCC start to fail?? 2000mhz??
Quote:
Originally Posted by fscussel
I think that depends on strap settings, meaning NBCC could fail at 380fsb but work at 401 because of the more loose timings...
do we just do Regedit > File > Export?Quote:
Originally Posted by Kunaak
CPUZ about tab - Register Dump...Quote:
Originally Posted by dinos22
Standard:
Strap=1066
CPU=2660MHz
FSB=266MHz
Multi=10
NBCC=266MHz
On P5B FSB=333:
Strap=1066
CPU=3330MHz
FSB=333MHz
Multi=10
NBCC=333MHz
On P5B FSB=401:
Strap=1333
CPU=4010MHz
FSB=401MHz
Multi=10
NBCC=334MHz
Right?
And...
The CPU speed is dependant on FSB*Multi.
The NBCC is believed to be dependant on FSB speed and the relation of default and set multiplier.
But...
On the P5B: the NBCC changes when u hit 401MHz FSB. U fall back from 1066 strap to 1333 strap.
Would the attached formula be more complete or did I hit it totally wrong?
i think the original thought of NBCC = (def mult/set mult x FSB) is wrong because it's based currently only on sandra. which is bugged :)
to get to know real nbcc, you need to get hold of some intel nonpublic papers or measure clock externally somehow.
i have no idea how much such thing as a nb radiates but rf scanner could be used for some measuring :)
though it'll be most likely that at that range, it'll pick up only fsb freq..
caater the formula above your post should then do the trick
Wow, this is a great thread! Definitely needs to be sticky. And it would surely help to change the thread title to something broader. This is like cracking the secrets to Intel OCing, very breakthrough stuff. Great job guys!
This one is worth looking at too:
P5W64 booting a 6600 @ 6x multi @ 450FSB, and then clockgen to 500FSB. Hmmm....
Edit: The link would help... ;)
http://www.xtremesystems.org/forums/...d.php?t=115912
...I tried to find interestings registers in differents dumps
between fsb:398<->fsb:402,but a lot of registers change when
you apply this fsb values.So difficult to know what is good or no.
However,there are some common registers that change in this dumps
made by bachus_anonym and kunaak (965 chipset):
http://img239.imageshack.us/my.php?i...pbachusux2.jpg
http://img239.imageshack.us/my.php?i...pkunaakja9.jpg
For example register at offset 144 and 1F1...
but this register are "intel reserved" in datasheets,
and I don't know what they are.
I made a little soft that allow to edit the mchbar,
it's work on chipsets 865/875 and 9xx.
MemTweak.zip
It's run only in 32bits.
You can try to change these registers and other with this soft,
but warning,don't change anything,else it's possible crash...
Your first address must be (in left column) FED14000 for 9xx chipsets,and FECF0000 for 8xx.
...for info-timings on 865/875 chipset is at address FECF0060,
-timings on 915<->975 chipsets are at address FED14110 to 120 for channelA 190 to 1A0 for channelB
-timings on 965 chipsets are at address FED14250 to 290 for channelA
650 to 690 for channelB
...also you can change your values with pmem ,it's a little good soft
made by Franck (cpu-z author),it's run in 8,16 and 32 bits.
btw, i made some screens with p5w, bootup at 200 and 437, also equalized timings in memset to minimize different registers.. note that values marked in red are ones that change even when just refreshing.. so you can easily discard them. grab the screens here
by the way, what datasheets do you use? 975x datasheet don't even say where "intel reserved" bits are..
i hope i could be of help.
i'll also try to boot at 266 with hp3 on and will write down all registers that change.. and, of course, will try to modify them :)
though it could be that 975 and 965 are a bit different.. if timings are at diff adresses already :s
edit: nm, noticed in datasheet, that every memory range not mentioned is "intel reserved" :)
edit2: btw, FELIX, could You make a little adjustment to Your program?
Please expand the range to FED14FFF and make the data window also sizable so one could
take a screenshot of whole data.. would be very helpful if asking additional info from others.
thanks :)
...thank you for the screen :)
for edit2,I not the time to do that actually,and I'm not at home for 10 days,
but I'll probably integrate memtweak in memset in a next version,
and correct that in same time.
So I guess this is the reason why i can POST 385 fsb but not 390 fsb on p5wdh , although the last one is completely stable in windows via clockgen...
Very interesting thread :)
ok.. here are the results with various settings, p5wdh.
hope you can understand it :)
though i think i'm back at the beginning
only bits that indicated most likely strap, were uneditable.
if they aren't status bits there's big chance they are write once bits..
may I through in my 2 cents:
It is clear from your results so far that when booting at the default multi, the strap changes at 400 FSB (NBCC=400 also). When booting at 400 then ramping up using clockgen, things go bad at 420 say becuase of the tight timing even though the starp is 1333. We all agree on that AFAIK.
The confusion occured when Bacus_anonymous (sp) did his test with the E6600 booted at 350*8 (NBCC=394) and then clockgen up, he was able to do it without it locking up at ~360 fsb as would be expected.
We assumed that when he booted at 350*8 that Asus bois still applied the 1066 strap since NBCC is under 400. However note that, if this is the case he has actually booted in the very unstable zone (370-399). Which he did not report. And the fact that he kept ramping up using clockgen without a lockup at ~360 tells me this:
What if Asus originally designed the whole thing to change the strap at fsb 333 MHz irrespective of multiplier ratio, then they made the special case change of the 400 MHz limit only when runnig default multi. We assume that the BOIS actually calculates the equivalent FSB number (356) when booting to *8 vs *9, but maybe Asus just applies the standard intel 333 Frequency and changes the starp.
So when bacus_anonymous booted at 350 *8, he actually booted into the 1333 MHz strap and thus sailed with clockgen because the timing is relaxed to begin with? Does this make any sense?
Note: I do not own an Intel. I am a nooob, and hardly understand this stuff anyway. Just a thought I thought maybe I should share. Thanks.
That was an interesting read.
That might explain why some 965 3D benches were on par with 975 benches and some were not.
I can try to see if there is a difference in bw when going from 300Mhz FSB to approx 450 in case memtest works with my P5W.
Bacus if you dont mind, could you do a 01 run at both 410Mhz set in bios and 410 using clockgen?
Would be interesting to see if it makes any change.
I understand about 10% of this thread. Someone needs to dumb it down and just tell me what FSB to run. Currently im running an E6600 at 8x405.
FELIX, great work my friend, i dont have intel right now so i cant test for you, someone try it though!!!
If you are using a P5B\Deluxe, you will probably get better memory performance at 400mhz FSB instead of 405.Quote:
Originally Posted by bw31
Tried 399 and 401 set from bios. All ran after reboot on same timings. E6600 on asus P5B 0614. Times are almost same while using 7 or 8 multi but sandra stil reports less bandwidth on the 401 FSB tests.
9x399
http://img.photobucket.com/albums/v636/loc_oc/9x399.jpg
9x401
http://img.photobucket.com/albums/v636/loc_oc/9x401.jpg
8x399
http://img.photobucket.com/albums/v636/loc_oc/8x399.jpg
8x401
http://img.photobucket.com/albums/v636/loc_oc/8x401.jpg
7x399
http://img.photobucket.com/albums/v636/loc_oc/7x399.jpg
7x401
http://img.photobucket.com/albums/v636/loc_oc/7x401.jpg
It seems I got it wrong. Now that I have my Conroe setup I see that it's not the NBCC that is changing, it's only the internal latency when u hit a higher strap.Quote:
Originally Posted by wittekakker
nbcc is dependant on fsb and strap. most likely a strap change will force different internal timings on nb, but also its very likely that strap change forces new multiplier to nb, thus changing nbcc.Quote:
Originally Posted by wittekakker
just like cpu speed is multi x fsb :)
but without those intel nonpublic documents it's hard to make a conclusion..
though one could use a frequency scanner to get real nb core clock :)
If we compute the Ram Frequency as:Quote:
Originally Posted by caater
Ram_freq=2*FSB_freq*north_multi/mem_div
i think that north_multi and mem_div are coded at the offset C00h in this way:
the first 4 bits give mem_div:
1 (0001) -> mem_div=2
2 (0010) -> mem_div=3/2
3 (0011) -> mem_div=6/5
0 (0000) -> mem_div=1 *(not tested)
the other 4 bits give north_multi:
1 (0001) -> north_multi=3 (533 strap)
2 (0010) -> north_multi=2 (800 strap)
0 (0000) -> north_multi=3/2 (1066 strap)
3 (0011) -> north_multi=6/5?(if 1333 chipset strap can be applied)
Moreover, as you caater already concluded, the north_multi seems to be present at E08h offset also.
Note that i computed the northbridge freq through the relation:
FSB_freq*north_multi
unfortunately c00h seems to be only indicator and it doesn't change anything.
well, what it does, it fools cpu-z and other programs though..
try to modify its value.. 10-4:3 20-1:1 30-4:5 40-2:3
so validated cpu-z mem screens do not mean a thing without bandwidth test :rolleyes:
also can't modify last 4 bits..
ok ive got a p5b on the way lets see how it works out.
You are right, so maybe it's an indicator of north multi also, that is set up at E08h offset. The problem i don't see another register cell that is constant with mem_div.Quote:
Originally Posted by caater
oh there are lots of them.Quote:
Originally Posted by astaris
138h, 1B8h (both dword), indicates that there's something changed per channel.
208h (dword), also changes with mem ratio.
C18h changes with ratio and C1Ch too. dword.
and those registers - also intel reserved..
tbh, there was more changes, even major ones, but once i wrote down common registers, i discarded all others.
Uhm, these locations are not costant with mem_div, but with mem_ratio, whereQuote:
Originally Posted by caater
mem_ratio=mem_div/north_multi
I'm pretty sure that mem_div set upmem_ratio, because with a given strap, i.e. north_multi, you can have only 4 mem_ratio, so it's logical to set mem_ratio with the two variable you are free to set, i.e. north_multi and mem_div, but the only cell i can see is constant with mem_div is C00h (the higher bits).
according to The Stilt he is running at 1066 strap in this screenshot.......511MHz FSB
Quote:
Originally Posted by The Stilt
HIS ANSWERQuote:
Originally Posted by dinos22
Quote:
Originally Posted by The Stilt
anyone else able to replicate this?
Yep, this is correct :)
I tried it after I did vdimm & vmch mods. With up to 1.67vmch I managed to "clockgen" from 400x9 to 468x9 and run pifast as well. Result? Full 0.50s difference, compared to straight boot @ 468x9 :fact: After that, I kind of stopped investigating it further, but I might try again, with more vmch. But yes, it is confirmed, just a matter of how high you manage to go. Just a note, this is no-go at any other ratio than 1:1 :(
Does the 1333 strap kick in at 400 or 401mhz? Im planning to try and hit 400x9 (3.6ghz).
I would do the tests myself but im too lazy atm :p
I wanted to share my results which confirm what others are seeing.
Screen #1 - booted into Windows at 400FSB, then used SetFSB to move a little higher
Screen #2 - booted in Windows at 503FSB
http://img137.imageshack.us/img137/5303/32m4026uw3.jpg
http://img80.imageshack.us/img80/6541/32m503x8zw0.jpg
More than 30 seconds difference. 503X8 may look more impressive. But looks can be deceiving. This is one reason why I prefer to run with lower FSB and a tighter strap. By using 4:5 ratio, I get a boost from higher memory speed.
When I stay on the tighter strap, the P5B Dlx is just as fast as any 975X board, IMO.
Now of course, higher CPU speed will eventually compensate for higher latencies. But once you move to a looser strap, you are fighting an uphill battle.
Can you please compare this for me?:
7 x 400 1:1 4-4-4-12
7 x 500 1:1 4-4-4-12
I was just curious as to how my e6300es would improve with new mem.