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The question is can we damage something by setting extreme or wrong values of ITEM in our board (in GTLref equations)?
Also we know now that setting Vtt over Vcore is not the best idea ;)
THX
As many other people, I tend to understand the GTL parameter and how to set it, but at the same time I don't. :confused:
Currently, I've got my CPU and NB GTL+ values at 0.067 and I worked out the equation and it turns out it should 74mV, or the closest to thereof. Where would I set this? Or is it already set?
Btw, my VTT is at 1.303v.
Hm. FSB Vref perhaps?
From your sig, I see that you have a DFI. You set the GTLs differently. Unless you can find someone who has set up some detailed tables, its a real PITA. I finally took DFI's excel spreadsheet from their BIOS setting guide and created a sheet to interpolate between values to get what I want. And there're some mistakes in DFI's table that became apparent when I worked-out the interpolations. Try starting here: http://www.clunk.org.uk/forums/hardw...rboards-2.html
Cryptik!
This idea just crossed my mind while I was testing a 1Mhz FSB increase (478->479) to make sure it would be stable before changing in bios, and came up with this small experiment! Reason for testing, Raid5 on ICH9R is damn ficky, if you crash the system you can be up for a 5hr long array verification! Gah The ICH9R is horrible for Raid5 when it comes to rebuild/verify. Using 4x320Gb sata2 drives thought it would be fun to try out.
Check these linpack results out. I found them extremely interesting! What I think you'll find the most important is the variation in Gigaflops of processing done for the tests of the run. For 478MHz which I spent a good few hours fine tuning to perfection the processing work done for each problem are +-1GFlop of each other. Then I set the FSB only 2MHz higher and suddenly they are all out of whack! Seems like a fine example of how critical tuning the Vtt and GTL References can be. At 478MHz the performance appears to be right at the edge of peak performance, where as 480MHz it drops significantly.
See next post for methodology, data and results.
Apps used:
Intel Linpack Benchmark 10.1.0018 64bit Binary
SetFSB 2.8.15 (change FSB on the fly)
CPU-Z (to verify changes to FSB)
Goal:
To show variations in CPU average processing power as a result of CPU and NB GTL Reference voltage and Vtt (AGTL+ Logical High Termination Voltage) fine tuned for a specific Front Side Bus BCLK frequency.
To show the importance GTL Ref and Vtt values have for a small band of FSB BCLK frequencies and where the values go outside their tuned range.
Method:
Start with fine tuned values for 478MHz FSB BCLK and only make changes to FSB BCLK frequency through SetFSB App in Windows. No changes made to GTL Ref or Vtt, and system not rebooted for the duration of all tests so base values are constant.
Data:
Common Linpack Data for all runs.
Parameters are set to:
Number of tests : 2
Number of equations to solve (problem size) : 2000 14000
Leading dimension of array : 2008 14008
Number of trials to run : 6 4
Data alignment value (in Kbytes) : 4 4
Maximum memory requested that can be used = 1569180256, at the size = 14000
480MHz FSB Vtt & CPU/NB GTL Ref Fine Tuned for 478MHz
Current date/time: Tue Dec 16 20:42:57 2008
CPU frequency: 4.317 GHz
Number of CPUs: 4
Number of threads: 4
============= Timing linear equation system solver =================
Size LDA Align. Time(s) GFlops Residual Residual(norm)
2000 2008 4 0.153 34.9357 4.657913e-012 4.051814e-002
2000 2008 4 0.159 33.5925 4.657913e-012 4.051814e-002
2000 2008 4 0.306 17.4794 4.657913e-012 4.051814e-002
2000 2008 4 0.167 31.8933 4.657913e-012 4.051814e-002
2000 2008 4 0.198 26.9641 4.657913e-012 4.051814e-002
2000 2008 4 0.172 31.0537 4.657913e-012 4.051814e-002
14000 14008 4 47.447 38.5635 1.832709e-010 3.309677e-002
14000 14008 4 45.706 40.0328 1.832709e-010 3.309677e-002
14000 14008 4 47.151 38.8055 1.832709e-010 3.309677e-002
----------
479MHz FSB FSB Vtt & CPU/NB GTL Ref Fine Tuned for 478MHz
Current date/time: Tue Dec 16 20:59:07 2008
CPU frequency: 4.310 GHz
Number of CPUs: 4
Number of threads: 4
============= Timing linear equation system solver =================
Size LDA Align. Time(s) GFlops Residual Residual(norm)
2000 2008 4 0.153 35.0199 4.657913e-012 4.051814e-002
2000 2008 4 0.151 35.4635 4.657913e-012 4.051814e-002
2000 2008 4 0.153 34.9244 4.657913e-012 4.051814e-002
2000 2008 4 0.156 34.3377 4.657913e-012 4.051814e-002
2000 2008 4 0.167 31.9228 4.657913e-012 4.051814e-002
2000 2008 4 0.162 32.9649 4.657913e-012 4.051814e-002
14000 14008 4 41.460 44.1328 1.832709e-010 3.309677e-002
14000 14008 4 41.545 44.0422 1.832709e-010 3.309677e-002
14000 14008 4 41.439 44.1550 1.832709e-010 3.309677e-002
14000 14008 4 41.177 44.4351 1.832709e-010 3.309677e-002
Performance Summary (GFlops)
Size LDA Align. Average Maximal
2000 2008 4 34.1055 35.4635
14000 14008 4 44.1913 44.4351
----------
478MHz FSB Vtt & CPU/NB GTL Ref Fine Tuned for 478MHz
Current date/time: Tue Dec 16 20:47:36 2008
CPU frequency: 4.303 GHz
Number of CPUs: 4
Number of threads: 4
============= Timing linear equation system solver =================
Size LDA Align. Time(s) GFlops Residual Residual(norm)
2000 2008 4 0.153 34.8233 4.657913e-012 4.051814e-002
2000 2008 4 0.154 34.7176 4.657913e-012 4.051814e-002
2000 2008 4 0.153 34.8557 4.657913e-012 4.051814e-002
2000 2008 4 0.158 33.8543 4.657913e-012 4.051814e-002
2000 2008 4 0.161 33.2057 4.657913e-012 4.051814e-002
2000 2008 4 0.152 35.1761 4.657913e-012 4.051814e-002
14000 14008 4 41.286 44.3187 1.832709e-010 3.309677e-002
14000 14008 4 41.152 44.4622 1.832709e-010 3.309677e-002
14000 14008 4 41.205 44.4057 1.832709e-010 3.309677e-002
14000 14008 4 41.196 44.4150 1.832709e-010 3.309677e-002
Performance Summary (GFlops)
Size LDA Align. Average Maximal
2000 2008 4 34.4388 35.1761
14000 14008 4 44.4004 44.4622
----------
477MHz FSB Vtt and CPU/NB GTL Ref Fine Tuned for 478MHz
Current date/time: Tue Dec 16 21:04:53 2008
CPU frequency: 4.295 GHz
Number of CPUs: 4
Number of threads: 4
============= Timing linear equation system solver =================
Size LDA Align. Time(s) GFlops Residual Residual(norm)
2000 2008 4 0.155 34.3763 4.657913e-012 4.051814e-002
2000 2008 4 0.160 33.3560 4.657913e-012 4.051814e-002
2000 2008 4 0.164 32.5663 4.657913e-012 4.051814e-002
2000 2008 4 0.163 32.8286 4.657913e-012 4.051814e-002
2000 2008 4 0.158 33.8674 4.657913e-012 4.051814e-002
2000 2008 4 0.153 35.0250 4.657913e-012 4.051814e-002
14000 14008 4 43.229 42.3267 1.832709e-010 3.309677e-002
14000 14008 4 43.619 41.9483 1.832709e-010 3.309677e-002
14000 14008 4 43.038 42.5139 1.832709e-010 3.309677e-002
14000 14008 4 41.981 43.5841 1.832709e-010 3.309677e-002
Performance Summary (GFlops)
Size LDA Align. Average Maximal
2000 2008 4 33.6699 35.0250
14000 14008 4 42.5933 43.5841
----------
476MHz FSB Vtt and CPU/NB GTL Ref Fine Tuned for 478MHz
Current date/time: Tue Dec 16 21:09:24 2008
CPU frequency: 4.288 GHz
Number of CPUs: 4
Number of threads: 4
============= Timing linear equation system solver =================
Size LDA Align. Time(s) GFlops Residual Residual(norm)
2000 2008 4 0.152 35.0469 4.657913e-012 4.051814e-002
2000 2008 4 0.190 28.0832 4.657913e-012 4.051814e-002
2000 2008 4 0.151 35.3378 4.657913e-012 4.051814e-002
2000 2008 4 0.152 35.0894 4.657913e-012 4.051814e-002
2000 2008 4 0.156 34.1345 4.657913e-012 4.051814e-002
2000 2008 4 0.151 35.3888 4.657913e-012 4.051814e-002
14000 14008 4 41.073 44.5480 1.832709e-010 3.309677e-002
14000 14008 4 41.429 44.1658 1.832709e-010 3.309677e-002
14000 14008 4 41.225 44.3841 1.832709e-010 3.309677e-002
14000 14008 4 42.916 42.6351 1.832709e-010 3.309677e-002
Performance Summary (GFlops)
Size LDA Align. Average Maximal
2000 2008 4 33.8468 35.3888
14000 14008 4 43.9332 44.5480
----------
475MHz FSB Vtt and CPU/NB GTL Ref Fine Tuned for 478MHz
Current date/time: Tue Dec 16 21:17:05 2008
CPU frequency: 4.274 GHz
Number of CPUs: 4
Number of threads: 4
============= Timing linear equation system solver =================
Size LDA Align. Time(s) GFlops Residual Residual(norm)
2000 2008 4 0.157 33.9416 4.657913e-012 4.051814e-002
2000 2008 4 0.154 34.7686 4.657913e-012 4.051814e-002
2000 2008 4 0.153 34.9108 4.657913e-012 4.051814e-002
2000 2008 4 0.155 34.4649 4.657913e-012 4.051814e-002
2000 2008 4 0.154 34.7279 4.657913e-012 4.051814e-002
2000 2008 4 0.153 34.9343 4.657913e-012 4.051814e-002
14000 14008 4 42.058 43.5045 1.832709e-010 3.309677e-002
14000 14008 4 41.602 43.9819 1.832709e-010 3.309677e-002
14000 14008 4 42.059 43.5038 1.832709e-010 3.309677e-002
14000 14008 4 41.546 44.0413 1.832709e-010 3.309677e-002
Performance Summary (GFlops)
Size LDA Align. Average Maximal
2000 2008 4 34.6247 34.9343
14000 14008 4 43.7579 44.0413
----------
Results:
To come.
I'll try and graph this up in excel to show a trend and simplify the data collected!
Apps used:
Intel Linpack Benchmark 10.1.0018 64bit Binary
SetFSB 2.8.15 (change FSB on the fly)
CPU-Z (to verify changes to FSB)
Goal:
To show variations in CPU average processing power as a result of CPU and NB GTL Reference voltage and Vtt (AGTL+ Logical High Termination Voltage) fine tuned for a specific Front Side Bus BCLK frequency.
To show the importance GTL Ref and Vtt values have for a small band of FSB BCLK frequencies and where the values go outside their tuned range.
Method:
Start with fine tuned values for 478MHz FSB BCLK and only make changes to FSB BCLK frequency through SetFSB App in Windows. No changes made to GTL Ref or Vtt, and system not rebooted for the duration of all tests so base values are constant.
Results:
To come.
Edit: Argh hard locked the system and now Raid5 array in verify state. Will add more FSB runs once it's done. So probably tomorrow at best. Should have disabled write-back caching before I started.
That is incredibly interesting! Nice find noticing that. Very strange how it seems absolutely spot on at 478 MHz, then becoming increasingly inconsistent slightly below and above that point and even decreasing despite the increase in FSB! 476 MHz and 480 MHz look to be the most affected. Were those Gflops readings reproducible in a consistent fashion upon re-running? How accurate do you think Linpack is in terms of processing work quantification? I guess so long as it's consistent it need not be accurate per se, as its just comparison of settings relative to each other.
Perhaps this may be shown through further testing to be the most suitable method to fine tune GTL Ref settings for specific FSB & clocks, beyond simply using them for gaining raw stability. I will also look into this in the next couple of days.
Sorry to hear about your raid array, 5 hours verification must be painful.
Quote:
Originally Posted by mikeyakame
yep i can get the same results within 0.1-0.2glfop consistently. if i change even Vcc or Vnb one notch it upsets it also! The variation should be very small if its setup correctly! I know when there is something out, i'll get anywhere from 35-42gflop across the 4 tests, thats how I figured out a way to use it for fine tuning. Near perfect gtl and voltages gives near perfect consistency and output, kinda like an engine thats balanced and works on very tight tolerances it'll perform the same day to day without a hitch.
I noticed a similar variation when searching for the correct GTLs. It didn't occur to me to try to use it for tuning!
So, you're suggesting that for a specific set of voltages, the GTLs that give me that max GFLOPs/min Times in LinPak (over several trials -- I usually run 15 before switching to prime95) is the sweet spot? That I should tune for that? See if it's stable and if not, move on?
Now that you mentioned this sweetspot and GTL's doing changes on Gflops here some old pics that i have stored.
http://www.aijaa.com/img/b/00813/3264988.jpg
and now today whit 0.635x GTL's
http://www.aijaa.com/img/b/00134/3264994.jpg
yeah you should be able to ;) just make sure you use the same problem size for all tests. you can use two different ones, ie like I do, small problem and large problem, just as long as the config is consistent for all the testing runs.Quote:
Originally Posted by davidk21770
That's how I've always tuned GTL for unknown FSBs heh I just figured others realized the same! I guess it's not as obvious as it looks to me!
Gives me a good idea, and usually if you get it right in Linpack..Prime95 should pass with flying colours provided you haven't hit an FSB Wall on the chip! Usually Linpack picks up the Wall before Prime anyway...nothing says wall more than a hard system lock that can't be tuned around!
Quote:
Originally Posted by mikeyakame
:up: I never thought of doing this! Thank you for that. Have not adjusted my Cpu GTL's this way but I just adjusted my NB GTL from .650 to .655 and shaved my time off about .19 and Gflops went up .21.Nice :)
Larry
I have noticed the variation in work throughput and noticed when I had the GTL Refs spot on that the Gflops were very similar within a run, but by the time I noticed I had my system tuned almost perfectly. It's probably a good idea to use this in addition to other methods to get the GTL Refs tuned for the particular FSB.
Quote:
Originally Posted by mikeyakame
I've found the more accurate linpack results are and smaller mean overall it reflects in all the system behaviour. Everything just seems to work in a smoother fashion which would be explained by the CPU being able to maximize its throughput efficiently.
Other thing I find is if the work output is say 35gflop at same freq cause the clock waves are out of whack, the peak temp on any core in linpack will generally be 10c+ lower by the end. After 4 runs with 1.6gb problems on the 64bit binary, I see a couple of cores hit ~81c when its running smooth.
Other thing is in Vista you need to make sure that with Linpack running there is no more than 80% memory usage or it'll start swapping out and screw up the results!
hi folks, i've a trouble with some GTLs
i've correctly settled my 1/3 GTLs (vFSB 1.25 x 0.635 = 0.793) - (vFSB 1.25 x 0.667 = 0.833) = -0.040mV but if i only touch the 0/2 GTL (now on AUTO) i can't boot ...
now i'm running 4500mhz (450 fsb, 1.54 vPLL, 1.25 vCC, 1.40 vNB, 1.25 vFSB - SB @ default) onto my MIIF ... and passed Linpack successfully ...
someone can give me a tip about those GTLs?
TIA (and merry xamas!)
any settings for the 780i with q9450 around 3,6-3,8 ghz
got new 780i board and old settings cant keep me running for more than 20 min
cpuv 1.5 yes i tried less but last board needed 1.5vcore new one is as stable 20min @ 1.38 as it is with @ 1.52 no v-drop pencile mode yet
vtt 1.3 1.2 wount chanfe the fail time
ddr 2.1
nb 1.4 tried 1.45 to 1.3
sb 1.5 @ stock tried up to 1.6
nb to sb 1.30 stock is 1.2 but it never matters unless it is above 1.4
lane 0 +.45 ive messed with these settings for 2 days with no love other than this gives me 20 ish minutes and every thing else is respectivley worse
lane 1 +.45
lane 2 +.05
lane 3 +.05
Hi Kurtz,Quote:
Originally Posted by KURTZ
With you vtt I would start with 10/-30/10/-30 which gives you almost perfect 0.8v on all GTLs and then you can go up.
From my experience this board (at least mine) really likes High GTLs from bracket 0.9v and up to 0.98v.
If you want to aim for GTL refs like this try 100/70/100/70 for 0.9 and work your way up - you might be surprised when you will find that you got best results with >0.95v ...
If you want to try 0.95v then settings are 150/110/150/110 or 150/120/150/120 (for me best results yield setting when 1/3 are a bit higher then 0/2 - I am talking about actual gtlrefs values not settings for them in bios)
Cheers - dont be affraid of high numbers they are all in spec of CPU and MB - the lower vtt the higher correction numbers and your vtt is vlow in compare to quads i. e.
thx mate, your post is really clear :)Quote:
Originally Posted by seban
however i've another question about the NB GTL:
the formula is the same than the other (vFSB x 0.64 = result - in that case 0.768) so i need to set the NB GTL like the GTL 0/2 or the GTL 1/3 correct? so if i follow your example and i want to put ALL my GTL to 0.8v i need to set +34mV onto the NB GTL correct?
TIA and merry xamas!
No problem m8 glad I can help.Quote:
Originally Posted by KURTZ
Well some time ago I was also wondering if I should set (just as you my friend) same GTL NB value as I am using for CPU GTL but I am not sure if it does the trick.
When I was tweaking NB GLT for the very first time I just set it to the same value as CPU GTL (I was at about 0.9v for CPU so I did same thing for NB) but it did not work. So I was just upping gradually NB GTL and stoped at one which gave me best resoults which was +60 at my vtt at that time in the past.
Then I fine tuned CPU GTLrefs. In the end CPU GTLrefs after fine tuning are almost the same as NBGTL ref which is working for me - so it looks like there is a correlation but also it might be just a coincidence.
I was lucky enough that I had problem that was solved by fine tuning NB GTL ref so I knew exactly when I set it to correct value.
If you want to have same effect just downgrade you vNB from your stable one by 2-3 notches to make it not stable and than fine tune NBtlref so you should see when it gets stable again and which NBGtl values is working for you.
K back to supper :)
You are going to have to drop the clock to where you are stable (eg: 3.4GHz) and slowly work up. Each board can behave quite differently from the last, even though the are the same model. There is no way you should need 1.5 vcore for those clocks, drop it to around 1.4v, Vtt 1.3v, vPLL 1.55v, and get it stable at lower clocks then work up. Each time it gets unstable after a small increase, work out what is required for it to be stable.Quote:
Originally Posted by billdavis
In your previous post I think you've got the GTL Refs around the wrong way. GTL Ref 0 & 2 = 0.635x and 1 & 3 = 0.67x.Quote:
Originally Posted by KURTZ
So your settings should look something like this for example:
GTL Ref 0 = +50mv
GTL Ref 1 = +10mv
GTL Ref 2 = +50mv
GTL Ref 3 = +10mv
Your NB GTL Ref has nothing to do with the CPU GTL Refs. The NB is a separate chip and needs it's GTL Ref set for whatever it specifically needs. For the M2F this is usually between -50mv and +60mv.
yes Cryptik but you told me that if i want i can change the 1/3 gtls or the 0/2 gtls ...
so i can put this settings:
GTL Ref 0 = +30mv
GTL Ref 1 = -10mv
GTL Ref 2 = +30mv
GTL Ref 3 = -10mv
cause i've the same result ... correct?
Yes that's fine, I just misunderstood one of your previous posts :) Very nice result you got btw.Quote:
Originally Posted by KURTZ
no mate, it's my poor english ... :) however thanks :)
Cryp,
Want to edit the first post and put a note about the naming and meaning of the CPU gtl ref land pin assignment names. Seems lot of people confused by their actual meaning and setting them in wrong context.
Something like this maybe.
CPU GTL Reference (0/2 Lane0/Lane2)
GTL Reference Data Strobe Input Buffer Middle/End Landing Pins 0 & 2. (GTLREF0/GTLREF2)
CPU GTL Reference (1/3 Lane1/Lane3)
GTL Reference Address Strobe Input Buffer Middle/End Landing Pins 1 & 3 ( GTLREF1/GTLREF3 )
For quad-core multi-die chips.
Middle Landing Pins (GTLREF0/1) act as input buffer for DIE0, End Landing Pins ( GTLREF2/3 ) act as input buffer for DIE1.
For dual core single-die chips.
Middle Landing Pin (GTLREF0/1) acts as input buffer for DIE0, End Landing Pin (GTLREF2/3) uncertain if used. Either unused and terminated to open drain Vtt or used as reference for middle pins as margin of error.
Address strobe Pins (GTLREF1/3) will generally tolerate small variance with respect to reference voltage accuracy, and should in most cases be setup a little lower with respect to Data strobe Reference multiplier or voltage.
Why?
Probably the same reason as any other reference or input voltage for clock strobes, signal resonance or cross talking.
Data strobe pins (GTLREF0/2) will not tolerate being out by more than 0.5-1% below nominal, but will tolerate slightly more above nominal. Keep set values above Address Strobe GTL multiplier/voltage offset.
Why?
Works better in almost all situations, don't know why until I get a chance to monitor on a logic analyzer.
By How Much?
Varies according to FSB base clock, higher the FSB BCLK the smaller the difference will probably need to be at least with respect to the Diff Amplitude driving the clock.
EOF
On a side note I'm going to try and see if a mate can get me access to a Logic Analyzer and the software to analyze and overlay the samples, provided I can figure out the board locations to measure the signals... I don't really even know where to start but my friend is a circuit board designer so hopefully he'll be able to work it out. Fingers crossed anyway.