I never said that, again: FSBs physical latency stays always the same for an Intel Core no matter how large cache or fast the FSB is. :confused: The lines, soldered on the board, provide a fixed latency, which the FSB protocol has to respect. Thats the weak point in my point of view. If the prefetcher catches the wrong data the whole Cache (no matter what size) is pollutet with sensless Data and a very very long access (through all the PCB layers) to the memory is necessary. In this Case the great advantage of the Core architecture (getting the data fast and very close to the processing unit) has turned upside down.
Jack, i just made a quick test with CoH and a 1950Pro, unfortunatly i cannot go higher with the resolution due to a 19 TFT
First shows Resolution 1280*1024 CPU settings max GPU setting max.
Second shows Resolution 800*600 CPU settings max GPU Settings low
http://www.abload.de/img/cputestxro.jpg
I have alot more Action on Core 3 with higher GPU Setting :confused: I'm confused :shrug:. Maybe you can check this out. Besides can you give me a script or program which records the cpu utilization ?
I´ll try to get more data later