Madhsrimps artricle about tRD (performance level) on i7!

http://www.madshrimps.be/?action=getarticle&articID=940

interesting!
the title of the article is a bit misleading imo, not exactly what the article is about. i was quite surprised when i read it, positively surprised... :D
has anybody else played with this cas B2B timing? sounds a lot like tRD alright... hope we can get it unlocked soon! though i think both dfi and evga already play with it by adjusting the memory speed straps... though adjusting tRD directly would be a lot more efficient of course :D

Very interesting Article, many thanks Saaya.

How were they able to determine the value of B2B on the ASUS board, I can't even see this timing in CPU Tweaker.
Or maybe it's present in the BIOS, I think they started to show the actual values set in one of the latest BIOS versions.

Is there any software which will show the value of this B2B setting ?

Very intereesting indeed :) Looks like I need to get my hands dirty on my R2E :cool:

could be the answer to all the problems with memory the DFI UT X58 has... good find saaya!

Very cool. One thing I like about the the Rampage Formula is that it allows tRD adjustment. It can make a noticeable difference for memory performance :up: I'd be interested to find out how similar B2B is.

Very interesting, thanks for the link! :)

Amazing... What a difference.. Nice post ;P

Dramatic effect on bandwidth, indeed.
Great article!

Would be nice to see more motherboards allowing to change this, but thinking of how this effectively would ruin DDR3-2000 kit sales which are significantly expensier than DDR3-1600 I don't think it'll happen...

At least RAM manufacturers would be highly resistant about adding this setting to more motherboards.

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Originally Posted by Frank M

Dramatic effect on bandwidth, indeed.

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Thats the least concern on i7. :D

Im more intrested in the scaling of bclk. :)

Almost no difference in BCLK, at least, not at first sight.

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Originally Posted by Hornet331

Thats the least concern on i7. :D

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Oh yeah, really :D
It might come in handy with dual-channel Lynnfield, though.

RTL is more tRD than anything else on this platform, the RTL value is a result of the post Tx equation and sets the read back time from the DIMM's (the the IMC needs to be ready within that window for the transfer to take place). All downstream offsets between the Uncore an CPU are set according to RTL. CAS perforamance can be mirrored by adjusting the RTL value by upto 4ns past the sensed value, so long as a transistor pad is avaialble by the time of a readback request you'll get a post. In effect one can get CAS 8 performacne at CAS 7 if the value is moved out too far. Basicaly speaking keep RTL as tight as possible if you want the fastest performance at every point. The only thing I have not looked at much is the effect of higher Uncore frequencies upon the avaialable RTL window.

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Originally Posted by raju

RTL is more tRD than anything else on this platform, the RTL value is a result of the post Tx equation and sets the read back time from the DIMM's (the the IMC needs to be ready within that window for the transfer to take place). All downstream offsets between the Uncore an CPU are set according to RTL. CAS perforamance can be mirrored by adjusting the RTL value by upto 4ns past the sensed value, so long as a transistor pad is avaialble by the time of a readback request you'll get a post. In effect one can get CAS 8 performacne at CAS 7 if the value is moved out too far. Basicaly speaking keep RTL as tight as possible if you want the fastest performance at every point. The only thing I have not looked at much is the effect of higher Uncore frequencies upon the avaialable RTL window.

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Great post raju. :up:

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Originally Posted by RPGWiZaRD

Would be nice to see more motherboards allowing to change this, but thinking of how this effectively would ruin DDR3-2000 kit sales which are significantly expensier than DDR3-1600 I don't think it'll happen...

At least RAM manufacturers would be highly resistant about adding this setting to more motherboards.

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not really, intel has obviously tweaked memory performance for 1333, thats what they focus on... since there is no official 1600 support they dont have a propper strap for that with really tweaked timings, so once bios engineers rip the intel memory code apart more and more, we might be able to tweak performance manually and get the same efficiency out of the imc as at 1333, which means with propper tweaking ddr3 2000 might actually make sense :)

does anybody remember how higher fsb clocking actually made little or no sense initially on 965/p35 etc as trd and the fsb straps above 333 were really lax and performance barely scaled or got even worse? similar thing here... im not surprised theres barely a gain with more than ddr3 1333 atm cause thats the max intel tweaked the memory code for, its the highest propperly programmed/tweaked strap...

its not like mem above 1333 will have huge boosts from this, 3 channels is really massive bandwidth even at low clocks already, and especially with apps only using 2, maybe 3 cores, there isnt a huge need for bandwidth... so far... but i do expect higher than 1333 to scale better if it would be tweaked propperly

and raja, im not sure but there is no rtl setting on the asus boards is there?
could it be that what they call b2b cas is a part of rtl or somehow adjusts rtl?

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Originally Posted by The-Fox

Very interesting Article, many thanks Saaya.

How were they able to determine the value of B2B on the ASUS board, I can't even see this timing in CPU Tweaker.
Or maybe it's present in the BIOS, I think they started to show the actual values set in one of the latest BIOS versions.

Is there any software which will show the value of this B2B setting ?

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We compared the AUTO setting, which reads out as zero in the bios with manual settings. What we did was test it with Everest benchmark, superpi 1 and 32mb. Then did the manual settings on the Gene II and REX II mobo's... till we found the B2B setting that gave the +/- same results.

It really has a dramatic influence on ram bandwith ( and not really on latency like with S775 ), luckily for us I7 users there's plenty of bandwith to mess with, but we want every Mb we paied for don't we ? When being around 12 ( for eg 2000mhz action ) and dropping to 10 gave nice boost, going down to 8, the boost was not as big and so on...

I only tested the values that were 100% Hyperpi stable (8 threads) and will include them results in the upcoming Gene II review. This means that eg if we recommend a setting of 8 for daily usage (this to be bulletproof) that you can squeeze out some more performance for eg for Pi 1Mb benching purposes by dropping an increment or two.

We passed Massmans and my findings to Asus...

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Originally Posted by RPGWiZaRD

At least RAM manufacturers would be highly resistant about adding this setting to more motherboards.

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I think it will be better to include this bios settings as it will get more performance if adjusted properly (if set too loose by the mobo's bios) and if required ( when set too tight like eg with the Asus boards) to allow more stability.



Some 32Mb and Everest screenies of the tests :

C12 Test 1600Mhz C7

http://users.telenet.be/OAP2/Gene%20...ENEIIC2B12.jpg

C10 Test 1600Mhz C7

http://users.telenet.be/OAP2/Gene%20...ENEIIC2B10.jpg

C8 Test 1600Mhz C7

http://users.telenet.be/OAP2/Gene%20...ENEIIC2B08.jpg

What a big difference!

My point was the higher frequency you go the higher you also have to have the B2B timing, handicapping the benefit of paying a load of extra money for very minor/no performance if at DDR3-2000 you'll have to use like 10-12 and at DDR3-1600 you can use like 6-8. That's what I'd think would hurt the DDR3-2000 sales unless there will be kits that handle such low B2B timings at higher frequencies too (but perhaps it's more of a mobo limitation? and then you're screwed eitherway).

When you're not able to change this setting (it's set to say 12), the performance gain at higher frequencies, eg. going from DDR3-1600 to DDR3-2000 there's a bigger benefit for these RAM kits (altough only a fraction of DDR3 sales are those kinda kits anyway). But average joe won't even know of this setting in first place so it won't matter however it would turn out, but assuming every1 were aware of it then clearly more people would start looking into lower frequencies and tweaking tight timings and low B2B at slightly lower frequencies like say DDR3-1600, at least with todays offerings and price of the higher binned stuff remain unchanged.

^ That's what RAM manufacturers might not like about this. It might lead to having to lower prices on the higher binned kits and that's something every manufacturer likes to avoid if being able to or then they simply disappear if there's no reason to sell them if you can get roughly same performance at lower frequencies with tighter B2B setting.

I see your point, good arguments there , but think that the high binned ram kits are also interesting to work with on other platforms, this is just purely I7 related (I5 is on the M testbench, will have to check with Massman how it goes there).

Indeed with this setting you can regain some big ram bandwith (on certain mobo's with a too loose B2B setting) with a mere 1600mhz kit. Ram manufacturers might not like it, but we do :p So I still wish all manufacturers would add this feature to their biosses (under whatever name)

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Originally Posted by Leeghoofd

Indeed with this setting you can regain some big ram bandwith (on certain mobo's with a too loose B2B setting) with a mere 1600mhz kit. Ram manufacturers might not like it, but we do :p So I still wish all manufacturers would add this feature to their biosses (under whatever name)

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Yes ofc as a tweaker that could spend several hrs just to find optimal RAM performance by changing one setting one-by-one, I personally would want this to be changable on all X58 (and P55) mobos ofc as I have my mind set on the DDR3-1600 kits anyway since those have by far the best price/performance/overclockability ratio IMO and this setting offers a little extra fun and seems very useful for these kits. :p:

It reminds me a lot of Performance level (PL) setting on DDR2 as I get roughly similiar results at DDR2-1000 4-4-4-8 PL7 as DDR2-1200 5-5-4-10 PL8. This setting wasn't changable on all mobos either but then most of the time MemSet would do it for you, I'm hoping some1 would manage to do this for B2B too.

This timing is mentionned in the Intel datasheet at page 69.
I made some test and it's possible to change it under Win; I'll add this feature in the 1.2 final version.

Thanks for the info and support Felix, you are truly a Gem to our community, what would we do without you ?

I am quoting from Intel's datasheet Felix has linked:

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B2B_CAS_DELAY.
Controls the delay between CAS commands in DCLKS. The minimum spacing is
4 DCLKS. Values below 3 have no effect. A value of 0 disables the logic. Setting
the value between 3-31 also spaces the read data by 0-29 DCLKS. The value
entered is one less than the spacing required, i.e. a spacing of 5 DCLKS
between CAS commands (or 1 DCLK on the read data) requires a setting of 4.

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So, massman, do you want to confirm that 0-3 values has not effect ? :p

I can confirm that on asus p6t dlx auto = 4 :) (bios 1606)

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Originally Posted by The-Fox

So, massman, do you want confirm that 0-3 values has not effect ? :p

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It makes sense since setting below 4 there's no gain in performance and, as Kiwi said, Asus defaults at 4 although the bios value indicates 0.

It's been here on the Gene II. Makes a huge difference in memory performance when you change values... 0 to 4 dont seem to make any difference, but as you increase the timing, bandwidth seems to suffer and scales with b2b