Originally Posted by
ArsTechnica
Reverse hyperthreading? Um, no.
By Jon Stokes | Last updated July 13, 2006 8:17 PM
Thank God the Inquirer finally put the whole "reverse hyperthreading" thing to rest with an admission that such a technology is not, in fact, coming to AMD processors. Judging by the volume of questions I got about this, a fairly large number of people were taken in by this canard. I never bothered to report on it, for much the same reason that Nobel Intent doesn't report on, say, the latest theories about how the US government is using HAARP to manipulate the weather. But because the Inquirer seems to be trying to shift the blame for this nonsense subtly onto AMD, I'll go ahead and explain why, no, it's not something AMD "would like to have" or that they'd ever consider.
Anatomy of a fabrication
In case you haven't been following the whole reverse hyperthreading saga, here it is in a nutshell. The Inquirer originally posted a report to the effect that AMD's forthcoming dual-core processors would be able to present themselves to the OS as a single CPU, sort of opposite the way that a single-core Pentium 4 with hyperthreading can present itself to the OS as two separate processors. Here's the meat of the article:
"It seems that all AM2 CPUs were outfitted with a support for Reverse-HyperThreading, an architectural change which enables software to think that it is working on a single-core alone. By combining two cores, the company has been able to produce the six IPC "core" that will go head to head against four IPC "core" from Conroe/Merom/WoodCrest combo.
It seems that in certain cases, even an old AMD Athlon 64 3800+ can wipe the floor with Core 2 Duo E6300 CPU."
First off, there's no way this would work the way the author seems to think it would. How would the cores' pipelines support this in any phase of execution? In the fetch phase, there would have to be some arbitration mechanism whereby the two cores fetched alternate instruction blocks from the I-cache, thus distributing the instruction stream across two processors.
Then, once the instruction stream is fragmented inside the two cores, how are the register files kept in sync? If an add in one line of code writes its result to a register in one core, then how could a test instruction in the other core read that distant register to see if it needs to branch? Or how would out-of-order execution work across two cores? Would the instruction schedulers have their own separate bus to communicate over?
Anyway, it's not worth going into too much detail here, because it's kind of like asking how Superman could lift an entire continent up into space without it breaking apart, or how he manages to fly in the first place, and so on.
Stick a fork in this one, because it's done.
) and now intel seems to have pulled it off, lol
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