Thanks.
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Thanks.
1) better fsb
2) kill your cpu
PLL...isin't that a chip on the PCB?
So, if my cpu does 475fsb x8 it will not help me in my quest for 450fsb x9?Quote:
Originally Posted by Supertim0r
Nope. SuperTim0r summed it up perfectly.
Darn, here comes some more science ...Quote:
Originally Posted by Richard Dower
PLL stands for phase locked loop and it is the primary circuit in the processor that sets the overall clock and not necessarily the processor .. PLLs are used anywhere that a device is clocked against a reference where the resulting clock is higher than the reference clock.
It works by taking an input waveform and generating a new waveform that locks it's phase to the incoming but with a multiple of the freqeuncy. This is why traditionally, multipliers have been whole numbers, because to lock the phase you want the generated wave form to start at the same point of the period and end at the same point of the period to remains stable.
Here is a square wave phase locked to a multiplier of 2, top row is input wave form, bottom is output wave form:
++++++++++++++++----------------+++++++++++++++++
++++++++----------++++++++------+++++++++-------.... and so on, the frequency is 2x of the input, phase lock is bolded --- this is just a simple example.
Now you can achived the same lock if you allow the end phase to be exactly 180 degrees out of phase:
++++++++++++++++----------------+++++++++++++++++
+++++++++--------------+++++++++---------------
So the output wave form is 1.5 of the input wave form.... now you have 1/2 multipliers....
Jack
He said PLL Voltage :) it just helps to gain stability with high FSB, I leave mine at 1.5 daily - max 1.6 for benching. But I've seen peeps here going over 1.7 and that even with 45nm CPU's... I don't take that risk...Quote:
Originally Posted by Richard Dower
if pll is for fsb, what does fsb voltage do?
All clock circuits have a certain amount of jitter. Increasing the clock speed results in the jitter increasing also. By raising the PLL voltage the noise margin is increased effectively lowering the perceived jitter.
What does it mean to be 180 degrees out of phase. Did you mean 90 degrees?Quote:
Originally Posted by JumpingJack
So that means if you bump PLL voltage too much you'll end up with a CPU for lunch?
http://i54.photobucket.com/albums/g1.../lunchtime.jpg
Well, that statement kinda applies to any CPU related voltage you bump up too much.Quote:
Originally Posted by fireice2
http://radarproblems.com/chapters/ch...ir/sine180.gifQuote:
Originally Posted by CoW]8(0)
The cyan trace is 180 degrees out of phase with the blue trace.
If you were to write the functionality of the blue and green it would look like this:
Blue = sin(x) with x in degrees
Cyan = sin(x+180) with x in degrees
180 is refered to as the phase shift, greek character phi is often used.
A PLL must lock onto a node, the simplest explanation is that for this to occur at the node when the wave forms cross at 0, in the same going direction (this would be in phase), this would result in whole multiples of the output wave form. If the PLL locks at the node where the node is going in opposite directions (negative going), it is out of phase....
This is a simple explanation for it... another way to think about it is that the output wave form is in phase with the input wave form ever 2 periods.
Here is a better example of a 2x PLL locked in phase with an integer multiplier.
http://www.necel.com/en/faq/faq0203b.gif
Jack
Sure but that doesn't really justify half multipliers does it? The blue and cyan are still at the same frequency.
No, if I want to lock I need to lock at a point of reference, I can be in phase at the start and end of the period, or I can be 180 degrees out of phase at the end of the period and still be on the node. The point at each node (where it crosses zero), the phase is 180 out.Quote:
Originally Posted by CoW]8(0)
Hence, you are x+1/2 a cycle more within the reference waveform.
You don't have justify 1/2 multpliers, you just need circuit that can do it..
But how does that relate to half multipliers?
Look this is easy... it is not hard.... but if you can't see it you can't see it....Quote:
Originally Posted by CoW]8(0)
Take a wave, then superimpose a wave on top of that such that the they both begin and end on zero, that is all you need.
Hang tight, I will do an XLS plot to show you.
EDIT, here you go:
http://www.xcpus.com/gallery/d/4601-2/2x+example.JPG
http://www.xcpus.com/gallery/d/4604-2/2_5+Example.JPG
The top 2x example is made by sin(2x) of the input wave, the 2.5 x example is, logically, multiplier 2.5 of the input wave. Both examples shows, in one period of the input wave in each case the nodes match this is what it means to phase lock more or less (over simplified). In one case the node has the waves locked at 0, in phase (both are starting their postive deriviatve), in the other case the node is locked, but the waves are 180 deg out of phase.
Now, this becomes an interesting mental exercise ... design a circuit that will phase lock on 1/2 nodes. Hmmmmm, I would have to think about that one. But if you google phase lock loop multipliers you will turn up oodles of patents.
sorry . for my question (have read many threads abut this PLL and GTL ref voltages and etc. .. sorry i am not on math & sience :) )
so just want to know if i have Asus Maximus Extreme board (bios v.1001)
and its minimum (manual) settable voltage value for CPU PLL voltage - is 1.50v and (in bios HW monitoring page it refers to 1.560~1.567 ( visual )
/ dont have equipment for real mesures /..
so have a qx9650 with TRUE120 on top ... what is my options ?
are these things some how related ? if that qx9650 nominal vcore is 1.25v (by intel spec) then is this 1.50-1.56v a killer for that cpu?
(but it is minimum cpu pll voltage for this board ) :shrug:
No, the PLL voltage is separate as it drives the clock distribution but not the transistor. You are fine. Don't worry about it.Quote:
Originally Posted by i43
@ JumpingJack ! Thank You for quick reply
:)
Thanks for the plots, but now plot sin(t) vs sin(1.5t + pi) and you'll see what's wrong with that statement.Quote:
Originally Posted by JumpingJack
I have PLL voltage at 1.60V for daily usage. Too much?
1.5t + pi just shift it over... by pi (180 degrees) with a multipler now of 1.5, this has nothing to do with mulitplying or phase locking. At the node, the waves will be out of phase, not the same frequency, but out of phase for 1/2 multipliers in 1 period of the input wave form... this is not hard.Quote:
Originally Posted by CoW]8(0)
I.e. sin(2.5t) != sin(1.5t+pi) != sin(t)
Look you are stuck on a semantic ...
At the node where the wave locks, for 1/2 multipliers, one end the waves are instantaneously in phase and on the other end out of phase. If you prefer, forget the term 'phase' althgether .. and simple say x out put waves in 2 periods of the input wave, or x/2, when X is odd it will be non-integer 1/2 multpliers. Not quite how the circuit works, but you can say it.
Intel specs out what it should be and what the ranges are....Quote:
Originally Posted by laragirl83
http://download.intel.com/design/pro...s/31873201.pdf
Intel quotes 1.5 volts +/- 5% (so 1.425 to 1.575) ... you are a hair over... probably not too much...
Can I just say guys, that this is an extremely interesting thread. Very useful for truly understanding the PLL voltage. Just started playing with it myself, with only a vague idea of what it did. This has certainly cleared it up!