AMD Bulldozer to be launched in 19th September

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據台灣主機板業指出， AMD 下代 AM3+ 處理器經過多次的修正後將會於 8 月初正式量產，預計將會 9 月正式發佈，初上市將會推出四款不同型號，包括四核心 FX-4100 、六核心 AMD FX-6100 、八核心 FX8-100 及 FX-8150 。

採用 32nm SOI 制程，原定於今年 Computex 發佈、代號「 Zambezi 」的全新 Bolldozer 微架構處理器，採用全新 AM3+ 處理器封裝，，由於部份設計需作出修改而延期，最終落實於 8 月初正式量產，預計將會 9 月 19 日正式發佈，這是 AMD 自 2003 年 Athlon 64 處理器後首次針對微架構作出重新設計。

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Translation:

Information from Taiwan motherboard maker, AM3+ processor will go to mass production in August after multi-delays due to some re-design/changes, expected to launch in September, initial launching includes 4 different models, that's quad-core FX-4100, hexa-core FX-6100 and octa-core FX-8100 and FX-8150.

Manufacture under 32nm SOI, initial debut at COMPUTEX 2011, codename "Zambezi" the Bulldozer is the ground-up redesigned micro-architecture, using Am3+ socket, it was delayed due to several changes in design, finally going to mass production in August, and expected to launch in 19th September. This is the whole new micro-architecture from AMD after Athlon 64 since 2003.
http://i56.tinypic.com/fw21s0.jpg

http://i55.tinypic.com/2igox8k.jpg

p/s: my own translation, please re-translate if you do not understand my word.

source: http://www.hkepc.com/6810/page/1#view

8170 frequency is going crazy:eek:

8150 for me on launch and 8170 after the 8150 sells on Amazon or for another build :evil:

If they undervolt well, ill go for the 8150, disable turbo --> green edition :)

I want the 8170!

I don't want to know what the price tag of that is however :confused2

Probably will just get a lower model like the 8100 and overclock the crap out of it :up:

If they are really all unlocked then there is not much point to get anything more expensive than 8100...

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Originally Posted by zalbard

If they are really all unlocked then there is not much point to get anything more expensive than 8100...

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In theory, higher speed models may overclock better. Specially with the first batches. Reviews will tell.

Isn't the suspect launch date origin from XS post?

4 model in 8x is too much and too close

does lower 4C/6C model got chance to core unlocked

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Originally Posted by imamage

Isn't the suspect launch date origin from XS post?

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yes. but usually HKEPC has a reliable track record on the information posted on their website.

Lets see and wait, still two month to go ;)

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Originally Posted by Nintendork

In theory, higher speed models may overclock better. Specially with the first batches. Reviews will tell.

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So far it has hardly ever been the case. The difference is too tiny when pricing is considered. It's the steppings that usually show significant OC headroom difference.

I just wish it came sooner, been waiting for this CPU for so long, hope the wait was worth it, AMD really needs a killer CPU to compete with Intel's current offerings. Liking the specs and CPU clock speeds, and I hope it performs as well and it sounds.

Isn't the lowest TDP of 8100 and 8120 restricts the OC headroom against the higher TDP of 8150 and 8170 (95W vs 125W) ?

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Originally Posted by mak1skav

Isn't the lowest TDP of 8100 and 8120 restricts the OC headroom against the higher TDP of 8150 and 8170 (95W vs 125W) ?

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it depends on how turbo can be adjusted, the moment we touch an overclock we kinda turn those things off and just do it our way

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Originally Posted by PatRaceTin

4 model in 8x is too much and too close

does lower 4C/6C model got chance to core unlocked

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Actually, if you look at it you see that its 2 8X a 4X and a 6X. The others are listed as Q1-12. Look at the dates on the bottom.

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Originally Posted by mak1skav

Isn't the lowest TDP of 8100 and 8120 restricts the OC headroom against the higher TDP of 8150 and 8170 (95W vs 125W) ?

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When you OC you blow away any TDP ratings anyways :p:

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Originally Posted by Sparky

When you OC you blow away any TDP ratings anyways :p:

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Don't the 125w chips have a different thermal design that allows them to clock higher than the 95w? :confused:

OMFG that's gonna be some OC goodness!!!
8 cores of pure OC goodness..... :D

I will be there :)...

Right before my birthday, excellent.

81xx series looks like it'll be fun to play with. I'll let you guys test the OCing on these chips before I dive in. If all chips scale the same, I wonder too if TDP and design will show a difference between 8100 & 8150.

What no one knows is how these will do temp wise. I think if we're looking at 125w TDP for the higher end, these will need to be put under water, but only time will tell.

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Originally Posted by [XC] Synthetickiller

Right before my birthday, excellent.

81xx series looks like it'll be fun to play with. I'll let you guys test the OCing on these chips before I dive in. If all chips scale the same, I wonder too if TDP and design will show a difference between 8100 & 8150.

What no one knows is how these will do temp wise. I think if we're looking at 125w TDP for the higher end, these will need to be put under water, but only time will tell.

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This is what I'm thinking as well. If the lower end 81XX scales as well as the higher end 81XX, I see no point in spending the extra money on nothing!

I always assumed 95w chips had to be the better binned chips since they need less voltage to operate at a given speed.

whaaahhh , i need trinity already

Well IMHO, that's usually the case when there's another regular part with the same clock but less TDP (and a premium price), but most probably you'll see both running the ~same voltage.
From 8100 to 8150 the 800MHz difference could justify the extra 30W, and there's also the big chance that those 95W are just lower bins because they can't hold 3.6GHz at 125W (and turbo power limits on top of that). I guess it's a bit to soon to see the low voltage models disclosed, maybe they'll appear at the Q1 12' speed up when the process has matured enough.

I don't put much weight on process node, really. As long as performance is there, and power consumption is ok, who cares really? Process node is only 1% of the whole picture.

on that note,
if next gen BD integrated next gen GPU could really be a revolution even if on a bigger precess than rivals, I suppose all that's left to see is how bd performs and then we can draw up some conclusions

IF I think about it Komodo should be released not so long after IB and if I am not mistaken IB will be released at the start of 2Q.

DHB got slide that stated october release, like what one britain site hinted.

http://www.donanimhaber.com/islemci/...e-edilecek.htm

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Originally Posted by Daveburt714

Seriously man, you realize your in the AMD section right?

You can't judge BD's preformance from a bunch of rumors...

I'm risking getting banned again here, but maybe you should go back to the Intel section. :shakes:

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Dave you rebel you :p:

I see your point though. This is tipical for near launch AMD CPU's. I don' t spend a lot of time in the Intel section, but don't recall the kinda of havok the AMD section gets on new product launches.

BTW, with the way Glo Fo is moving I can see the process gap shrinking very soon. And like mentioned above, process node is not the huge picture. AMD has been competing pretty well being a node behind in the segment they are in.

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Originally Posted by charged3800z24

Dave you rebel you :p:

I see your point though. This is tipical for near launch AMD CPU's. I don' t spend a lot of time in the Intel section, but don't recall the kinda of havok the AMD section gets on new product launches.

BTW, with the way Glo Fo is moving I can see the process gap shrinking very soon. And like mentioned above, process node is not the huge picture. AMD has been competing pretty well being a node behind in the segment they are in.

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For example, Phenom II (refined AM3 version) is very competetive with 45nm wolfdale...
I expect AMD to at least match Bloomfield CPC this time around, and if they can do that + release chips that run high clocks 4.5-5 Ghz OC they will have a great chip to compete with. (Something Bloomfield didnt do, think Sandy Bridge @ 4.4 with 8 cores type feel) The price is what matters, though.

if they are giving us 4.x ghz turbo, i hope we see 5ghz easy on water 24/7
and if theres no cold bug, im scared to see what some LN2 will do

switching platform on september 19th going bk to AMD going to give a FX-8150 a try from my current set up!

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Originally Posted by bro20000

switching platform on september 19th going bk to AMD going to give a FX-8150 a try from my current set up!

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8170 is part of a refresh to the lineup, it isn't in the initial launch. Unless of course AMD pulls another switch like they did with the 1075T/1090T.

Any more flamebait keiths and you'll be removed from this section.

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Right before my birthday, excellent.

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For me it's right after my birthday :)
But it will make the perfect 1-day-later b-day present for me. Gonna go straight for the powerhouse - FX-8150.
Hope the release date sticks :up: (although i wouldn't mind a day earlier..)

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Originally Posted by Gautam

Any more flamebait keiths and you'll be removed from this section.

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Don't hesitate, I have no need to converse with those who think what was written was flamebait, but what I ask is this subforum not show up on what's new.

That's enough, keiths.

Can't wait for this to come out OMG. My E8400 is like a brontosaurus and is begging to be put into retirement. Will definitely wait and see some results before I dive in though.

@Vapor, do you happen to know what episode/season of Futurama that Bender gif is from? :)

Roughly 7 weeks to go. :)

I had a chance to upgrade/sidegrade my Intel rig and made it into a secondary system. My AMD system should be ready to go for Bulldozer. I just need to get a good cooler that will handle it. I was thinking of getting a COOLER MASTER Hyper 212 Plus and using it on my Phenom II in the meantime. Anybody know if this will have any problems cooling these chips or should I wait for coolers that have been verified to be able to handle it?

The 212 doesn't rate very high on the list. It's respectable, but there are better options. There aren't any specific things we'll have to worry about with Bulldozer core CPUs. They dump heat into the same heat spreader we've all come to know and love. The bigger and more efficient the heatsink, the better it'll be at removing higher heatloads produced under overclocked and overvolted conditions.

http://www.frostytech.com/articlevie...id=2572&page=4

But the CM Hyper 212+ does very well in the price/performance value. In Norway its 1/2-1/3 the price of the top dogs, yet its not really that far behind in cooling.

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Originally Posted by Particle

The 212 doesn't rate very high on the list. It's respectable, but there are better options. There aren't any specific things we'll have to worry about with Bulldozer core CPUs. They dump heat into the same heat spreader we've all come to know and love. The bigger and more efficient the heatsink, the better it'll be at removing higher heatloads produced under overclocked and overvolted conditions.

http://www.frostytech.com/articlevie...id=2572&page=4

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Oh my god, people should be given a week's ban for referencing frostytech. They are WRONG.

By the way, a Mach2 GT holding -50c at 125w heatload? No. No. No. A thermaltake Frio does not beat an NH-D14 either.

You're welcome to your opinion I guess, but I trust FT's heatsink reviews more than anyone else's currently. It's in the same way that I trust JonnyGuru to review power supplies.

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Originally Posted by Particle

You're welcome to your opinion I guess, but I trust FT's heatsink reviews more than anyone else's currently. It's in the same way that I trust JonnyGuru to review power supplies.

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It's kind of like jonnyguru's reviews, without any of the accuracy. It'd be like if he used a kill-a-watt to measure efficiency and a $10 analog voltmeter to measure voltage changes. They review a lot of heatsinks, but most results are not indicative of real-world results. Some heatsinks listed are clearly worse than others yet perform better on their test plate. It's almost like they test heatsinks with whatever thermal paste comes in the package instead of using a consistent paste and/or mount pressure.

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Originally Posted by BeepBeep2

By the way, a Mach2 GT holding -50c at 125w heatload?

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Thats just about right on evaporator temp. CPU's core temp. will be varies

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Originally Posted by BeepBeep2

It's kind of like jonnyguru's reviews, without any of the accuracy. It'd be like if he used a kill-a-watt to measure efficiency and a $10 analog voltmeter to measure voltage changes. They review a lot of heatsinks, but most results are not indicative of real-world results. Some heatsinks listed are clearly worse than others yet perform better on their test plate. It's almost like they test heatsinks with whatever thermal paste comes in the package instead of using a consistent paste and/or mount pressure.

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It would be like that if they used bad equipment and had no consistent testing methodology, but they don't and they do.

will the Super Talent 1600 9-9-9-25 1.5V work with any BD chip?

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Originally Posted by Particle

It would be like that if they used bad equipment and had no consistent testing methodology, but they don't and they do.

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It's a good concept, however they show results that aren't logical. Xiggy SD964 beating H50? (I own one of those SD964's btw, and a core contact freezer...bought because I used to believe frostytech reviews) True 120 beating True 120 Extreme by 4 degrees at 125w?...

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Originally Posted by duron

will the Super Talent 1600 9-9-9-25 1.5V work with any BD chip?

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sir, i think it's more on d board compatibility side instead of chip. i got sticks which can happily run 2.1k on one board but disliked by another. :)

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Originally Posted by ah_khoo

sir, i think it's more on d board compatibility side instead of chip. i got sticks which can happily run 2.1k on one board but disliked by another. :)

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True, but it is a little of both really. ;)

agreed. it also depends on whether or not the imc of the chip play nice with the ram being used. :)

i thought the IMC has the upper hand when controlling or having compatibility issues

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Originally Posted by duron

i thought the IMC has the upper hand when controlling or having compatibility issues

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not necessarily coz sometimes same chip & ram can yield different results on different boards sir. :)

Man I can't wait! My mother has been wanting a new computer for a while, so when I told her that her next computer could have 8 cores instead of 6, she immediately told me she would wait and she's on pin and needles with excitement, waiting for BD to come out. I'm building her a high powered Adobe Suite Graphics Station. Possibly later with a second screen. I can't wait till I get to mount that new CPU!!!

Is it true that you get better faster processor for the same money as for buying Intel cpu?


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- Sent from my iPhone using Tapatalk

I don't know, but I know BD is gonna be real fast.... and I don't buy Intel because of their business practices, so really for me its the only other option. Even though there's two companies with lots of options to choose from, it still feels like a very limited choice. I really wish AMD would get its act together and recover from the blows its suffered.

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Originally Posted by LLiH

Is it true that you get better faster processor for the same money as for buying Intel cpu?


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- Sent from my iPhone using Tapatalk

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no, that's not true.

What you will get is a competitively priced CPU that will be better than Intel at some some, while worse at other things. It may be a little cheaper for the power you get, as AMD doesn't have quite the reputation as Intel.

As for the upcoming BD chip from AMD. I suspect multithreaded apps it will be better, while single threaded it will be worse (for your money anyway). Will you notice.... nah, I doubt it.

I hope they're out by the end of September. I'm more than ready :)

After that I'm going to upgrade my GPU with AMD's next big thing when it hits.

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Originally Posted by Blacklash

I hope they're out by the end of September. I'm more than ready :)

After that I'm going to upgrade my GPU with AMD's next big thing when it hits.

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yeah & while their at it maybe they could release FM2 by January :D

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Originally Posted by duron

yeah & while their at it maybe they could release FM2 by January :D

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Waiting on FM2 probably is a wise move. I'll be happy if overclocked BD can hang with overclocked SB well. If FM2 ends up blowing BD out of the water in performance, I'll eventually move to that.

I'm tired of playing the waiting game so I'm snatching up BD when it hits.

Oh looks like AMD discovered Netburst architecture - I smell patent war :ROTF:

Not if AMD allready have right to some patents of Netburst.

You remember what Intel had to settle with AMD? :)

Bulldozer has nothing to do with Netburst. It has high clock potential,that is the only similarity.

Only one month away now....

What's the expected price on these? I'm not crazy about the FX returning, they were as bad as the old P4 extreme chips with way too high a price for what they did not do.

Wooo! 2 posts since 08', darn forum change over :p:

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Originally Posted by Judaeus Apella

I don't know, but I know BD is gonna be real fast.... and I don't buy Intel because of their business practices, so really for me its the only other option. Even though there's two companies with lots of options to choose from, it still feels like a very limited choice. I really wish AMD would get its act together and recover from the blows its suffered.

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:up: gotta support the underdog, intel is a damn monopoly!

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Originally Posted by Blacklash

I hope they're out by the end of September. I'm more than ready :)
After that I'm going to upgrade my GPU with AMD's next big thing when it hits.

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the anticipation for both BD and the HD7000 series is killing me....

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Originally Posted by duron

yeah & while their at it maybe they could release FM2 by January :D

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pffft 2012 is the end of the world remember?? AM3+ will go out in style with no replacements :D

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Originally Posted by Zeus

Only one month away now....

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Last I read (on digitimes/pcmag) server parts will be released Sept 26th, followed by the desktop parts a few weeks later.

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Originally Posted by SoF

Oh looks like AMD discovered Netburst architecture - I smell patent war :ROTF:

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Having speed demon design does not mean it's like netburst.....
BD will have higher IPC than K10.5, while Netburst had lower IPC than Pentium 3.

It's like AMD decided to make it a speed demon AND a brainiac chip at the same time.
And they designed something superior to hyperthreading (modules).

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Originally Posted by Apokalipse

Having speed demon design does not mean it's like netburst.....
BD will have higher IPC than K10.5

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Actually pushing higher IPC was not the design goal in BD.

Can you elaborate on that? I seriously doubt that BD wasn't meant to be faster clock-for-clock. AMD hasn't pushed real IPC improvements in K10 so that would mean that they would be satisfied with IPC that is comparable to K8 (2003?).

IPC may not have been the largest design goal, but it has indeed increased in the BD core regardless.

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Originally Posted by JumpingJack

Actually pushing higher IPC was not the design goal in BD.

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But they did push IPC. It just wasn't the only thing they pushed.

Indeed,IPC will probably increase with Bulldozer core but not by much- think 10% in int and similar for FP (without recompile). With Llano we had a >6% (AT measured up to 14% and as low as 3%), just by some smaller tweaks and upping the L2 cache size to 1MB. With BD ,we have a whole new L2 cache that is now shared,we have some massive pipeline changes (to allow higher clock) and we have some major uarchitectural improvements in instruction fecth,decode,branch prediction and last but not least prefetching.All these are a big step up and will offset any IPC impact that longer pipeline (or 3rd ALU) might have had on Bulldozer average IPC.

i think their initial concern was making a proper module that gives the best perf/mm2 they could. if they on top of that worried about a massive IPC increase, they might have messed up alot of the balancing and created accidental bottlenecks.

i think what will be good to watch is the number of cores for a typical chip (250-300mm2) on each process. the increase is currently showing a rapid increase due to K8 design being slightly updated for almost a decade now, and so with each shrink they can simply pack in more. so in the next decade we can either see chips with 30+ cores as things continue to just double, or we might see a trend leading to a cap as IPC starts to become the main focus.

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Originally Posted by Manicdan

i think their initial concern was making a proper module that gives the best perf/mm2 they could. if they on top of that worried about a massive IPC increase, they might have messed up alot of the balancing and created accidental bottlenecks.

i think what will be good to watch is the number of cores for a typical chip (250-300mm2) on each process. the increase is currently showing a rapid increase due to K8 design being slightly updated for almost a decade now, and so with each shrink they can simply pack in more. so in the next decade we can either see chips with 30+ cores as things continue to just double, or we might see a trend leading to a cap as IPC starts to become the main focus.

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IPC is not the main focus for a long time. More cores and ISA extensions are. Intel did manage to get some good increases out of Core design,that is true,but with Haswell you can expect something more like coprocessor onboard and more specialized instructions for specific tasks.And yes,more cores. Similar goes for Bulldozer's successors.

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Originally Posted by informal

Indeed,IPC will probably increase with Bulldozer core but not by much- think 10% in int and similar for FP (without recompile). With Llano we had a >6% (AT measured up to 14% and as low as 3%), just by some smaller tweaks and upping the L2 cache size to 1MB. With BD ,we have a whole new L2 cache that is now shared,we have some massive pipeline changes (to allow higher clock) and we have some major uarchitectural improvements in instruction fecth,decode,branch prediction and last but not least prefetching.All these are a big step up and will offset any IPC impact that longer pipeline (or 3rd ALU) might have had on Bulldozer average IPC.

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IPC was definitely not a focus of Llano. It's basically just K10.5 plus a GPU, and minor changes. And BD has a completely new core, so it's not really comparable.

IPC is definitely not as high as AMD could have made it. But I think it would put it somewhere in the ballpark of SB (where exactly I don't know).

You do need a good balance of IPC and frequency (not just focus on one of them and ignore the other eg Netburst), and I think AMD tried to be aggressive up to a point in both, but they do often trade off each other (as well as power consumption, die area)

So yes it is more complex than saying "AMD focused on getting IPC up", but it's not completely inaccurate.

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Originally Posted by v0dka

Can you elaborate on that? I seriously doubt that BD wasn't meant to be faster clock-for-clock. AMD hasn't pushed real IPC improvements in K10 so that would mean that they would be satisfied with IPC that is comparable to K8 (2003?).

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http://ieeexplore.ieee.org/Xplore/lo...hDecision=-203

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Compared to previous AMD x86-64 cores, project goals reduce the number of F04 inverter delays per cycle by more than 20%, while maintaining constant IPC, to achieve higher frequency and performance in the same power envelope, even with increased core counts.

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AMD published 3 articles on Bulldozer at the ISSCC 2011, this one describes in detail the integer cores and scheduler, there was another paper describing the details of the module, sharing, and circuit design and a 3rd which discussed details on the L3 cache design. All three were very interesting reads.

Jack

"while maintaining constant IPC" is the key word. The design is clearly optimized for good average IPC,keeping the pipelines fed via the aggressive prefetch and 3 separate schedulers.

Does "constant IPC" mean that it doesn't vary much between different loads? (ie being able to keep feeding the cores with aggressive prefetching, etc)

Yes,at least that's how I read it.

There is always going to be significant IPC differences between various types of workloads. Some algorithms will naturally make better use of certain architectures than others.

The way I read "constant IPC" was as maintaining a consistently high IPC within any given workload. As opposed to, say, blazing through the arithmetic only to stall hard because of a missed branch predict. The new branch prediction, prefetch, beefy decoding, cache hierarchy, etc I think backs that up. It's to keep the reduced number of ALUs consistently fed. If they were going for maximum IPC they could have added extra execution units as well. It would benefit certain types of code with high ILP, but the extra units would be hard to keep fed on average and so IPC would fluctuate more.

IPC depend on software optimisations, but also is hardware dependent. All CPU's have relativly same peak IPC, but average IPC isn't same. Average CPU IPC represents how much ILP has software on certain CPU or even GPU. That average IPC is determined by memory access, cache hit rate, how CPU handle with Out of Order execution, number of execution units, efficiency of branch prediction, type of workloads etc...
If you have CPU with long pipeline, bad branch predictor, high memory latency, average prefetcher and on the other hand lot of FP execution resources and high memory bandwidth, that CPU could be potentionaly bad performer with pure branchy integer code, but will be monster with accessing paralel data and SIMD execution.
However, CPU's are tradeoffs in most cases.
In Bulldozer module we have one flexible FPU, which has almost the same area of 10h FPU. But that FPU with two threads from two integer cores has almost same IPC per thread like 10h FPU alone. With two threads FlexFPU is completly utilised and there is no wasted resources. Also front end... average workload has not IPC more than 1. BD front end can decode up to 4 instructions. That is enough to feed execution engine with two strong threads and has minimal imact on performance per thread per core (not module).

I want to tell that for eg. if you have strong FPU, and weak integer CPU you have not balanced CPU for most workloads. Also if you have strong integer CPU, and weak FPU, CPU isn't balanced well. But you can make ultimate IPC CPU with ultimate FPU, but that is expensive or can't clock high or isn't power efficient. If you make for eg. tradeoff with critical elements, you can lose 5-10% of IPC, but you can get less expensive CPU that clocks higher and dissipate less energy.

Because of that IPC isn't everything. This is a part of whole picture. We all want CPU with good IPC, which clocks higher than todays CPUs, which has also good single thread performance and CPU with cool core. That is more important than how much FPU in such CPU can execute DP ops per cycle. :cool:

BD will be very good if IPC per module will be 15-25% higher than 10h, frequency 15-20% with same or lower power envelope.

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Originally Posted by Solus Corvus

It's to keep the reduced number of ALUs consistently fed. If they were going for maximum IPC they could have added extra execution units as well. It would benefit certain types of code with high ILP, but the extra units would be hard to keep fed on average and so IPC would fluctuate more.

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2 ALU's isn't so much problem because L1 Data cache is 2-ported. There is only two memory operations per cycle, with 10h or even BD. There is two AGU's which is used for memory address calculatons. Most of integer operations are mov's from reg-mem, mem-reg etc.... BD integer core will be much stronger than 10h, because of much better memory level parallelism.

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Originally Posted by drfedja

2 ALU's isn't so much problem because L1 Data cache is 2-ported. There is only two memory operations per cycle, with 10h or even BD. There is two AGU's which is used for memory address calculatons. Most of integer operations are mov's from reg-mem, mem-reg etc.... BD integer core will be much stronger than 10h, because of much better memory level parallelism.

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I didn't say it was a problem. Sometimes you really can do more with less. If they kept the extra ALU or even added more to satisfy certain high ILP code (ie, not average) then they would just be wasting power and transistors that could have been, and were, spent elsewhere (more cores).

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Originally Posted by drfedja

I want to tell that for eg. if you have strong FPU, and weak integer CPU you have not balanced CPU for most workloads. Also if you have strong integer CPU, and weak FPU, CPU isn't balanced well. But you can make ultimate IPC CPU with ultimate FPU, but that is expensive or can't clock high or isn't power efficient. If you make for eg. tradeoff with critical elements, you can lose 5-10% of IPC, but you can get less expensive CPU that clocks higher and dissipate less energy.

Because of that IPC isn't everything. This is a part of whole picture. We all want CPU with good IPC, which clocks higher than todays CPUs, which has also good single thread performance and CPU with cool core. That is more important than how much FPU in such CPU can execute DP ops per cycle. :cool:

BD will be very good if IPC per module will be 15-25% higher than 10h, frequency 15-20% with same or lower power envelope.

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Right. I mean, it wouldn't be that hard to increase IPC by 25 or 30% from K10.5 But it would be very hard to do it without using a lot of transistors, using a lot of power and/or sacrificing a lot of frequency.
Instead of increasing IPC in any way possible, you'd want to increase IPC in inexpensive ways, and try not to spend transistor budget in areas that won't get much use.

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Originally Posted by Solus Corvus

I didn't say it was a problem. Sometimes you really can do more with less. If they kept the extra ALU or even added more to satisfy certain high ILP code (ie, not average) then they would just be wasting power and transistors that could have been, and were, spent elsewhere (more cores).

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Maybe in rare cases, but in average ILP is much more dependent by MLP than how much ALU units you have. ;)

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Originally Posted by Apokalipse

Right. I mean, it wouldn't be that hard to increase IPC by 25 or 30% from K10.5 But it would be very hard to do it without using a lot of transistors, using a lot of power and/or sacrificing a lot of frequency.
Instead of increasing IPC in any way possible, you'd want to increase IPC in inexpensive ways, and try not to spend transistor budget in areas that won't get much use.

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Increasing ILP (or IPC) is more important for execution of non-paralel code (singlethread), but for high paralel code is more important how much cores you have and how much power they dissipate. That is the main paradigm of Bulldozer CMT - good single thread ILP with usage of all shared resources, and average multithread ILP with lot of low power cores. If you have a fat CPU core, you can add a little than you have two tiny cores. Because of that, BD module acts like one fat CPU core or two tiny with power budget of one fat core.

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Originally Posted by drfedja

Maybe in rare cases, but in average ILP is much more dependent by MLP than how much ALU units you have. ;)

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ILP isn't at all dependent on the number of ALUs. Having more ALUs, and a smart front end, only allows you to take advantage of ILP when present and convert it into IPC, but the ILP is fixed.

ILP depends on the specific code being executed. Instructions that depend on the results of previous instructions reduce ILP. Some pieces of code don't have any ILP and only clocks or speculative execution can help.

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Originally Posted by Solus Corvus

ILP isn't at all dependent on the number of ALUs. Having more ALUs, and a smart front end, only allows you to take advantage of ILP when present and convert it into IPC, but the ILP is fixed.

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Instruction-level parallelism (ILP) is a measure of how many of the operations in a computer program can be performed simultaneously. A goal of compiler and processor designers is to identify and take advantage of as much ILP as possible.
ILP is dependent of course by smart front end, and also by memory ordering subsystem. CPU with good memory disambiguation will have more ILP than CPU without it.
When I talk about memory level paralelism I mean that how CPU handle load/store operations. This is one of main CPU function (load and store). ILP and IPC are different words for same think. Only difference is how it is measured. IPC measures how much instructions are executed per cycle. ILP is not measure. ILP is feature - for example: how many instructions is executed per minute, second or cycle is feature of instruction throughput.

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ILP depends on the specific code being executed. Instructions that depend on the results of previous instructions reduce ILP. Some pieces of code don't have any ILP and only clocks or speculative execution can help.

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ILP and IPC depends on specific code. Instructions can't depend on previous instruction, data has dependencies. If n-th instruction uses data which is calculated by n-1 instruction, that instruction works with data which has data depenedent by previous calculated data. Because of data dependencies instructions must wait on scheduler for needed data.
Speculative memory address calculation can help with data dependencies.

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Originally Posted by drfedja

Instruction-level parallelism (ILP) is a measure of how many of the operations in a computer program can be performed simultaneously. A goal of compiler and processor designers is to identify and take advantage of as much ILP as possible.
ILP is dependent of course by smart front end, and also by memory ordering subsystem. CPU with good memory disambiguation will have more ILP than CPU without it.
[...]
ILP and IPC are different words for same think. Only difference is how it is measured.

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The first part is true and an unsourced quote from wikipedia. The bolded part isn't true. ILP is a function of the code, it doesn't depend at all on the hardware it is being run on.

IPC and ILP are related but not the same thing. ILP is a measure of how much total parallelism possible, at the instruction level, there is in any given code. Instructions are either dependent on each other or they aren't. IPC is a measure of how effective any particular CPU is at recognizing and utilizing that ILP, or speculatively bypassing dependencies, to keep available processing units occupied and how long it takes those units to complete the given instructions.

Maybe an analogy would help: think of Thread Level Parallelism. A program with 2 threads, for example, has a TLP of 2. It has that TLP regardless of if it is running on a single core or dual core CPU. Obviously a dual core would be able to utilize that inherent parallelism better. Even though the TLP of the program doesn't change depending on the CPU, the throughput (a rough proxy for IPC at the TLP level) will be higher on the CPU that can recognize and utilize that parallelism.

The way I see it is AMD perceives the code its target market runs most depends more on MLP and TLP than it does on further increases in IPC. Instead of fighting with Intel over diminishing returns in IPC, at a high cost of power and transistors, they are targeting the relatively unexploited parallelism in high-threaded data driven applications. This says to me that they are aiming, first and foremost, directly at retaking the server and scientific market.

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Originally Posted by Solus Corvus

The first part is true and an unsourced quote from wikipedia. The bolded part isn't true. ILP is a function of the code, it doesn't depend at all on the hardware it is being run on.

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Ok...I have missed something... definition from wiki says: Instruction-level parallelism (ILP) is a measure of how many of the operations in a computer program can be performed simultaneously (from wikipedia).

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IPC is a measure of how effective any particular CPU is at recognizing and utilizing that ILP, or speculatively bypassing dependencies, to keep available processing units occupied and how long it takes those units to complete the given instructions.

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...that explains why profilers has IPC for measuring performance of code. If you have more ILP with code, IPC will be higher and peformance of code could be higher. (not neceserily higher)

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Originally Posted by drfedja

...that explains why profilers has IPC for measuring performance of code. If you have more ILP with code, IPC will be higher and peformance of code could be higher. (not neceserily higher)

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Profilers use IPC because it is the more useful measurement. ILP is how many instructions could theoretically be executed in parallel given an idealized CPU. IPC is related to how many instructions actual hardware can execute simultaneously. Rather than some theoretical figure that doesn't really help, IPC is telling you how the code is playing out in real hardware.

Generally more ILP is good, but it's not a rule. ILP is just a measure of how many instructions can be executed in parallel, it doesn't tell us anything about how much useful work is being accomplished by those instructions. There are cases where a lot of parallel but simple instructions accomplish less than a few serial but more complex instructions (such as a bunch of individual math ops VS a single AVX or SSE instruction), or where a more efficient version of an algorithm (or one that is a better match for a given CPU's branch prediction capability, etc) has less ILP but still accomplishes a task faster than a less efficient algorithm. Again, this is why measuring the real performance of your code on actual hardware with a profiler is important.

drfedja

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BD will be very good if IPC per module will be 15-25% higher than 10h, frequency 15-20% with same or lower power envelope.

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I agree. Llano is also better by 6-7% and those were just some minor tweaks with doubled L2 cache.
Now BD has an Integer cluster bigger by 15% than Llano and the whole module except the second integer is bigger by 60%. I think we will see a healthy increase in IPC.

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Compared to previous AMD x86-64 cores, project goals reduce the number of F04 inverter delays per cycle by more than 20%, while maintaining constant IPC, to achieve higher frequency and performance in the same power envelope, even with increased core counts.

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IF its true, that would be great for notebook Trinity, because honestly Llano APU for notebooks is too much limited by TDP and thats why the frequency of cpu is so low.