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i have not found a way to unlock them, this thread is dedicated to people who want to help me and others to find a way to unlock the recent multiplier/fsb/cache lock.
ok, i will start with the cache and the relating L2 (andL9) bridges first. here is the 1st LAYER of the L2/L9 circuit of my locked duron 1.4ghz
I have a 1.6gig duron on the way for a friends system.. ill be planning on clocking it so ill see what I can do midweek once the chip arrives.
well in case amd changed the bridges slightly, or cut them in a way that they are always shorted, no matter how you bypass them, you can cu the trace comming from and leading to the cut and connect them directly.
weeeeee! i have just fuggered like 200 of my own posts, halfway to it baby.
i will check the circuit of the multis next, the duron died when i removed the entire first layer of the L2/L9 bridges a few hours ago :D
ok, making a drawing of the multiplier circuit (layer1) now.
have you guys noticed that except for the left L9 bridge all of the L9 bridges go back to a pin? so maybe enabling the L9 bridges will make the cache controlable via the pins? something amd originally planned, but always locked afterwards?
this could have been plannes for compability purposes originally, like a mainboard that doesnt support barton cpus could tell the cpu to run with only 256kb cache so it would work... just an idear, i dont see what the L9 bridges should be good for if not for that...
has anybody tried cutting a bridge? if the cpus would really be core locked as a lot of people claim, then it wouldnt make a diference right? i dont think they are core locked. if the core would have a lock, then it must be there since the first tbreds probably since the first palominos. but if they had that lock all the time ehy did they spend all the workforce to change the package again and again to keep people from unlocking and overclocking the cpus rather than just enable the lock?
i think it has to do with the package...
all traces leaving the image are going straight to the core. i will take off the little black chips and check the second layer tomorrow. hope you guys can make use of it.
just keep on commin' on. we'll figure it out someday. even if it means removing a layer of the pcb modding it and putting it back on LOL.
saaya - how are you removing the substrate to expose the circuits? Sounds like fun, I have a dead 1700+ and a nice stereo-microscope here.
first i used a razor knife, but then i switched to small grid sand paper, much faster :D
you can remove the first layer of epoxy with some chemicals, but its not worth it if you ask me...
according to ita from fab51 you could change the L2 cache size of unlocked chips via the multis, if you connect all L9 bridges. i bet it wont work, but ill give it a try anyways :D
ive got a feeling that amd either used some new pins that were labeled as nc till today, or maybe even uses a vcc pin as a signal pin now, to make it harder for us to find the new pin(s)
or its only the package... wich would make most sence, since amd has been working on the package for months now... and it would be a lot easier to do that change or use new pins for a lock...
dude it would be great if you could make a drawing of the circuits of that cpu or post pics!!!
hmmm i got some very interesting results when i meassured the resistance between the pins of the black chips!
all the pins on the core side have no resistance to each other.
the right pin of the chip of the L2 bridge leading to the right L2 bridge wich controls the L2 cache size and is cut on durons and throtons reads no resistance the any of the core sided pins either!
how do i read the values? :P
if i set my multi to read resistance and set it to 2000, does it mean the actual resistance is the number on the display x 2000 :confused:
EDIT: the black chips are resistors it seems. whe i set my multimeter to read resistances and 2000 i get 998 from each pin to its counterpin. so if the resistance between a pin and its counterpin of the black chips is smaller than 1000 the two pins are connected somewhere else right?
according to ita from fab51 1kohm resistance results in less than 1v when the cpu boots up, and is interpreted as a 0 or no connect.
this makes sence, all the pins have a resistance of 1000 ohm to their counterpin, wich means they are disconnected, unless the bypass, the bridges, are connected and reduce the resistance to around 350 ohm. if the bridges are connected the resistance between the pins drops and the voltage rises above 1v and will be interpreted as a "1". if the bridges are connected the 1k ohm resistance reduces the voltage to under 1v wich is then interpreted as a "0".
when the black chips where still connected to the bridges i meassured this on them:
(multi set to resistance / 2000 ohm black-cable=ground on the pin that points away from the core)
from right to left:
0 ohm
184 (174when i switched the cables of the multimeter)
186 (178 when i switched the cables of the multimeter)
990
the L2 bridges the pins lead to (from right to left) were :
cut - connected - connected - cut
I hope you will suceed would be awsome. :toast: Keep up your work :D
all the L2 bridges on my 1700+ are closed, and i get a resistance of 204 (multi set to read resistance /2000) between all the legs of the black chip and their counterpins!
220 for the connected bridges and 990 for the pins connected to cut bridges.
i meassured the voltages on my duron on diferent spots while it was running:
black chip of the L2/L9 bridge: all pins read 0.014v , except for the pins that lead to the connected L2 bridges, they had around 0.32v running through them. i expected more :/
btw, all golden spots, triangles, the bridge names etc read 0.014v ....
hmmmm the trace of the right L2 bridge runs like this:
core -> right L2 bridge -> 1Kohm resistance -> vss?
(im pretty sure its comming from the core ,or its only running under the core, but i dont think so)
so cutting the trace that leads to the core and connect it to vss with a resistance inl line should work?
i will try to enable the cache, and not mess with the multis atm, since its a cluster of bridges and as you can see from my drawing is extremely messed up. the cache bridge is build up extremely simple, there are 4 traces to the core, each can be set to 1 or 0 by cutting the appropiate bridge or, assuming the L9 bridges are connected, by the mainboard by connecting AD8 AF8 AH8 AF6 to some current or grounding them.
hmmm, i will bypass the entire L2 bridge array on my 1600 tomorrow, and connect the traces leading to the cpu with vss and vcc with a 300 ohm variable resistor in line.
wish me luck! :D
if this doesnt work the cpus are either locked inside the core (seems more and more likely to me the longer i think on it) or they have a mechanism to ignore the external signals, maybe we need to short some pins or connect some pins to disable that lock and be able to access the multiplier cache again.
First of all I'm pretty sure AMD did not locked the barton inside the core. The main reason I'm thinking this is because there are steppings which are the same between locked en unlocked procs (aqzea)
Maybe you could be on to something with those resistor packs. I have done some measuring on them before en these are the values.
maybe this is also comes in handy. A nice hi-res pic of the barton :D. Way more usefull than looking through a magnifing glass. HI-RES PICQuote:
fist the pic for clarification
http://members.home.nl/youpy/bartonnetje.jpg
Now some numbers. I just completed measuring the resistancepack. From top to bottom in the pic:
Pack 1 -- Top
Unlocked______Locked
1002_________998
996__________1001
905__________977
904__________980
Pack 2 -- Middle
unlocked______Locked
902__________955
898__________956
903__________951
1003_________1003
Pack 3 -- Bottom
unlocked______Locked
900__________958
905__________963
918__________976
900__________973
All these values are in ohms. I know the resistorpacks are somehow related to the bridges. Maybe the lower values result in a logic 0 and the higher values to a logic 1, which are interpreted by an mp chip.
youpy, the lock could have been integrated to the core from the beginning of the palomino, but they never enabled it... and now they want to push people to move to the a64, so they enabled it all the sudden. there would have been no need to make a new revision of the core and they wouldnt change the stepping name of course, so people dont know exactly whther a cpu is locked or not from the stepping name.
These new locked chips suck. Glad I stocked up on onder tbred 1700's when it was looking like this was going to happen. About 5 new, and the 8 in my folding@home farm.
Newegg has some mobile 1700xp's 1.25 volts.
Pic looks like the normal tbred, before the new PCB crap.
http://www.newegg.com/app/viewProduc...3&searchdepa=0
looks good! and with one cut they are desktop chips :D
how much do they cost?
Tedinde, AIRGA0231WPDW ???
mobile...
saaya - your pm box is full. I've developed a fairly severe allergic reaction to something that will require medical attention. Don't wait on me for 1700+ circuits. Sorry :(
:eek: feel better!...
yea it sucks there now locked. cant you still buy one used from someone upgrading his machine though?
$58 from newegg. Havnt searched anywhere else. I miss those Mid $45 1700XP's bad!!!
saaya,
I'm sanding the dead 1700+ now. Down to the copper "ground plane" without seeing any traces. Did I go to far or do I need to sand some more. Using 600 grit. Hard to tell, this is a "brownie" and not the translucent "greenie".
i wonder if the new fx-51's will be locked also when the 939 chips come out, i sure hope not, as that is what will be my next setup.
no, afaik amd people said the fx will always be unlocked. its the performence cpu for the extreme enthusiasts.
and sjohnson, hold the chip agaibnst the light, if there are any copper traces they should refelct the light.
600 grit is pretty fine eh? hmmm your almost through the entire package already and there are no traces? :eek:
amd procesors? how weird, what are they used for? i heard they have a line of tools to break rocks, hammer or sumethin
saaya - I've removed a few thousandths of an inch (perhaps 0.1 millimeter) and I'm at the so-called ground plane we all tried to avoid when painting bridges. I saw some "pieces" of traces under the microscope that would disappear on the next swipe of the sandpaper. I can still see all the bridges, surrounded by that solid "ground plane."
Perhaps I used sandpaper that was too coarse and went right through the bridge traces?
found these links on enabling the L2 cache thats been disabled on the applebreds, wonder if its the same for thorntons.
http://forums.2cpu.com/showthread.php?threadid=42838
http://www.ocforums.com/vb/vb/showth...hreadid=236587
yeah its pretty much the same for throtons, but it only works on unlocked cpus before week 39/40!
sjohnson, the cpu package of the new chips is like theis:
-pins
-clear epoxy layer
-layer with copper traces
-silicon core of the package
(with a lot of small dots that go through it, that connect the traces of the layers on both sides of it)
-layer with a few small traces and the squares under the bridges that short the cut bridge if the cut is just filled with conductive paint
-layer with traces , the bridges and traces from the pins to the core are on this layer(95% of the bridge array are on this layer)
-clear epoxy layer
i used 180 sand papaer i think :/ weird...
what about the bridges? were there no traces going to the bridges? no traces under the bridges?
the cpu core is soldered on the first layer of traces under the clear epoxy layer in nano ball grid array.
I got mine but im a tad confused about the cache mod.
Here is a pic of the chip, do I just connect those two points with conductive paint?
Do I go over the bridge and fill it with paint as well?
I can go around or over..
Im not using a board with multiplyer controll... so I cant test that ATM, I may just force a higher speed by modding the bridges themselves.
Ooops forgott the pic.
Holst, I enabled the cache on my Duron 1400 MIXIB 0335 VPMW by filling the lasercut pit with conductive silverglue :)
So no painting around whatever, just simply filling the lasercut pit, and not connecting it to any dots :)
K, thanks for the help.
Now where did I put that silver paint?
LoL... now to unlock the damn chip, eh Holst? ;)
I cant even find the paint LOL.
I think I have some at work... although this PC (including the chip) has to be given away fairly soon.
Ill try and see if its unlocked now (I found an 8rda+ hiding in a cupbpoard)
No multimplyer conrtoll, but it boots up at 166x12 stock voltage... so its not all bad :)
stopped posting at 185x12 at 1.53v vcore (this board has had several vmods removed so I think its a bit messed up)
Pretty good going so far, im just gona install the OS so I can stab test it.
sorry , but i have to dissapoint you... that chip is definately locked... :(
yeah those durons clock really really nice... too bad they are locked :(
mine can do 2ghz+ primestable with just 1.5v :)
Got 5 thortons in today 2400+'s, all locked. Testing the first one. before any modding. 160fsb stable. 2400mhz.
Gonna pick the 2 best one's to upgrade my AMD duallie. For that 5ghz box!!! and 1mb of total L2 cache. currently a pair of 1700xp's @ 2250mhz in it.
Gonna suck if these things wont do the XP-MP Bridge connect, has anyone tried it yet on the thortons.
Just connected the one L2 that's cut, it's the far left l2 that's cut on mine, not like the duron aboves right one??
Dam you AMD and you locking crap up!!! Dam pin mod doesnt for changing mults, One of these chips is going in a cheapo Epox Micro ATX board, for a customers rig, I was hoping to lock it in as @ 3000+XP
Quote:
Originally posted by Garrett
Holst, I enabled the cache on my Duron 1400 MIXIB 0335 VPMW by filling the lasercut pit with conductive silverglue :)
So no painting around whatever, just simply filling the lasercut pit, and not connecting it to any dots :)
First attempt didnt work. I did it like my usual 1700 mod. Fill in laser cut then connect. with circuit works pen.
Ok filling the lasercut pit as you say. And you had luck, Always though myself that's like the ground layer, you sure about that one Holst!!
But then i've got 5 chances with 5 chips. what the hell, i'll give that a shot.
No luck your way either Holst. Wondering if these thortons can be enabled @ all, gonna try another one.
Still no luck enableing the cache on 3 of them. Has anyone had any luck enableing the 512 on 2400+ thortons??
Can complain though. All of them are clocking just fine. I ordered them mostly because no killer 1700xp's to be found anymore.
I'd buy more of these chips without hesitation..
the new locked chips can still be modded to be a MP !!!! appearently thats the only thing that can still be changed!
at least thats what some people in the ocers forums said.
Are you scraping the surface to exposed the contacts? I've modded mine w/o any problem. I even closed the L12 bridge and made it 166MHz. See my posts here: http://www.xtremesystems.org/forums/...threadid=22221Quote:
Originally posted by Tedinde
Still no luck enableing the cache on 3 of them. Has anyone had any luck enableing the 512 on 2400+ thortons??
btw: these chips are weird though. On my NF7-S v1.2 if I use newer bios the auto detection becomes disable, the multiplier is always locked and the chip is detected as 166x15 but if I use an older bios, the chip is seeing as a 3000+, advance setting is enable and the chip shows up as 166x13
More info here: http://forum.abit-usa.com/showthread...threadid=29034
166 x 13
EQuito, it doesnt work on cpus after week 39/40...
they are locked with a new mechanism, maybe inside the core... the more i work on it, the more it looks like its inside the core... but im not giving up yet :D
I think we're talking about two different things here... ;)Quote:
Originally posted by saaya
EQuito, it doesnt work on cpus after week 39/40...
You are talking about unlocking multipliers and I was responding to Tedinde on how to enable the extra cache, even on multiplier locked Thortons like mine and his.
Cheers!
I also have a locked applebred 1400. The voltage can also be changed on the cpu. Well, at least trough the pin trick mod. I also tried to change the voltage with the bridges but that didn't work.Quote:
Originally posted by saaya
the new locked chips can still be modded to be a MP !!!! appearently thats the only thing that can still be changed!
at least thats what some people in the ocers forums said.
equito, the new locked durons have a new locking mechnism. modding the bridges doesnt work anymore, except for the mp mod it seems... the cache can NOT be enabled on the new cpus after week 39/40.
amd couldnt change the voltage pins because then the new chips would have been incompatible with some boards i guess...
Yesterday I bought one of it. His week is 46. last of L2 was cut. I try to cenntect it but cash was still 64k. others of L2 was connected, but I have decided to check it, and they was unconnected in fact...
What does it mean? Maybe L1 is unconnected too. Maybe it is fake?
Sorry for bad english
OK, looks like I was being too cautious. Since I thought I had nothing to lose I went deeper with my sanding and bam! started seeing the circuits of my dead 1700+.
This is an adaptation of saaya's first drawing. None of my L2 and L9 circuits go all the way to the core as in saaya's drawing. The one red circle shows a trace that appears to terminate under the 8-pin SMD, it does NOT connect to the SMD.
How can I tell? Because I can see copper where the one trace does connect and the red-circled trace still has some substrate above it, I cannot see the copper trace on it.
Two hours of bleary-eyed peering thrugh the microscope and sanding. I'm done for the night. I might need to clean up this drawing a bit but it's essentially correct.
(Edit)After some more sanding, the four traces going off the magnified area end up terminating at the core.
none of the traces go to the core? are you sure? maybe on the next layer... ?
what happens with the yellow traces that leave the zoomed area? where do they go?
have you looked at the circuit under a microscope or magnifying glass?
thx a lot sjohnson!
The sanding went so slowly that I wasn't able to clean enough off to give it a perfect look, so I may be wrong about the traces not going to the core. Scraping next to the core is difficult as you probably already know saaya.
I'm using a very nice Bausch & Lombe medical stereo-microscope to examine the traces. Bought it at an estate sale for 25 USD :D
I'll do some more sanding this evening (isn't world time sucky, I'm just getting up to go to work) and make changes as needed.
No need for thanks, it's kind of fun lol...
yeah, its really nice to see the guts of a cpu you played with for years isnt it? :D
damn i wish i had a microscope :D im using a simple magnifying glass wich more or less has a 2x zoom effect :/
since i meassured the voltage on the bridges while the cpu was running, i found out that the right L2 bridge didnt have any voltage at all, so my plan was to cut the trace going to that bridge before it reaches the bridge where it is set to ground somewhere. then connect the trace from the core to another trace of the L2 bridges wich DOES get some volts since the bridge is connected.
i cut 2 traces that were ging to the bridges, comming from the core, and the cpu would not boot! so the traces are not useless! if the cpu would have been completely die locked, then it wouldnt matter if the traces would have no contact afaik.
i carefully sanded the package of my duron 1600 until the traces were accessable, then i carefully cut the trace that leads to the right L2 bridge ,i already mentioned.
next step was to cover the other traces with clear epoxy again, what i just did. im now waiting for the epoxy to dry out and then i will connect the two traces and see what happens
Just finished some more sanding. I need a life lol...Quote:
Originally posted by saaya
none of the traces go to the core? are you sure? maybe on the next layer... ?
what happens with the yellow traces that leave the zoomed area? where do they go?
have you looked at the circuit under a microscope or magnifying glass?
Working on the next layer only after I get the whole chip first layer traced. Might be a while, this is slow going :rolleyes:
The four yellow traces that leave the zoomed layer all meet up and go to the core, about across from the "L6" mark.
It is so interesting to read your postings...
If you guys unlock the Duron, so I think you will be the international heros. :-)
I think that L9 is have a some meaning. Because when I tried to unlock the cache (I have 4th of L2 was cut, and all of L9 was cut), so I connected 1st and 4th of L9, then turned on computer. but he did not start... When I cut only 1st of L9, so computer started... Maybe the part of locked cache is really bad..
Maybe it have another meaning.
Why I connect L9: because here (In russia) we have experience to connect 1st and 4th of L9 and connected pin AF8 to GND, AH8 to GND that is equivalent L2.
Why I wrote it all, maybe it help you to unl:banana::banana::banana::banana: it. Because I have Duron 1400 (46 week) too...
Thanks, hws :). Who knows what bit of information might lead to an unlock?
I tried the Lv2 mod but have had no success so far despite trying a few times. I am scratching the 'cut' Lv2 bridge and completely filling it with Silver conductive paint from Maplins.
Each time i try to boot with the paint on it beeps lots of times,although works fine when i remove it with a rubber. The chip i got is:
It is actually very strange! The bridges are completly differnt to all the photos/pictures i have seen, so i hink this thread is about two different cpu's. As this crude picture shows:Quote:
DHD1400LV1C T807117260549
MIUHB 0338VPMW
http://www.asck76.dsl.pipex.com/eBay/Applebred1.jpg
http://www.asck76.dsl.pipex.com/eBay/Applebred2.jpg
The shown loops are actually more complicated but would only confuse the matter if i did show them.
My main problem is that the bridge i am trying to connect is very small - smaller than a Tb core - it certainly cant be see without a magnifying glass.
This article HERE (in Italian) may be explaining my problem. If I understand the article correctly (via Google translator) AMD has changed the bridges i.e. thorton core. It looks like the the connection points are misaligned from the traces as to make painting impossible.
The article alludes to an upcomming pin-mod but it's not yet available.
Here is a close-up of what my chip looks like as shown on the above mentioned site:
http://www.hwtweakers.net/immagini/rootkill/m4.gif
If you look very carefully you can see that the connections are not so simple anymore, even if you do scratch to get to them.
I had another go today but had the same result! So i'm watching this hread like a hawk and will help contribute if i can.
The connections are as simple as before once you scratch the surface:Quote:
Originally posted by del_35
If you look very carefully you can see that the connections are not so simple anymore, even if you do scratch to get to them.
del_35, the dots you connected are fake and are notconnected to the bridges as at all! you have to scratch off the first clear epoxy layer, then you see the copper bridge that has been cut, and can connect the two sides agfain. its really really small thus very hard to do though. if you had a problem with connecting ther fake spots already you shouldnt try to connect the real bridge as its even a lot smaller.
and about the L9 bridges, as i wrote before, they are a second way to set the cache size. you can either set the cache size by the L2 bridges, or by using the L9 bridges. amd cut all the L9 bridges though and disabled the option to set the cache by connecting some pins.
havent had time to connect the two traces yet, maybe tomorrow...
Sorry if i didnt make it clear but this is what i am trying to do at present, i might go buy a decent magnifying glass and it should be ok then. I am tring to conect the hidden dots.Quote:
You have to scratch off the first clear epoxy layer, then you see the copper bridge that has been cut, and can connect the two sides agfain
Do you think if i successfully connection the laser cut bridge it will renable the Lv2 cache? Anyone done it yet?
You have the older core there. The new ones have fake dots.Quote:
Originally posted by EQuito
The connections are as simple as before once you scratch the surface:
EDIT: Been trying again today but it didnt work. It must be locked :mad:
yes, your chips is before week 39/40 right? then you can enable the extra L2 cache!
check the first pic i posted in this thread, it shows the bridge array
http://www.xtremesystems.org/forums/...5&pagenumber=1
my DHD1600DLV1C MIXIB 0345 UPMW duron ( so week 45 ) in an nf7-s motherboard is multiplier unlocked! :banana: dunno why but it is. any suggestions?
http://break.darkangel.hu/duron4.JPG here is the screenshot whit a 10x multiplier , no mod made on the proc
There seem to be sporadic reports of unlocked Durons. I saw an unlocked week 47 over at AMDMB and a 44 (I think) at OC forums. Give the L2 mod a try - see if the extra cache will work. I did it on an older Duron 1400 and it worked like a champ.
maybe the lock doesnt work on all chips and some are still unlocked?
should i give the simple l2 cache enable mod a try?
Well, I thought about the whole multiplier locking thing today and came to the following conclusion:
IMHO, AMD locks the chips' multipliers on the die level and not on the OPGA PCB or perhaps on the connection interface between the die and the package (more likely).
You ask me why I come to this conclusion? It's quite simple:
The question that came up in my mind was:
How come that there are still reported cases of CPUs with a production week >40 and they are still unlocked???
AMD is building Durons with Tbred-A core now, so they seem to have plenty of stocks left.
Perhaps these unlocked week >40 chips were built with DIEs that were left in stock from a production earlier this year and were then planted onto a week >40 package.
Well, sadly that would mean that we could never unlock these locked chips!
Perhaps I'm wrong and I'm open for any comments or possible corrections, but if it's true, were at a dead end trying to unlock these new chips and analysing/studying the differences in package.
Just my :2cents:
I hope I'm wrong, though :D :ROTF:
Edit: Perhaps I'm even seeing it the wrong way and the PCB is the real difference, but would it make a difference if there was a connection change on the package, exactly at the point where the DIE is connected to the PCB? :confused: We could never change that, too.
You mean older packaging. As you can see in the pic above, I didn't connect the fake dots.Quote:
Originally posted by del_35
You have the older core there. The new ones have fake dots.
I scrapped the protective layer and got down to the real dots for both FSB and cache.
Did your CPU mod then? Is it ok to cover the fake dots too or does this stop the chip working/moding? should i be just aiming to cover the hidden/covered bridge?Quote:
Originally posted by EQuito
I scrapped the protective layer and got down to the real dots for both FSB and cache.
EDIT: I went back again just now and it seem i have managed something.
It just booted but only registered 128k of Lv2 cache!!!! It also said unknown CPU 1400mhz
I'm guessing this means all my cache isnt available for some very strange reason.
Go check my post on the first page of this thread. ;)
well i figured i would thorough my 2 cents in here i found a local store that i bought a new 0403 1600 duron it was unlocked. so i went back and bought 2 more all 3 are mixib dlv1c 1600 durons the last numbers of the s/n's are 682, 685,and 689 so they should have came out all about the same day and about right after one another.
but 2 of these durons are locked the 85 and 89 is locked and the 82 is unlocked so i dont think it is the week and stepping that is unlocked but maybe just a lucky chip that gets through amd's new locking process
btw this duron will prime 2200 mhz at 1.5 in bios 1.47 in windows on an nf7-s and 1733 1.15v
yepp i think there are a few chips that dont get locked for some reason, too bad intels locking mechsnism locks all chips and doesnt leave a few unlocked like here :D
the cpus are def die locked, no way to unlock them unless we know how the locking mechnaism on the die looks like and how it owkrs. and even then it would be a huge work load to unlock them...
what about week 43 mobile bartons.. i dont get how they work unlocked fully while a reg 2500 is solid locked hard. they cant be making differant cores... thats way too many. it must be something else.
actually its the other way around.
the regular bridges are all locked, expect for the L5 and the mobile bridges on the right of the packaging. amd forgot to lock the L5 bridges so now we can turn every super locked xp into a mobile xp. the multi of mobile xps can be changed by the bridges on the right side of the core and by crystal cpu from windows. amd probably couldnt lock the bridges on the right side of the core wich set the operating speed of the mobile xps because they would have run into problems using speed step.