AMD Scorpius desktop platfrom and 32 nm Zambezi in 2011

Hi,

http://plaza.fi/s/f/editor/images/20...md_roadmap.jpg

I got this interesting slide from AMD which shows their current roadmap for Desktop Platform 2009 - 2011.

Next year AMD is planning to bring Leo-platform with 45 nm six-core Thuban CPU and RD890+SB850 chipset for enthusiasts and Dorado platform with Athlon II and RS880P+SB810 for mainstream.

In 2011 AMD is planning to launch new Scorpius-platform with AM3r2 Socket and 32 nm Zambezi CPU with 4 and more cores. For mainstream users AMD is planning Lynx-platform with Llano APU (up to 4 cores + 1 GPU).

Source: Finnish hardware site Muropaketti.com

Interesting. So is the Scorpius platform going to be a Phenom 2 derivative or Bulldozer? It seems to fall into place between the two.

R900 before "Scorpius", it seems. Aren't these platforms defined quite early, like Q1? That would mean that R900 should be ready by then and would go on-par with the current "Q3/Q4" rumours. Other than that, Lynx seems somewhat strange. Up to 4 CPU cores and one GPU core, in same package? That would mean that GF would manufacture at least some of ATI parts, even if only for the CPU. Wasn't the first GPU to be embedded in a CPU to be from HD3k series?

What exactly is the Llano APU? What's the purpose of APU?

Barcelona (city), Deneb (star), Thuban (star), Zambezi (city)...
Uh-oh. Ominous.

And I wonder if AM3 rev2 will be a PGA or LGA...
And why they didn't go LGA with AM2.
*shrug*

But I hereby demand they go 192bit memory on Bulldozer - I want my 6 DIMM slots on desktop boards.

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Originally Posted by Calmatory

What exactly is the Llano APU? What's the purpose of APU?

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APU, as in "accelerated processing unit". GPU-on-CPU. Few Bulldozer cores with a low end GPU on-die.

Zambezi=river actually

spirit actually.. this spirit brings them water to grow crops and fish to eat..

i guess amds waiting on a big harvest..

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Originally Posted by AKM

Zambezi=river actually

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Yup a river, but you also get the beer....that national beer of Zimbabwe.

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Originally Posted by largon

APU, as in "accelerated processing unit". GPU-on-CPU. Few Bulldozer cores with a low end GPU on-die.

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Now that gets strange. How does the CPU utilize the APU? If there's a sequence of certain instructions, they are executed by APU, just like floating point operations are executed by FPU? If so, great. Now we just need compiler support.

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Originally Posted by Calmatory

Now that gets strange. How does the CPU utilize the APU? If there's a sequence of certain instructions, they are executed by APU, just like floating point operations are executed by FPU? If so, great. Now we just need compiler support.

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this will likely end up similarly to how x86 CPUs handled x87 co processors.

I hope they keep the prices reasonable like they always do. :)

The AM3r2 must be related to AM3, otherwise they'd get a different name. Should have been AM4 IMO, less confusion.

Either way, it doesn't sound like Bulldozer to me. I thought it would need a completely new socket?:shrug:

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Originally Posted by largon

Barcelona (city), Deneb (star), Thuban (star), Zambezi (city)...
Uh-oh. Ominous.

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actualy it is Agena not barcelona if you're talking about desktop , and it is also declared as Stars in earlier AMD slides

on server side we got barcelona , shanghai, istanbul , etc ...

Am3r2 is probably like AM2+.

So hopefully it'll work in AM3 also.

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Originally Posted by Mats

The AM3r2 must be related to AM3, otherwise they'd get a different name. Should have been AM4 IMO, less confusion.

Either way, it doesn't sound like Bulldozer to me. I thought it would need a completely new socket?:shrug:

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Someone over at AMDZone has speculated that it is AM3+, i.e. Zambezi would work in existing AM3 sockets and in AM3+ sockets, but there would be perhaps be a minor loss of performance in regular AM3. Regular AM3 processors would not work in AM3+, ie downward compatibility but not upward compatible. Of course Zambezi would not work in AM2+ either.

The AM3 socket has 940 pins, but I think the AM3 cpus only use 939 pins. Maybe the extra pin is reserved for something. There are some really good threads on AMDZone about the technical justifications for and against this compatibility.

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Originally Posted by Mats

The AM3r2 must be related to AM3, otherwise they'd get a different name. Should have been AM4 IMO, less confusion.

Either way, it doesn't sound like Bulldozer to me. I thought it would need a completely new socket?:shrug:

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AM2+ was also named AM2r2 internallt so my guess is that it's AM3.

Zambezi will be based on the Bulldozer architecture, and most likely only support DDR3, so it will be socket compatible with AM3 and AM3+. Wonder when AMD will finally change socket?:shrug:

I personally like the easy upgrade path. Why change socket if it gives no benefit?

Quote:

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Originally Posted by Calmatory

Now that gets strange. How does the CPU utilize the APU? If there's a sequence of certain instructions, they are executed by APU, just like floating point operations are executed by FPU? If so, great. Now we just need compiler support.

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Eh, it's not any stranger than Intel Clarkdale, CPU with an integrated GPU.

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Originally Posted by AKM

Zambezi=river actually

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There's a also a city by that name.

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Originally Posted by Abu Assar

actualy it is Agena not barcelona if you're talking about desktop , and it is also declared as Stars in earlier AMD slides

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Oh, completely forgot about that, you're right.

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Originally Posted by largon

Eh, it's not any stranger than Intel Clarkdale,

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Of course not, I am more interested in how exactly does the APU utilize the ISA. For example, does the OS see it as a GPU? Does it need drivers? Could it be possible to run GPU physics on it? GPGPU? What kind of API support?

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Originally Posted by Calmatory

Of course not, I am more interested in how exactly does the APU utilize the ISA. For example, does the OS see it as a GPU? Does it need drivers? Could it be possible to run GPU physics on it? GPGPU? What kind of API support?

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That is a very interesting question, imo.

That would certainly be my guess--that the APU will show up as a regular GPU to the system. Historically, as new technologies have been introduced to the PC platform, it very rarely took the form of an abrupt change if it was to be successful. Some things can't be done in that way but are major value adders, such as sound cards. Either you've got sound or you don't. Other technologies like 64-bit, SATA, and such are packed full of compatibility modes and such. Looking at that history, it won't surprise me if the APU shows up as a GPU and the term APU just becomes AMD marketingese for "GPU on CPU".

2011 and new socket and cgpu, if THIS isnt bulldozer then my guess is bulldozer is actually dead :p:
thuban is 6 cores, and they mention above 4cores for zambezi, so that sounds a lot like up to 8 cores to me...
which is what bulldozer was supposed to be, native octa core...

apu, you guys are reading too much into it i think... :p:
i highly doubt that itll be integrated into the cpu silicon, and even if thats the case, itll be, guess what, a gpu and itll be recongized as such... this is the same intel is doing with 1156 igp, the same thing...

the sad thing is... bulldozer 8 cores were supposed to be out... earlier this year...
and now something that looks like a bulldozer/shanghai crossing is scheduled for 2011... so looking at amds cpu track record itll arrive in 2012+
and until then its going to be the same architecture... from now until at least 2011... so 2-3 years without anything new? ouch :S

Basically ,on desktop we will have:
2010-QC Athlon IIs for mainstream(renamed Phenom IIs?) and a new desktop hex core high end 45nm MPU based on Lisbon design(modified Istanbul),presumably at higher clocks/lower TDP
2011-a mix of new design on the high end (Zambezi-Bulldozer for desktop in AM3+ socket,backward compatible) and a 10h design(Shanghai QC) done @ 32nm and integrated along side the new GPU part on the same die. The last part about Llano being a 10h derivative done @ 32nm was already confirmed by design team member at AMD @ work blog,so it's official. This practically means AMD will not risk to introduce the BD design first on the brand new node,but instead they will "practice" the node on the Shanghai shrink and then move on the brand new design.

so this is still not bulldozer?
then bulldozer IS dead... what a shame... if theyd at least have something else to refresh the platforms, but they dont... :shakes:
so they will continue to just stuff more cores down our throats until 32nm, where they will finally introduce a new architecture?
or at least thats what they plan NOW... not really exciting is it? :/

and having igp on the cpu package... i still dont get it, they could have done that years ago...
as soon as they introduced the athlon 64 and hyper transport to the desktop, it was possible to move the igp chipset onto the cpu or do a cpu/cpu mcm...
they sat on their hands for 8 years now... intel had to do both first for them to really work on this seriously... :stick:

Zambezi IS bulldozer,and it was always scheduled for 2011,keep up Saaya :).

FYI folks, AM2+ was once codenamed AM2r2. AM3r2 will likely be known as AM3+. We'll probably see a little backwards compatibility.

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Originally Posted by Calmatory

Of course not, I am more interested in how exactly does the APU utilize the ISA. For example, does the OS see it as a GPU? Does it need drivers? Could it be possible to run GPU physics on it? GPGPU? What kind of API support?

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Seriously guys. It's just an IGP on the CPU. AMD calls it an 'APU', that's just marketing to make it sound more fancy than it really is. Same as the graphics cards have 1600 and 512 'cores'.

may BullDozer has a big leap in FPU performance due to the integrated GPU .....

Zambezzi is project Bulldozer, because Bulldozer is project codename K11, Orochi is CPU nick and Zambezzi is core (similary as K10-Phenom-Deneb)

Just FYI,AMD has stopped using Kx for their cores/designs some time ago.So K10 was in fact 10h. K8 was the last design that had a "starting" K letter in its name. Bulldozer is internal name for the uarch. project but I know there is one other name AMD uses for BD that is not known publicly(I don't know how they call it though).

Interesting thing about Bulldozer is that design was scheduled and targeted (originally) for 45nm node and 2009. But some thing(s) got in the way (die size at that node,AVX specs emerged in 2008,core rework in order to be competitive with intel's 2010/2011 cores etc.) so they postponed the core launch some 15 months from the original plan.That's not so bad since they had a backup plan in the form of San Marino platform and Magny Cours MPUs to tide them over until they "shrink" the BD to 32nm.So essentially BD is coming much improved and at smaller node in 2011,instead @ 45nm in 2009.

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Originally Posted by haylui

may BullDozer has a big leap in FPU performance due to the integrated GPU .....

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they havent managed to put a gpu and a cpu on a single package for 8 years... and now you think all the sudden they will jump from 0 to 110 and even integrate the gpu so deeply into the cpu that it can be used to boost fpu performance? caaaaaaaamm aaaaaaannnn :D

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Originally Posted by bowman

Seriously guys. It's just an IGP on the CPU. AMD calls it an 'APU', that's just marketing to make it sound more fancy than it really is. Same as the graphics cards have 1600 and 512 'cores'.

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For a software developer it is MUCH more than "just an IGP". The magic happens here: "on the CPU".

If a CPU can manage for example 50 GFLOPS with two FPUs, an integrated GPU in a CPU with 120 SPs could do 80 GFLOPS, that alone would give HUGE floating point performance, the FPU part of the CPU could be dropped and all the floating point arithmetric moved to be handled by the APU.

...OR then use FPU and APU, voila, 130 GFLOPS on a (mainstream) CPU. The thing which interests me is the interface between the APU and OS. Is it just a graphics processor which needs drivers, or can the OS see it as a co-processor? Can the OS see it at all? What kind of ISA?

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Originally Posted by Calmatory

For a software developer it is MUCH more than "just an IGP". The magic happens here: "on the CPU".

If a CPU can manage for example 50 GFLOPS with two FPUs, an integrated GPU in a CPU with 120 SPs could do 80 GFLOPS, that alone would give HUGE floating point performance, the FPU part of the CPU could be dropped and all the floating point arithmetric moved to be handled by the APU.

...OR then use FPU and APU, voila, 130 GFLOPS on a (mainstream) CPU. The thing which interests me is the interface between the APU and OS. Is it just a graphics processor which needs drivers, or can the OS see it as a co-processor? Can the OS see it at all? What kind of ISA?

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your dreaming! wake up already! :D

its an igp chipset on the cpu package, the same intel will launch in a couple of weeks for 1156... same thing!
you just move it from the mainboard onto the cpu package... there is no new driver model or anything like that...

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Originally Posted by bowman

Seriously guys. It's just an IGP on the CPU. AMD calls it an 'APU', that's just marketing to make it sound more fancy than it really is. Same as the graphics cards have 1600 and 512 'cores'.

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This is how I see it too. They do still have those 2 other options, anyone have that chart for AMD's future? It has like 3 options, I really don't expect to see 5870 performance on a cpu for quite a while haha.

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Originally Posted by saaya

your dreaming! wake up already! :D

its an igp chipset on the cpu package, the same intel will launch in a couple of weeks for 1156... same thing!
you just move it from the mainboard onto the cpu package... there is no new driver model or anything like that...

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Seconded....

Saaya is correct. AMD announced this years ago and Intel is coming with their version in a couple of weeks. Big whoop.

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Originally Posted by saaya

your dreaming! wake up already! :D

its an igp chipset on the cpu package, the same intel will launch in a couple of weeks for 1156... same thing!
you just move it from the mainboard onto the cpu package... there is no new driver model or anything like that...

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No new driver model obviously. So the whole thing is the most simpliest? Just a GPU moved to the same package and thats it?

For a few reasons it sounds somewhat strange. As the GPU has huge advantage over integrated FPU(parallelized workloads) of a CPU, what exactly is there which stops AMD from extending the ISA(for these parallel workloads) and use the GPU for floating point arithmetric? Of course, there is the issue between x86 and RVxxx ISA and defining a standard ISA for integrated GPUs would mean that future GPUs could not be used as APU due to differences in ISA. And as far as I can think, the ISA should be same between Intel and AMD integrated GPU for a standard ISA extension to happen.

Apart from that, in theory it should be very possible to run floating point operations on the dedicated cores of the GPU, granted that the ISA will be extended for this.

Even if nothing like that, ATI Stream on the APU and all GPGPU that way.

Whatever about whatever, but Zambezi is a very cool name for it! :p:

AMD needs a new(higher IPC) Uarch. badly. We all know this, this should be job one for the next latest Uarch. If BD isn't on par with INTC lastest, its a huge problem. And the seemingly delays to BD, Orochi or whatever is killing this company. I don't believe that AMD can withstand another Barcelona fiasco.

RussC

So AM3r2 (AM3+ or whatever you want to call it) probably won't work on an AM2+ socket like msi k9a2 plat? I would really enjoy that, but who knows if it will support ddr2 at that point. That would most likely be the real issue, that and bios support (I hope MSI steps up if that actually occurs).

i would rather stick with AVX for SIMD on cpu. putting a gpu on die is not that revolutionary.

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Originally Posted by Calmatory

No new driver model obviously. So the whole thing is the most simpliest? Just a GPU moved to the same package and thats it?

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i cant know this, but im 99% sure...

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Originally Posted by Calmatory

For a few reasons it sounds somewhat strange. As the GPU has huge advantage over integrated FPU(parallelized workloads) of a CPU, what exactly is there which stops AMD from extending the ISA(for these parallel workloads) and use the GPU for floating point arithmetric? Of course, there is the issue between x86 and RVxxx ISA and defining a standard ISA for integrated GPUs would mean that future GPUs could not be used as APU due to differences in ISA. And as far as I can think, the ISA should be same between Intel and AMD integrated GPU for a standard ISA extension to happen.

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they dont need to change the machine code of their gpu, if they translate things efficiently from x86 to gpu machine code, thatll work fine... in the end all x86 cpus do is translate x86 to risc pretty much... so yes, that would work... but then how do you use the gpu as a gpu? youd have to talk x86 to get through to it... and that wont work, unless you come up with a compiler that translates gpu machine calls to x86... thats no weekend project! :D

in theory you could have two interfaces for the gpu, one through the x86 decoder and one through the traditional gpu call to machine code decoder... that would work, you couldnt use the gpu for both at the same time or would have to find some way to balance and prioritize work... but yes, this would work...

but while this is all possible, it wont JUST happen...
you have to walk before you run... amd is standing right now...
the first step is moving the gpu on the cpu package, the second is moving it into the cpu silicon, the third is properly merging them, and that takes several steps actually until it works really well i think...

while its possible to skip step1 and go integrated into the cpu directly, its VERY unlikely that amd, with all their castrated budgets and way overworked engineers jumps from 0 to step3 of having the gpu integrated and merged to the cpu...

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Originally Posted by Chumbucket843

i would rather stick with AVX for SIMD on cpu. putting a gpu on die is not that revolutionary.

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+1

I'd like to see SIMD go to the extreme (1024-bit and more?).
Though I wonder where the point of diminishing return for SIMD is?


EDIT: I'd also like to see GPUs fix their double-precision FP units...

Thuban is barely an improvement over current Phenom II. It has two extra cores but it still have the same 6MB L3 cache and it use 45nm

And Thuban is simply a Desktop version of AMD Istanbul which according to reviews performed worse than Quad-core Xeon based on Nehalem architecture

I guess AMD will use Rivers names for BD CPU's (Zambezi and Llano are also cities, but that wouldn't make sense).


Purely speculating: If BD actually needs more than the 938 pins (31 x 31 - 23) in AM3, is it possible that AM3r2 have more than that?

Let's say the AM3r2 socket would have 35 x 35 -(>23) holes.

- An AM3 CPU would fit in the center of the socket, surrounded by two rows of empty holes on each side.

- An AM3r2 CPU would have a larger package and all ~1200 pins, and use the whole socket.


Is this too crazy? The biggest problem would be people who doesn't understand how to mount the CPU.

I'm not saying that BD must have more pins, but it's quite strange that AM3 (K10) CPU's will get the newer socket too, according to the link.
Why would they do that? That's the most weird piece of info in that link. Unless Google translate got it all wrong . .

The R6XX uarch is a VLIW design iirc

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Originally Posted by poke349

EDIT: I'd also like to see GPUs fix their double-precision FP units...

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what for? theres no game that benefits from double precision performance afaik...

and good point about the added pins...
they will need at least some extra pins for the video out signal...
hmmm but maybe there are enough unused pins in an am3 socket for that?

does anybody know how many unused NC pins there are in an am3 socket?

Can APU replace FPU x86 ? Can APU execute SSEx instructions ?

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Originally Posted by vietthanhpro

Can APU replace FPU x86 ? Can APU execute SSEx instructions ?

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AMD's Fusion might have something to do with this ;)

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Originally Posted by vietthanhpro

Can APU replace FPU x86 ? Can APU execute SSEx instructions ?

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What is the point of this? All the goodness of SSEx (x86 fpu isa isn't used in 64-bit OSes any more) is that it is executed inside CPU's pipeline (speculative & out-of-order). If you send those instructions to the external execution unit you will probably meet serious performance penalties. Even if this external execution unit can execute much more instructions per cycle then internal fpu, it doesnt realy help because of very limited ability for the code parallelization in the current apps.
In my opinion APU is something like Cell's PPE - small processor with its own simple ISA and wide vector unit (or array of execution units). Then the purpose of main core will be to send tasks to those APUs and programmers will need to deal with writing small programs using some proprietary ISA for those APUs (not really a beloved job for a Cell programmers). Or it can be x86 compatable (something like Larrabee integrated in CPU core).

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Originally Posted by saaya

what for? theres no game that benefits from double precision performance afaik...

and good point about the added pins...
they will need at least some extra pins for the video out signal...
hmmm but maybe there are enough unused pins in an am3 socket for that?

does anybody know how many unused NC pins there are in an am3 socket?

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Games don't, but GPGPU do.

I've had a number of requests for a CUDA version of the Pi-program in my siggy. Poor DP-FP is one of the reasons why I can't do it right now.

Here's the translation I was talking about.

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In 2011, AMD plans to bring the power users, the beginning of Scorpius, which consists of 32 nm technology in the preparation of the Zambezi-koodinimellisestä processor, featuring four or more cores. At the same time the current position AM3 processor will update apparently second-generation version of R2.

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Too early to see the whole picture here, but since they have everything from low end Llano CPU's to Zambezi, I just can't understand why they're keeping the K10 AND giving it the new socket, if it already works as it is in AM3r2?

A similar situation was when 65 nm Agena showed up. But back then, AMD needed their old K8's since they didn't have any new K10 dual cores yet. Still, they never gave the K8's the AM2+ specs, and nobody missed it anyway.

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Originally Posted by Mats

I just can't understand why they're keeping the K10 AND giving it the new socket, if it already works as it is in AM3r2?

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^^Probably because the new Llano MPU will require more pins due to integrated GPU so the AM3r2 socket won't be enough.

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Originally Posted by poke349

Games don't, but GPGPU do.

I've had a number of requests for a CUDA version of the Pi-program in my siggy. Poor DP-FP is one of the reasons why I can't do it right now.

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so instead of improving graphics performance on their new gpus, you WANT nvidia and ati to INSTEAD use transistors and time to improve the DPFP performance so we can run superpi on a gpu... :slap: :P

sounds to me like am3 is fine for non igp cpus, but for igp cpus they need a new/revised socket

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Originally Posted by saaya

so instead of improving graphics performance on their new gpus, you WANT nvidia and ati to INSTEAD use transistors and time to improve the DPFP performance so we can run superpi on a gpu... :slap: :P

sounds to me like am3 is fine for non igp cpus, but for igp cpus they need a new/revised socket

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Obviously not for benchmarks...

But there's about a billion useful things out there that require DP-FP and are highly parallelizable.

Seeing as how nvidia has been pushing for GPGPU for a while now... it will probably help them out a lot if they improved their DP-FP.

I'm guessing AM3r2 is AM3 with HyperTransport 3.1 (6.4 GT/s). That's one reason I feel why it's AM3r2, and not "AM4". So I'm also guessing it's going to be pin-compatible.

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Originally Posted by poke349

Obviously not for benchmarks...

But there's about a billion useful things out there that require DP-FP and are highly parallelizable.

Seeing as how nvidia has been pushing for GPGPU for a while now... it will probably help them out a lot if they improved their DP-FP.

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ok, thats a bold claim there, and its based on speculation... and even if thats true, and there IS a lot of demand, then it doesnt mean its easily portable to gpu, and even IF its easily portable, it still doesnt mean its going to happen...

building a product for applications that dont exist is ridiculous... im surprised nvidia keeps blowing money on it before there is a propper infra structure... thats not how it works...

you either pick one or several existing tools and then accelerate your hardware for it, or you cooperate with the devs and build the infra structure together, they do the software you do the hardware, or you do both, software and hardware.

nvidia just creates the hardware and then waits for the software to come out of nowhere... except for some few tidbits of code they wrote for devs and then lets them use it for video transcoding and image processing...

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Originally Posted by informal

^^Probably because the new Llano MPU will require more pins due to integrated GPU so the AM3r2 socket won't be enough.

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Yeah I'm sure Llano needs more pins, but that doesn't explain why they're putting old K10 cores in AM3r2 packages when they have a whole new lineup coming, which the text says.
We're talking about different things here.

Besides, that pic doesn't say that Llano uses AM3r2, tho I hope it does.

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Originally Posted by poke349

Obviously not for benchmarks...

But there's about a billion useful things out there that require DP-FP and are highly parallelizable.

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just name at least 3 which comes to your mind... then speak...

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Originally Posted by blaH

just name at least 3 which comes to your mind... then speak...

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Finite Element Analysis
Matrix Inversion
Matrix Multiplication
Fluid Dynamics Simulations
Thermal Dynamics Simulations
Fractals
High precision Mandelbrot
High precision Arithmetic
Fourier Analysis
Fourier Transform
Signal Processing (not sure if this requires DP though)
Discrete Event Simulations

You just named some buzzwords thats all, matrix mul can be anything int, sp, dp, so now name actual apps which uses them and you use them daily...

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Originally Posted by poke349

Obviously not for benchmarks...

But there's about a billion useful things out there that require DP-FP and are highly parallelizable.

Seeing as how nvidia has been pushing for GPGPU for a while now... it will probably help them out a lot if they improved their DP-FP.

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fermi has a peak of 768DP GFLOPS.:D thats 8x faster!

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Originally Posted by blaH

You just named some buzzwords thats all, matrix mul can be anything int, sp, dp, so now name actual apps which uses them and you use them daily...

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The market for GPGPU probably won't be on the consumer side as much as the industrial side. You won't believe how much companies are willing to pay to make their simulations go 10x faster. Especially when there's money to be made...

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Originally Posted by Chumbucket843

fermi has a peak of 768DP GFLOPS.:D thats 8x faster!

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Woah... that's serious...

heh no argue there, but simply from my as consumer perspective DP is nearly useless

I want Thuban comes out Q1 2010...would like to double the core counts for my Phenom II X3 720BE (Phenom II X6 xxxBE??)

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Originally Posted by Chumbucket843

fermi has a peak of 768DP GFLOPS.:D thats 8x faster!

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I thought there claiming only 2.5 better though :shrug:

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Originally Posted by Jamesrt2004

I thought there claiming only 2.5 better though :shrug:

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fermi whitepaper says around 4x faster effective. it really depends on what you are doing though. the power point slides arent really an effective way to combat 58xx.

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Originally Posted by Chumbucket843

fermi has a peak of 768DP GFLOPS.:D thats 8x faster!

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Yep that is quite fast but the 5870 X2 is suppose to have around 1088 Gigaflops and if we look at a cheaper alternative the 5850 x2 may have around 838 Gigaflops. Now those value seem unrivaled by GF100/GT300 and only a GX2 version which can score around 15xx DP points can kill them. In terms of cost i think 5850 x2 will rival GT300/GF100.

BTW For people who are interested 5870 has 544DP and 5850 has 419DP

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Originally Posted by largon

Barcelona (city), Deneb (star), Thuban (star), Zambezi (city)...
Uh-oh. Ominous.

And I wonder if AM3 rev2 will be a PGA or LGA...
And why they didn't go LGA with AM2.
*shrug*

But I hereby demand they go 192bit memory on Bulldozer - I want my 6 DIMM slots on desktop boards.

APU, as in "accelerated processing unit". GPU-on-CPU. Few Bulldozer cores with a low end GPU on-die.

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Zambezi is a river. Borders Zambia and Zimbabwe. In Africa.

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Originally Posted by ndlar

Zambezi is a river. Borders Zambia and Zimbabwe. In Africa.

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Welcome to XS boards bro...

But this^ thread is old, you necro'd it back to life as most these posts are 7-8 months old.

Well, the subject is pretty interesting. Would be nice to hear more things about Scorpius/Zambezi.

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Originally Posted by saaya

ok, thats a bold claim there, and its based on speculation... and even if thats true, and there IS a lot of demand, then it doesnt mean its easily portable to gpu, and even IF its easily portable, it still doesnt mean its going to happen...

building a product for applications that dont exist is ridiculous... im surprised nvidia keeps blowing money on it before there is a propper infra structure... thats not how it works....

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saaya, there is a lot of demand in HPC clusters for GPGPU computing.
and re:applications, they are always customized for these jobs, climate modeling, oil exploration, etc.

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The Nebulae system which uses 4,640 Tesla chips, consumes about 2.55 megawatts compared to about 7 MW for Jaguar.

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eetimes

there is also one other chinese supercomputer that uses ati radeons:

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and 5120 AMD RV770 GPUs [2560 ATI Radeon HD 4870 X2 2GB cards]. Together, 6144 Intel CPUs and 2560 AMD GPUs reach a theoretical speed of 1.206 PFLOPS.

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bsn*

hardware is always ahead of software, as history shows.
i think youre just off your game today. coffee?

http://www.4gamer.net/games/110/G011...093/TN/005.jpg

???

that last roadmap doesnt seem very legit at all

i just want me a nice 8 core bulldozer for my rendering and i will be a happy puppy :D

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Originally Posted by Florinmocanu

i just want me a nice 8 core bulldozer for my rendering and i will be a happy puppy :D

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Bulldozer with 8 cores/16 threads, it'd be great :yepp: considering how Intel is doing good with their HT :p:

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Originally Posted by amdsempron_xs

Bulldozer with 8 cores/16 threads, it'd be great :yepp: considering how Intel is doing good with their HT :p:

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Bulldozer for desktop is 8core/8thread chip,no SMT in version 1.

pwease explain?

I thought "CMT" "SMT" (!?) was intragral to the design of the Ccore/"Module"

CMT is not the same as SMT. Bulldozer IS Clustered Multithreaded design,each module(or "super" core) is composed of shared and discrete structures inside(shared front end,L2,shared FPU with a method similar to intel's SMT,discrete integer cores with discrete L1 caches).While BD cores share some parts and have dedicated execution units per core/thread inside the super core/module,intel's Westmere/SB cores dynamically share resources within single core(entire pipeline).It is speculated that one BD module will be smaller than one SB core but will have greater throughput.

Sure that's how I understand it. You say Bulldozer will have no SMT in version 1.. So looking at it the other way, what will the next revision have then?

Well it is 8 cores/8threads now,but AMD didn't say they won't bring SMT at some point in the future. Version 2 may have it(SMT,each integer mini core being 2 threads capable) and may have eager execution wrongly called "reverse HT" (done entirely by hardware and assisted by software). Also there could be a GPU in the place of the FPU we see in Version 1 :).

Ah OK thanks. For a minute i thought they'd chopped a BD module in half or something ;) . Sounds interesting, as does the upcoming fight between It and SB

Yeah it will indeed be interesting clash :). Launches won't happen at the same time,but 2011 will see both designs on the market.I'd say server will be a win for AMD,while desktop a slight advantage for intel(depending on the clocks too).

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Originally Posted by informal

Also there could be a GPU in the place of the FPU we see in Version 1 :).

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This makes me believe that the second generation BD will use the Llano socket (or its successor) since it got GPU and probably PCIe, and that AM3r2 will be the last AM socket.
That is, if AMD want to use only one desktop socket, which I hope.

What do you think?

I think Llano socket is to small for highend Bulldozers.

who knows.

Llano = 4 32nm K10 cores + GPU.
Bulldozer = 8 BD cores. I think they can use the same socket, the gpu in llano should be quite a big part of llano.

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Originally Posted by Florinmocanu

who knows.

Llano = 4 32nm K10 cores + GPU.
Bulldozer = 8 BD cores. I think they can use the same socket, the gpu in llano should be quite a big part of llano.

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Exactly, especially since the Llano socket can be made with BD support in mind.

The AM socket series have no PCIe or IGP support, so to me looks like a dead end.
So why not use the same socket for both Llano and the next BD?

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I think Llano socket is to small for highend Bulldozers.

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Do you know how big it is? I haven't seen it.

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Originally Posted by Mats

This makes me believe that the second generation BD will use the Llano socket (or its successor) since it got GPU and probably PCIe, and that AM3r2 will be the last AM socket.
That is, if AMD want to use only one desktop socket, which I hope.

What do you think?

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There is a chance BD version 2 may use Llano's socket,but it's still early to say anything.Depends what kind of new stuff AMD plans to bring in.If they opt for higher than dual channel IMC,then the chances are slim.

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Originally Posted by informal

If they opt for higher than dual channel IMC,then the chances are slim.

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Unless they thought of that too.:yepp:
AMD probably learned a lot from the AM series, so they must have thought twice before finalizing the new socket,
and remember to include whatever they might want in the future, even if it's just represented by reserved pins for now.
Again, that is, if they want to use only one desktop socket.

bulldozer will have quad channel that's already known.

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Originally Posted by demonkevy666

bulldozer will have quad channel that's already known.

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On desktop it won't,it will be DualCh. DDR3-1866.Server chips (Magny Cours) already do have QC memory controllers and in order to be socket compatible,BD variants of server chips(16 core ones) will need to have the same QC memory controller support.

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Originally Posted by informal

Well it is 8 cores/8threads now,but AMD didn't say they won't bring SMT at some point in the future. Version 2 may have it(SMT,each integer mini core being 2 threads capable) and may have eager execution wrongly called "reverse HT" (done entirely by hardware and assisted by software). Also there could be a GPU in the place of the FPU we see in Version 1 :).

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they will have to include an x87 fpu otherwise it would not be backwards compatible.

Yeah they must include it,maybe as a part of the new GPU?