http://www.xbitlabs.com/news/other/d...022211442.htmlQuote:
Originally Posted by XbitLabs
STRICTLY AMD ONLY PLEASE :), ty to Zornundo for finding this as well :)
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http://www.xbitlabs.com/news/other/d...022211442.htmlQuote:
Originally Posted by XbitLabs
STRICTLY AMD ONLY PLEASE :), ty to Zornundo for finding this as well :)
I'm not going to allow bashing of AMD of any kind or any sarcastic or tongue in cheek posts of anykind, or any fanboy comments for that matter.
Let's keep it clean.
I have a considerable amount of patience, but it has its limits, and considering that XS News is the second most updated and frequently visited section on XS, I would think people would like to keep their access to it.
__________________________________________________ ___________________________________________
Whats interesting here is that AMD does have plans to come out with an octal core around 2009, with one on MCM and a native octo core as well.
I'll try to post a roadmap of this when I can, though I'm hoping 45nm will bring some architecture changes as well, perhaps to lose that 3ghz barrier X(
Perkam
I don't understand a bit.
Does it mean they want to release first 45 nm CPUs on market in H1 2008 or they'll just start producing and release it in H2 2008/H1 2009?
Ramp basically means they'll start equipping facilities for 45nm in Q1 2008 for production in q4 2008 and retail in q1 2009.Quote:
Originally Posted by bedlamite
Perkam
Fabtechs take.
Quote:
AMD 45nm ramp revisited
Oct 22, 2007 at 10:26 AM
News from last week’s AMD conference call that told us the company would start production of 45nm microprocessors in the first half of 2008 shouldn’t be looked at from the point of view of ‘volume production.’ The message that should be taken from the news is that at some time in the first six months of next year, AMD may well have a small amount of devices entering the supply-chain.
...
AMD has one big advantage over Intel at the 45nm node, namely the ability to push out the adoption of high-k dielectrics and metal gates until the 32nm node due to the use of SOI wafers.
...
The 45nm migration should start ‘mid-year,’ but with new immersion tools required, both qualified and ramped, we would still expect ‘volume production’ to be in 2009, not 2008, with a significant amount of Fab 36 production switched to 45nm by 2Q09.
AMD has not been able to bring their 65nm process to the same level as 90nm. AMD's high-end CPU are still manufactured on 90nm. The process shrink from 90 to 65nm has hindered clock speed. Why do you think the shrink from 65 to 45nm would help clock speed?Quote:
Originally Posted by perkam
To date Barcelonas < 1.8GHz are rare; I have never seen a 2GHz for sell. I'm just wondering how you reason AMD going from, struggling to produce 2GHz(quad) @ 65nm to 3GHz(quad) @ 45nm is likely?
Well I can't say much as it is, but retail Phenom X4s coming this November/December will reach current k8 speeds with ease.Quote:
Originally Posted by Sup3rman
Salvadar, no one's expecting these before 2009 as it is, which is fine by me as long as they improve steppings and yields on Barcelona throughout 2008.
Perkam
Will they ever make a dual-core Barcelona that doesn't rely on having two cores disabled? That'd be the first step towards making money.
what i really dont understand
i know the benifits of SOI,your Cs and Cd decreases drammaticly and Id is increased about 30%
=> so this should be good
But why is everyone having trouble with SOI then?
can someone please fill me in
It's starting to look up for AMD :D
@Bobsama, I thought that dual core Barcelona/Phenom was a standard dual core (maybe with some quads with 2 bad/disabled cores).
@Sup3rman, the shrink from 90nm to 65nm was just a shrink and yeah isn't yielding as good apparently as 90nm (though it has gotten much better). But if AMD has been putting more focus on 45nm that might be the reason why 65nm suffered some, they devoted more time/resources to getting 45nm perfected. Just throwing that out there as a possibility.
Positive and Negative about AMD are fine, as with other threads, lets just not invite the blue team over as this isn't about them :)
I have tried multiple times to ask Mr. Poncho, who happens to be an Intel employee, to mind his own business so as not to derail the thread with sarcastic and jeering posts but he doesn't seem to respond.
He is an intel employee after all and Fugger has such good relations with Intel, I can't forcefully throw him out, so there's little more I can do. Some people just can't respect the wishes of others.
@Bobsama, native dualcore k10 is codenamed Kuma and is coming end of q1 2008.
Perkam
AMD should have an edge with 45nm as they and IBM have been working on 45nm for quite some time...Quote:
Originally Posted by perkam
i cant wait , 2x3870's a Phemon(anom) in a sweeet new Am2+ mobo would be awesome.
even tho intel have top cpu's atm i'm diggin the cheap prices amd is sellin the 6000+ unlocked multi and such , it works out 80 euro cheaper than an e6600 :D
gl amd , you'll need it :up:
it's looking better for AMD
Q1 09 would fit in nicely for a scheduled hardware update (AMD (past) to Intel (present) & back to AMD (future)).
perkam, so it's almost certainly SOI still then? I think SOI is needed for any future integration of ZRAM (possibly in Fusion maybe?) otherwise that money they threw at it would be wasted.
Honest question and not jeering. Will Kuma or Phenom X2 really be Native Dual Core or Phenom X4 with two dead cores? Seems to me that pressing out two and four core packages are counter productive given the failure rates of even good yields. We know both AMD and that other company has a propensity to lie and try to turn failure into triumph:down: Look at what AMD said about Tri-Core or X3? The truth would have easily been accepted.Quote:
Originally Posted by perkam
I hope I'm wrong but AMD will have to show me this improved Process. After the last two years their word (and many others BTW) is worthless IMHO.:rolleyes: I hope like hell they get it right. Without Competition we'll sooner or later go back to the Days of X2 across the board high @$$ed prices. Simple Supply and Demand dictates that.
I read the whole thread before it was changed by Perkam. He said nothing wrong. Poncho you are acting like an idiot. Time would prove whether what Perkam said is true or not. Your coming into the thread with a clear trolling attitude is pathetic...Quote:
Originally Posted by FLG_Poncho
Anyway, here's to hoping Amd can get 45nm going well, they certainly need it...
Ply
The low model dual cores will be X4 with 2 dead cores, but that will probably change once yield is up to where it should be on X4s...Quote:
Originally Posted by Donnie27
No more useless posts or discussions of mod requests. This is a public forum - not kindergarten. If you don't have anything interesting to say - don't say anything
To be quite honest, I could give a rats az who is or is not someone who works for any company or if they are a standard member of this forum.
Post the wrong crap you will receive the appropriate 'reward'.
If someone has a problem with a member of the XS Staff, take it to an Admin or Fugger directly.
Do Not bash any moderator in the open forum, I don't care if the moderator was/is wrong, YOU will be the one to receive the first reaction.
it'll be the same as with K8 Dual core and single (E6 venice cores were manchesters with 1 core disabled and E3 native single cores ;) )Quote:
Originally Posted by Donnie27
no chance amd gets enough "faulty" cores to supply a whole DC product line.
getting more and more interesting, and one side note:
65nm has surpassed 90nm with the ne G2 revision brisbane chips (used in be and 5000 black edition)
OK, I'll bite. Are you claiming that Phenom will come out this year with the 3.2GHz stock speeds, or are you talking about how well they will overclock?Quote:
Originally Posted by perkam
Take it how you wish. I have full confidence that K10 can get up to that speed, but there is no evidence as to how well it will OC...Quote:
Originally Posted by Periander6
Yields should be pretty good, which is why I said AMD shouldn't have to sell many half dead X4s.Quote:
Originally Posted by generics_user
Now please go back and look at where you quoted me LOL?Quote:
Originally Posted by DeathReborn
Quote:
Originally Posted by Donnie27
AMD is nowhere near 45nm=P
I post tgdaily's article first and this post gets stickied? WTF?Quote:
Originally Posted by GoThr3k
I think I posted AMD's reply to Fabtech's original article in the thread that got deleted:Quote:
Originally Posted by Salvador
Advanced Micro Devices is not delaying 45-nanometer manufacturing, according to the company, which is trying to correct an erroneous report on a blog.
"We are still on track to produce the first (45-nanometer) products by mid-2008," said Gary Silcott, an AMD spokesman. The company will have "pretty good volumes" of 45-nanometer chips by the end of 2008, he added.
The also claim that the problems with Barcelona have been with finalizing the chip design, not with their manufacturing process:
Analyst
Dirk, I had a question for you. On the Barcelona ramp you said it materialized a little slower than anticipated and your speed grades haven't been targeting the top end right off the bat. There has been some speculation that perhaps your yields on 65 nanometer specifically as it relates to Barcelona is the issue here.
Any comments you would want to make or a different explanation you would want to offer up on why Barcelona's speed grades aren't as fast as you would like them to be?
Dirk Meyer
First of all, I'll say that the basic silicon yields of Barcelona are right where we expected them to be. They're right line on line with the previous 65 nanometer products from a deep activity and overall yield perspective.
The issue has been simply one of tuning the design to the technology so as to support a high volume ramp. It is that particular issue that caused us to take a few extra weeks before we turn on the high volume ramp in the middle of this quarter.
Analyst
In other words, there's nothing endemic to your process technology that is problematic or which might spill over to your 45 nanometer ramp?
Dirk Meyer
No. The minor issues we've been experiencing have nothing to do with the process technology or the manufacturing capabilities. It is all a matter of wedding the design to the technology so as to be able to ship in volume.
Analyst
Anything else you could share along those lines in terms of details as what the issues have been in wedding your designs with your process technology?
Dirk Meyer
I don't think in this forum.
badass, i hope AMD can put out some good clocking 45nm chips :)that would make my day seeing them put it back on Intel cus competition is key and prevents stagnation within the industry which in the end always benefits us :D
If AMD can make a production quality < 2.6GHz quad core this year why would they prefer to sell it as a desktop CPU instead of a high margin server CPU?
I am assuming the barcelona and phenom cores are the same? If my assumption is true then why the big difference in clock speed between barcelona and phenom?
They are making < 2.6GHz chips right now. 2GHz < 2.6GHz ;) :p:Quote:
Originally Posted by Sup3rman
If you mean > 2.6GHz (greater than), well AMD usually doesn't release the fastest part first, also leaves more "breathing room" so to speak in their server chips and binned them lower even if they were capable of higher speed (which is partly why the older s939 opterons for example would usually OC very well). Why they do I'm not sure.
actually the reason AMD NOR Intel releases their top bins at first is because the yields are not perfect and take months before improvements are availableQuote:
Originally Posted by SparkyJJO
nobody cares to explain why SOI is so difficult on 45nm? :(Quote:
Originally Posted by GoThr3k
Too technical for me to know or answer :p:Quote:
Originally Posted by GoThr3k
The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10 - 15% increase to total manufacturing costs but outside of that, there is little reason for difficulties outside of specific implementation details (Z-Ram for Example)Quote:
Originally Posted by GoThr3k
savantu explained it/posted a link, but it got deleted... :rolleyes:Quote:
Originally Posted by GoThr3k
so the use of SOI shouldnt be the reason for the high leakage on the 65nm parts?Quote:
Originally Posted by nn_step
How can your article dated 18th of October, be AMDs answer to the fabtech article i posted dated 22nd of October?Quote:
Originally Posted by oldblue
please,don't act like a child,amd said clock per clock,and in some workloads.....Quote:
Originally Posted by MR_SmartAss
if your only intention is to flame and to cause a amd vs intel war,please go spam another thread
its about 45nm here....
Show us that official claim from AMD?Quote:
Originally Posted by MR_SmartAss
Why am i not surprised :)Quote:
Originally Posted by MR_SmartAss
Btw check AMD section, K10 seems to overclock afteral and seems to scale not linear afterall...:up:
First link : http://www.news.com/AMD-Go-to-Barcel...3-6152645.htmlQuote:
Originally Posted by MR_SmartAss
"We expect across a wide variety of workloads for Barcelona to outperform Clovertown by 40 percent," Allen said.
To blame AMD because this sentence has been transformed to "We expect across [a wide variety of workloads for] Barcelona to outperform Clovertown by 40 percent," Allen said, it's a little lame.
..Quote:
Originally Posted by Hornet331
Back on topic :
http://www.semiconductor.net/article/CA6464480.html
As late as mid 2007 AMD was still debating what to do at the 45nm node and some think they will greatly reduce the process gap with Intel in 2008. LMAOQuote:
Bulk or SOI? AMD Considering Its Options
David Lammers, News Editor -- Semiconductor International, 7/31/2007 12:30:00 PM
Advanced Micro Devices (AMD, Sunnyvale, Calif.) is still mulling whether to use silicon on insulator (SOI) or bulk silicon technology for its future high-end and mobile products.
“This is in the exploratory phase, and AMD has not made any statements about when it would make a decision to produce next-generation processors in bulk or SOI,” a spokesman said, adding that AMD technologists are asking questions that “are not answered yet, so we are leaving the question open as they look at the issues.”
During a July 26 meeting, AMD executives described the company’s technology and product roadmaps. Doug Grose, senior vice president of manufacturing and supply chain management, said that AMD is “evaluating the mix” of SOI and bulk technologies for 2009 and beyond.....
And for SOI challenges :
http://www.semiconductor.net/index.a...A6464480#69173
Quote:
One of the major differences between the SOI and Bulk technology for the 45nm and beyond is to control the electostics or the short channel effects. For the bulk technology used by Intel the quantum confinement of carriers is controled by a combination of Hallow source/drain implant, and retrograded channel/substrate doping.
On the other hand, for the SOI technology the quantum confinement of carries in inversion layer is carried out by physically reducing the SOI thickness, Tsoi by narrowing the space between the gate oxide and the buried oxide. To mitigate the short channel effects, 45nm SOI may require 50nm~40nm Tsoi, 30nm~20nm Tsoi for 32nm, and 10nm or less Tsoi for 22nm technology. Such a thin Tsoi causes significant carrier mobility degradation and increase in threshold voltage, Vt. Furthermore, for the scaled devices, the strain induced mobility enhancement techniques become less effective.
This is particularly more so for the thin SOI technology simply because in such a thin ~10nm junction and isolation depths, and channel inversion layer thickness it is extremely difficult to implement GeSi S/D junctions and a large lattice mismatch induced by the relaxed Ge-Si substrate in the channel.
Even for the 45nm SOI technology, the manufacturability of the strain induced mobility enhancement techniques used for 90nm and 65nm may not be feasible. In this respect, the SOI technology for the 45nm and beyond has a significant disadvantage over the bulk technology. IBM and AMD are at the crossroad today to determine extenderability as well as manufacturability of the SOI technology for 45nm and beyond.
The conversion from the SOI to the bulk 45nm technology node has enormous technological and manufacturability challenges. This is because IBM and AMD do not have the required learning experiences such as process, design, reliability and device yield gained from the 90nm and 65nm bulk technology development and mannufacturing. Furthermore, two major new materials were introduced in the bulk 45nm technology: the thermal oxide, SiO2 that was used for 40 years is replaced by HfO2, and the polysilicon gate that was used for over 30 years is replaced by the metal gate.
Today Intel is the only company that is manufacturing the bulk 45nm. If that is true, Intel has enormous advantages over its competitors, particularly if IBM and AMD have to adopt the 45nm bulk technology. This is because Intel must have resolved most of the device, process, reliability, and manufacturability issues as a result of introduction of the new materials and processes.
When the new materials and processes like HfO2, metal gate, and their new processes are introduced, new or unknown faiure mechanisms will be also introduced. Therefore, it is crucial to design test structures so as to bring out the unknown failure mechanisms for early detection, and develop effective E-test and reliability test screens. Such experiences gained through the 90nm and 65nm bulk technology development cycles will give an edge to Intel in successful development of the 45nm technology and beyond.
@ Savantu, could you summarize what the article means for AMD? They do have a year (all of 2008) to make that decision and face those challenges, based on which decision they make.
@ Zornundo, check first post :)
@ Periander, well, the biggest disconnect with respect to AMD's Phenom X4 today is that the general public don't have access to results that a limited number of people do.
@ Cooper, ty :bows:
All I can say is, yes, you'll see it perform quite well with some new "enhancements" with respect to ocing them.
Perkam
Let's hope so. Same process, same size as Brisbane and we've seen some Brisbanes hitting 3.5ghz on air; no reason to believe that the quads can't reach upwards of 3.0 ghz as well! It'd be nice to have an AMD quad setup under my Christmas tree this year. :up:Quote:
Originally Posted by perkam
Yeah, I can see where that's confusing. It was the reply to Fabtech's "original" article. Fabtech originally speculated that there would be no 45nm from AMD until 2009, and AMD corrected them. Fabtech somehow didn't see AMD's response before their second article (the one you posted), so they only talked about the conference call. They missed the fact that AMD expects to have "pretty good volumes" of 45nm by 2H 2008.Quote:
Originally Posted by Salvador
I guess it depends on what you mean by "produce." It sounds like there won't be any chips available for sale until mid-2008 (which could very well mean September). But they are making 45nm chips now, and expect to ramp production in 1H 2008:Quote:
Originally Posted by MR_SmartAss
Dirk Meyer
We're looking forward to ramping 45 nanometer product production in the first half of next year
...
First, we are on track relative to having basic yields in place in our factories on material that we're running today. We're building 45 nanometer microprocessors as we speak and those two facts give us increasing confidence in the public statements we've been making for some time around our intent to be starting our production ramp of 45 nanometer processors in the first half of next year.
I think it's less that they "missed" what AMD said and a lot more they simply don't find AMD's statements credible. Throughout AMD's 2006 conference calls they repeatedly stated that they would be shipping 65nm K8s before the end of the year. Although Brisbane was launched in December, it was pure paper until late January.Quote:
Originally Posted by oldblue
Things aren't so simple.Quote:
Originally Posted by perkam
You have 2 main types of leakage in a transistor : gate leakage and subthreshold.
Subthreshold was the bigger one in 130 ,90nm but at 65nm gate leakage took over.SOI helps with subthreshold leakage and a few other things, but has no effect on gate leakage and brings a different set of problems.
The problem : once you get to 65nm and lower gate leakage increases dramatically.As a result , SOI's usefulness in reducing leakage is getting smaller and smaller.Also you can fight subthreshold leakage with circuit design techniques ( does Intel's Restrictive Design Rules ring a bell ? )
How do you fight gate leakage ? With metal gate and high-k dielectrics.These 2 things become a must have for a successful 45nm process.AMD lacks both at the 45nm node AFAIK .Intel virtually pushed back the problem by decreasing gate leakage by a factor of 10.
Now go back to my previous post and reread the comment on SOI problems with carrier mobility degradation and threshold voltage.
Basically it boils down to : AMD is FUBARed if they don't do something fast.Basically they are waiting for IBM to pull their a** out , yet IBM suffers from the same problems.
To give you a hint on AMD's problems , let's look at their 65nm process. Besides the official PR BS with "most advanced , high yields" the process is significantly different from what was expected.
In 2005 when AMD presented their tech papers on their 65nm process they reported a 1.2 nm thick oxide (the same thickness as Intel's 65 nm), yet Semiconductor.com reported (I saw at EETimes) just recently reversed engineered a barcelona chip in which AMD's oxide thickness was actually 25% thicker than Intels.
http://www.eetimes.com/news/design/s...leID=202100946Quote:
...The transistor performances of Intel's Woodcrest and AMD's Barcelona appear to match fairly closely, with the Barce- lona's gate leakage about half that of the Woodcrest. This is not so surprising, as Intel uses a 25 percent thinner gate dielectric....
The 65nm node was the 1st process node where gate thickness stayed the same : this was done to keep gate leakage under control.
AMD even increased their oxide thickness from 1.2nm (90nm) to 1.5nm for 65nm in order to keep leakage under control.
Does this help with leakage ? Yes. Does it diminishes transistor performance ? Yes. Basically , their 65nm is excellent power wise , but clocks like sh*t.If you wonder why 65nm K8/K10 can't hit higher clocks , look no further.
But what do you do at 45nm ? Intel didn't bother with SiO2 , say hello to Hafnium which solved the problem , but AMD will have massive problems with oxide thickness/leakage/voltage as they try to hit clocks at 45 nm.
All of this is pretty much speculation even by the experts. I'm not one of them and none of us probablya are, so I'll just wait and see.Quote:
Originally Posted by savantu
I do know as far as clocking, I've seen a 5000+ hit 3.7G on air and a Barcelona get a 400mhz oveclock with stock votage on air. Maybe the experts were wrong about AMD's abitlity to get higher clocks.
The discussion is not about the current 65nm parts, its about the upcoming 45nm parts.Quote:
Originally Posted by PhilDoc
Also its nice that amd finaly has masterd its 65nm process, thought it should have been there from the start, not a year later.
Savantu,
You seem to know alot about soi vs bulk silicon. Do you work for a semiconductor company? You should visit scientias blog and discuss this material there.
Phildoc,
Savantu said 65nm soi clocks like s**t. I believe him. 3.7Ghz on 65nm-must be fake.
I know its about 45nm, but SOI is part of the equations and how they do with 65nm is also part of it. The 3.7G is real just look at the AMD forum and you can read all about it.
Here just to save you some time. http://valid.x86-secret.com/show_oc.php?id=253783
:) :)
And compared to competitors it is what?Quote:
Originally Posted by grunge100
SOI today is a big bleeding wound on AMD. It was the chance they took. Bulk vs SOI is an easy question for 45nm and down. At 130nm and 90nm it was another ballgame.
I personally dont like AMDs work with IBM on this area. IBM tends to go exotic rather than practical in many cases. And there just aint room for that with a fierce competition. Specially not when you are also with your head down in the mud.
Those 2 things aren't exclusive.Quote:
Originally Posted by grunge100
Individual OCs say virtually nothing about what AMD can crank out of the 65nm process.
AMD's 65nm process was optimized for low power , not speed.As a result 65nm K8 isn't able to match 90nm K8 in top frequency , at least not yet( probably never will ) .
As a rule of thumb a shrink is able to do 20% better than the previous process size at the same power.
3-3.2GHz 90nm 125w -> 3.6-3.8GHz 65nm 125w
AMD is stuck at under 2.8GHz.
See more here :http://www.eetimes.com/showArticle.j...leID=196701745Quote:
Interestingly, this first application of 65-nm technology was designed not to improve performance over the previous, 90-nm Athlon, but to reduce power consumption.
The tradeoffs involved in keeping leakage under control = slow transistors speed , difficult to reach higher frequencies.
Dirk Meyer says something interesting :IMO , they cover the flaws of the process with the design of the chip , as to minimize them. ( same as Thoroughbred days , they added more layers , etc )Quote:
The issue has been simply one of tuning the design to the technology so as to support a high volume ramp.
K10 has excellent power usage when running at low speed , once you crank up the speed the power usage goes through the rough ( slower , thicker transistors need more voltage , remember the 1.52V 2.5GHz sample ? ).
Hmm.
Are CPU transistors realy so different from GPU ones?
New Radeons 38x0 will be 55 nm.
Isnt it at least a bit simmilar?
gpus arnt produced by amd fabs, they are produced by TSMC or UMC, which use a different tech.
Savantu,you can't expect that uarchitecture that was originally designed for 90nm process and introed at 130nm to scale up to 3.6-3.8Ghz at 65nm.It isn't only the process that matters,but as D.Mayer recently said (about K10),"wedding the design to the process".Quote:
Originally Posted by savantu
So no,nobody ever expected K8(in X2 variant even less!) to go to 3.6-3.8Ghz ,125W on 65nm process.There are other limitations in K8 that would come into play,it's not the process alone.
The process is much different. CPUs require a much higher quality process, more metal layers and so on. I dont even think TSMC would be able to make a standard 65nm K8/K10 or Core/Core2.Quote:
Originally Posted by bedlamite
55nm is also just an optical shrink of 65nm and mainly a cost improvement.
Which they pass on to customers thankfully :) There are also some architecture improvements Shintai, be they as insignificant as you wish, the addition of UVD, DX10.1 and SM4.1 are big marketing cues that AMD will use to their advantage.Quote:
Originally Posted by Shintai
Perkam
Thats kinda funny.Quote:
Originally Posted by perkam
They sure keep their share...and abit more ;)Quote:
The firm turned in net profits of NT$30.37 billion on revenue of NT$88.96 billion for its third quarter, which ended the 30th of September last. That gave TSMC a gross margin of 45.8 per cent and a net margin of 34.1 per cent.
And for those comparing it with Intel/AMD. Remember there is no chip R&D needed. And their fab volume is quite bigger.
Yes,but those weren't as radical changes as pipeline changes would be(even K10 hasn't changed much in that respect) .AMD were sticking to the original plan and as you said,tweaked the design to the smaller node when it was possible to net further clock/power benefit.Quote:
Originally Posted by MR_SmartAss
I'm fully aware of that , however ,as ceteris paribus a shrink will offer some frequency gains.Quote:
Originally Posted by informal
I'm really interested to see what frequency will K10 reach since its pipeline is basically the same as K8.The sudden jump in power consumption from 2.3/2.4GHz to 2.5/2.6GHz is indicative of an inflexion point in the shmoo.
Bingo!Quote:
Originally Posted by MR_SmartAss
AgreeQuote:
Originally Posted by MR_SmartAss
... But there is absolutelly nothing new: it is constant process, when next revision is faster then previous: 90nm F2 > F3, 65nm G1 > G2
I would say if you dont have years to make one final rev - it is the only way to tune it up eventially - from revision to revision.
Perhaps, but I said it before, I'll say it again, the B2 Stepping K10s will clock similarly to K8s :)Quote:
Originally Posted by MR_SmartAss
Perkam
65 or 90nm K8s? :ROTF:Quote:
Originally Posted by perkam
But I dont think so really.
All of this has(or at least should) happen during the design phase not after release. But i guess AMD would work on the design and process after release to improve clockspeed. If their 45nm is really as close as they state i doubt its worth putting any R&D into 65nm though. I'm also waiting to see how much they can gain from the use of SGOI if they get around to implementing it at 65nm after all. A 40% increase in electron mobility is quite a substantial improvement if it's true.Quote:
Originally Posted by MR_SmartAss
About time:p:Quote:
Originally Posted by Zytek_Fan
Still sure about that ?Quote:
Originally Posted by perkam
http://www.xtremesystems.org/forums/...d.php?t=163780
When you need >1.53V to get to 3GHz while a K8 on 65/90nm does it at under 1.4V , allow me to take your claim with a healthy dose of salt.
As I said in that thread, that Phenom looks very suspicious...so don't believe it until it can be confirmed from more than one site ;)Quote:
Originally Posted by savantu
Clock yes, Volt no. I have to go to 1.55v to get 3GHz on my X2 so it's not hugely dissimilar.Quote:
Originally Posted by savantu
OC doesnt count.Quote:
Originally Posted by DeathReborn
What's suspicious ?Quote:
Originally Posted by Zytek_Fan
When Anandtech reviewed the 2.5GHz B2 it ran at 1.52V too , that's stock.
Tell me that's "normal".
was it BA or B2?
What are we talking about, the results of one cpu. Why don't we just wait until we have a few more to look at.Quote:
Originally Posted by savantu
More from Xbit:
X-Bit labsQuote:
Chartered May Start Making AMD Processors Using 45nm Process Tech in 2009
Chartered Preps to Manufacture 45nm Microprocessors for AMD
As Advanced Micro Devices is getting ready to start pilot production ramp of its 45nm process technology, its “flexible” manufacturing partner Chartered Semiconductor claims that it would be ready with its 45nm process technology late this year. The contract maker claims that it expects to produce 45nm silicon-on-insulator (SOI) chips by mid-2009, just a little later compared to AMD itself.
“Our 45nm technology bring up is on track. I have also talked in the past that from the industry adoption and ramp standpoint, we should [hardly] see any meaningful volume until probably [the] early part of mid-2009, which roughly [is similar with the ramp of 65nm process technology],” Mr. Hwee said.
Despite of the fact that AMD uses SOI, it will be able to take advantage of Chartered production capacities in the first half of 2009, just like other customers of the Singapore-based contract chipmaker.
“Specifically on the SOI, we do not see any change in terms of the timing as well. It’s going to be around [for production] in that kind of timeframe in the late first half of 2009,” Mr. Hwee added.
Typically contract semiconductor manufactures, such as Chartered or TSMC, first develop their bulk process technologies and then supply their partners so-called libraries of elements and general design rules. Intellectual property owners have to develop their chipsets according to guidelines of the new process technologies; therefore, there is a timeframe between availability of fabrication technologies and volume manufacturing.
So, no metal gates in AMD's 45 nm?
Interesting.
Well they are not, at least initially. How did you reach that conclusion from this article though? Just to make it cler Chartered ispart of the AMD/IBM alliance.Quote:
Originally Posted by bedlamite
Well, Intel uses mysterious High-k Insulators to cooperate with their metal gates.
AMD still wants to use SOI, so i think they wont use metal gate.
Or im wrong and they have some way to make both.
Thats what they claim although initially they wont use either. Apparently its stilll under development to appear later on 45nm. I guess if they cant make it work they'll be forced to switch to bulk for 32nm.Quote:
Originally Posted by bedlamite
Low k is planned for AMD 45nm.
Any source of that?
And how they want to make high k + SOI ?
lol, All the sources are in threads here That I and other posted. Also low k is mentioned for 45nm in alot of amd news briefs. I hope youll excuse moi if I dont rush out and get those for you. When you find the news youll note that its Low k not air gap or ULK/Cu.
Also it could be on my news blog.
http://www.dewdnews.com/
Mysterious? What would hafnium be then? The only mystery is the alloys and process to make it cohesive and non destructive(so to speak)Quote:
Originally Posted by bedlamite
The mystery meat I am most interested in is the metal gate alloy. Hafnium aluminum insulation, woot yay , Are the gates platinum/Ra , Now there is a mystery. For some tidbits check out IEEE spectrum october issue.
:up:
Welcome to the XS forums :welcome:Quote:
Originally Posted by DAN16
Well, sorry, but i don't understand all of this technical english so i could miss that.
But thx for correction.
No problem. In the october issue of IEEE spectrum High K is mentioned. Now grose is in the news with talking about High K for AMD... link
http://www.semiconductor.net/?reques...l&referer_url=
I vote doug as the next AMD ceo. His credentials are Impressive.
No mysterious High-k this is hafnium which was already discuss in itrs 1999Quote:
Originally Posted by bedlamite
"Gate materials, high-k dielectrics, and capacitors
The challenges and options for high-k dielectrics and the related gate and capacitor processes are many, and there is still considerable debate about the various solutions. One point of agreement is the need for process integration and cooperation. One technical trend where there seems to be agreement is in the need to shift from silicon-insulator-silicon structures to metal-insulator-metal structures. Much of the current work is focused here.
IMEC's approach is an indication of the magnitude of the task of developing gate dielectrics. Marc Heyns, department director of IMEC's Advanced Surface Preparation, Thin Film, ES&H, and Gate Stack organization, reports, "Currently, there is no consensus on the material that can be used as alternative gate dielectric. Development in such a critical layer in an IC is only possible through large-scale international collaboration. That is why we have set up an Industrial Affiliation Program to develop gate dielectrics and gate electrodes (including metal gates) for sub-100nm devices. Within this program, IMEC wants to develop a manufacturable process for thin films (equivalent oxide thickness [EOT] <1.5nm) with low defect density and accurate thickness control. The gate stack must be integrated in the (n and p) MOS transistor, with the possibility to down-scale the stack to 0.5nm EOT." Their work points to ALCVD as the solution. Heyns adds, "ALCVD results in perfect thickness and uniformity, as well as composition control over large substrates. Therefore, we aim to use this technique to deposit very thin, high-k dielectric layers such as (but not limited to) Al2O3, ZrO2, HfO2, and their silicates for use as alternative gate dielectrics.""
Originally Posted by Donnie27
AMD is nowhere near 45nm=P
LOL!
Why is this even a sticky? We basically have zero information about how AMD's 45nm process development is going beyond the equivalent of the "Barcelona is on track" we heard for over a year and that meant absolutely nothing.
Just imagine for one minute if AMD didn't purchase ATI. They could've possibly used the money they had banked to fund R&D in 45nm and beyond. Just maybe, they would be able to put out 45nm chips in 2008.
Yes, in fact they are. GPUs are simply many many many watered down FPU units working in parallel, GPUs are highly specialized for one type of application. They are built for parallel number crunching with extra high throughput, but not necessarily clock speed. Thus, the max clocking capability of the GPU does not carry the same kind of emphasis as the general performance of the CPU.Quote:
Originally Posted by bedlamite
A transistor is a transistor, in the application of a binary on or off, this is where they are similar.... beyond that, they are constructed quite differently.
Jack
well it's not like that u can reverse the merge........
AMD will have to be bold this year and choose a path.
Well, you are a little confused on your process technology based on the context of this post.Quote:
Originally Posted by bedlamite
SOI is a substrate, which buries a layer of SiO2 beneath the transistor body. The purpose is to provide perfect electrical isolation from the transistor to the bulk of the rest of the substrate, and isolate each transistor from the other. In non-SOI constructed devices, also called bulk (i.e. no buried SiO2 layer), the electrical isolation is created by what is called a retrograde well implant. What this does is forms a PN junction diode that under normal operations will be reverse biased, as such current will not flow. Both the SOI isolation and the retrograde implant wells leak, but SOI leaks less than the the bulk. Unfortunately, as you scale smaller the SiO2 layer and the overlying Si layer must also shrink and this advantage over bulk gets smaller. I will not go into the disadvantages of SOI (which AMD and IBM will not publicize to the layman press), but they are numerous and are part of what is holding AMD back from ramping clock speeds no doubt.
The metal gate idea you have is indeed backwards... Intel did not put high-K in to play well with metal gate, rather they chose to use metal for the gate electrode because they want to relace SiO2 with a high-K dielectric. What Intel found, and what is published in the literature, is that gate electrodes that are made with metal do not suffer from Fermi Pinning as traditional poly-silicon gate electrodes do. As such, high-K is much more difficult to implement using traditional gate electrodes. The motivation for this technology is because the tried and true SiO2 isolation dielectric used to form the gate has been scaled to the limit. In fact, we hit that limit at 90 nm and it cannot go any thinner. You see this with both Intel's and AMD's 65 nm process, Intel could not clock their 65 nm Cedar mills any higher than their 90 nm prescotts, AMD can't even achieve equivalent clocks with thier 90 nm process.
Staying with SOI does not alleviate AMD's need to figure out how to get around this gate dielectric problem, without it they cannot scale the equivalent oxide thickness of the gate, without it they cannot move away from the gate leakage cliff, and without it they will most likely not exceed even 65 nm clock speeds when moving to 45 nm (this last part is my opinion, I have not seen any data one way or the other).
You may want to take a little time studying the device physics, and purpose for these new technologies before you post... or, if it is of no interest to you, then I suggest you refrain from posting at all :) ... you are bound to get flack :)
Jack
I'll believe it when I see it. Phenom was super late out the door and is by all indication a bust. I don't believe AMD anymore after all the hype that was put into their 65nm chips. The way things are going AMD won't have 45nm out the door until 2009 and by then Intel could have even denser chips.