Just wondering, has anyone compared nehalem to q6600? A lot of people still have them and if the QX9770 is that much better in these tests, I'll stick with cheap stuff for a while.
Printable View
Just wondering, has anyone compared nehalem to q6600? A lot of people still have them and if the QX9770 is that much better in these tests, I'll stick with cheap stuff for a while.
I think you are misreading the data, in all but the COH a 2.93 GHz Nehalem is faster than a QX9770 ... a 2.66 Nehalem will be roughly the same as a QX9770 or better... with the exception of what is shown in some games (COH, WOC, COD4) ... but even these will be significantly faster than a Q6600.Quote:
Originally Posted by [XC] Synthetickiller
The Crysis benchmark is on load times, the rest are synthetics, rendering, and file compression software.
Now, the question is really is the application you are looking for worth the money in the upgrade ... if your idea of a computer is simply gaming, regardless of Q6600, Core i7, Phenom what ever... the answer to the question is actaully no ... that is because how you play the game is GPU determined, not CPU determined.
Jack
Just look to my thread: http://www.xtremesystems.org/forums/...d.php?t=202139
And you will see that the Nehalem will be much faster..ofcourse you have to compare them at the same speed!
JP.
Thinking about the same thing I'm thinking ?Quote:
Originally Posted by [XC] Synthetickiller
Nehalem EX Skullthrail and 4 GTX350 ? :hehe:
Folding Monopole Farm ?
I am thinking the same, 256kb seems too small, but dont forget the L3 cache is inclusive, so all data from L2 and L1 is stored into the L3 cache. Thats 4*(256+64) = 1280KB it takes awa from the L3 cache. With bigger L2 caches you would start canabalizing the L3 cache. The inclusive architecture also has the advantage that a core doesnt have to "search" into the other cores L2 cache. This means less traffic to the L2 cache. Another advantage is that the L2 cache isnt occupied with inter core traffic.Quote:
Originally Posted by JumpingJack
Judging these advantages maybe a 256KB L2 cache is justified?
I still have my doubts, but we will see in a month :)
I kind of disagree with you here, at least from the perspective of a Home User.Quote:
Originally Posted by informal
I am looking to get a new system sometime in the first QTR of 2009 and I was considering Nehalem, but if it can't beat a Dual Core Penryn in gaming, then with the price premium it will carry, it would be of no value to me, as a Dual Core Penryn is plenty fast enough for all my non-gaming needs.
Hell, Deneb could even come into consideration for me if their IPC & Clock rate improvements prove not to be illusory.
The effect of memory speed/bandwidth on application performance has tended to be much over played for a long time now.
JJ, is the low hanging fruit all gone?Quote:
Originally Posted by JumpingJack
Or they just figured out that this would be the easiest way of increasing share and profit without risk... I mean, we all know what they're trying to dethrone here. :p:
For simple home users a E6600 is already to fast, but agree with youQuote:
Originally Posted by JumpingJack
This is a very hard question to answer .... the short answer is yes and no.Quote:
Originally Posted by Macadamia
It depends on what you mean by low-hanging fruit. For example, the most common low hanging fruit is cache size ... up the cache is almost a guaranteed increase in IPC efficiency, the problem is that the % improvement decreases geometrically with size ... for example, the improvement going from 256 K to 512 K is larger than going from 2 Meg to 4 Meg cache ... in most applications (it is app dependent). However, designers often spend some of the transistor budget increasing cache one generation over the other (Intel most commonly and now AMD will start doing it more often I suspect -- shanghai is a good example).
However, there is still plenty of room to improve IPC. A microprocessor today be it Core based or A64 based, actually spends more time dormant (waiting on instruction/data) than it spends in actual execution. The actual IPC of, for example, a C2D core varies between 1 to 2 on average ... this is because there are several lost cycles when the CPU stalls ... to improve, designers need to find and design clever ways of avoiding these stalls and keep the processor more occupied over time.
So many tricks have been implemented a long time ago (OoOe, wider cores, larger cache, TLBs, wider instruction windows, BTBs etc.) ... some improvements can come (low hanging fruit) by simply making some of these tricks bigger --- both Barcelona (and now Nehalem) for example have worked to increase the instruction window and that buys another 10-15% over prior generations (in the Barcelona case at least).....
Revolutionary designs though will be needed to make major leaps I suspect (my opinion)... something new that has never been done before.