More P5B secrets uncovered

...I tried to find interestings registers in differents dumps
between fsb:398<->fsb:402,but a lot of registers change when
you apply this fsb values.So difficult to know what is good or no.
However,there are some common registers that change in this dumps
made by bachus_anonym and kunaak (965 chipset):

http://img239.imageshack.us/my.php?i...pbachusux2.jpg

http://img239.imageshack.us/my.php?i...pkunaakja9.jpg

For example register at offset 144 and 1F1...
but this register are "intel reserved" in datasheets,
and I don't know what they are.
I made a little soft that allow to edit the mchbar,
it's work on chipsets 865/875 and 9xx.

MemTweak.zip

It's run only in 32bits.
You can try to change these registers and other with this soft,
but warning,don't change anything,else it's possible crash...
Your first address must be (in left column) FED14000 for 9xx chipsets,and FECF0000 for 8xx.

...for info-timings on 865/875 chipset is at address FECF0060,
-timings on 915<->975 chipsets are at address FED14110 to 120 for channelA 190 to 1A0 for channelB
-timings on 965 chipsets are at address FED14250 to 290 for channelA
650 to 690 for channelB

...also you can change your values with pmem ,it's a little good soft
made by Franck (cpu-z author),it's run in 8,16 and 32 bits.

btw, i made some screens with p5w, bootup at 200 and 437, also equalized timings in memset to minimize different registers.. note that values marked in red are ones that change even when just refreshing.. so you can easily discard them. grab the screens here
by the way, what datasheets do you use? 975x datasheet don't even say where "intel reserved" bits are..
i hope i could be of help.
i'll also try to boot at 266 with hp3 on and will write down all registers that change.. and, of course, will try to modify them :)
though it could be that 975 and 965 are a bit different.. if timings are at diff adresses already :s

edit: nm, noticed in datasheet, that every memory range not mentioned is "intel reserved" :)

edit2: btw, FELIX, could You make a little adjustment to Your program?
Please expand the range to FED14FFF and make the data window also sizable so one could
take a screenshot of whole data.. would be very helpful if asking additional info from others.
thanks :)

...thank you for the screen :)

for edit2,I not the time to do that actually,and I'm not at home for 10 days,
but I'll probably integrate memtweak in memset in a next version,
and correct that in same time.

So I guess this is the reason why i can POST 385 fsb but not 390 fsb on p5wdh , although the last one is completely stable in windows via clockgen...

Very interesting thread :)

ok.. here are the results with various settings, p5wdh.
hope you can understand it :)
though i think i'm back at the beginning
only bits that indicated most likely strap, were uneditable.
if they aren't status bits there's big chance they are write once bits..

may I through in my 2 cents:
It is clear from your results so far that when booting at the default multi, the strap changes at 400 FSB (NBCC=400 also). When booting at 400 then ramping up using clockgen, things go bad at 420 say becuase of the tight timing even though the starp is 1333. We all agree on that AFAIK.

The confusion occured when Bacus_anonymous (sp) did his test with the E6600 booted at 350*8 (NBCC=394) and then clockgen up, he was able to do it without it locking up at ~360 fsb as would be expected.

We assumed that when he booted at 350*8 that Asus bois still applied the 1066 strap since NBCC is under 400. However note that, if this is the case he has actually booted in the very unstable zone (370-399). Which he did not report. And the fact that he kept ramping up using clockgen without a lockup at ~360 tells me this:

What if Asus originally designed the whole thing to change the strap at fsb 333 MHz irrespective of multiplier ratio, then they made the special case change of the 400 MHz limit only when runnig default multi. We assume that the BOIS actually calculates the equivalent FSB number (356) when booting to *8 vs *9, but maybe Asus just applies the standard intel 333 Frequency and changes the starp.

So when bacus_anonymous booted at 350 *8, he actually booted into the 1333 MHz strap and thus sailed with clockgen because the timing is relaxed to begin with? Does this make any sense?

Note: I do not own an Intel. I am a nooob, and hardly understand this stuff anyway. Just a thought I thought maybe I should share. Thanks.

That was an interesting read.
That might explain why some 965 3D benches were on par with 975 benches and some were not.
I can try to see if there is a difference in bw when going from 300Mhz FSB to approx 450 in case memtest works with my P5W.

Bacus if you dont mind, could you do a 01 run at both 410Mhz set in bios and 410 using clockgen?
Would be interesting to see if it makes any change.

I understand about 10% of this thread. Someone needs to dumb it down and just tell me what FSB to run. Currently im running an E6600 at 8x405.

FELIX, great work my friend, i dont have intel right now so i cant test for you, someone try it though!!!

Quote:

---

Originally Posted by bw31

I understand about 10% of this thread. Someone needs to dumb it down and just tell me what FSB to run. Currently im running an E6600 at 8x405.

---

If you are using a P5B\Deluxe, you will probably get better memory performance at 400mhz FSB instead of 405.

Tried 399 and 401 set from bios. All ran after reboot on same timings. E6600 on asus P5B 0614. Times are almost same while using 7 or 8 multi but sandra stil reports less bandwidth on the 401 FSB tests.

9x399
http://img.photobucket.com/albums/v636/loc_oc/9x399.jpg

9x401
http://img.photobucket.com/albums/v636/loc_oc/9x401.jpg

8x399
http://img.photobucket.com/albums/v636/loc_oc/8x399.jpg

8x401
http://img.photobucket.com/albums/v636/loc_oc/8x401.jpg

7x399
http://img.photobucket.com/albums/v636/loc_oc/7x399.jpg

7x401
http://img.photobucket.com/albums/v636/loc_oc/7x401.jpg

Quote:

---

Originally Posted by wittekakker

Standard:
Strap=1066
CPU=2660MHz
FSB=266MHz
Multi=10
NBCC=266MHz

On P5B FSB=333:
Strap=1066
CPU=3330MHz
FSB=333MHz
Multi=10
NBCC=333MHz

On P5B FSB=401:
Strap=1333
CPU=4010MHz
FSB=401MHz
Multi=10
NBCC=334MHz

Right?

And...
The CPU speed is dependant on FSB*Multi.
The NBCC is believed to be dependant on FSB speed and the relation of default and set multiplier.

But...
On the P5B: the NBCC changes when u hit 401MHz FSB. U fall back from 1066 strap to 1333 strap.

Would the attached formula be more complete or did I hit it totally wrong?

---

It seems I got it wrong. Now that I have my Conroe setup I see that it's not the NBCC that is changing, it's only the internal latency when u hit a higher strap.

Quote:

---

Originally Posted by wittekakker

It seems I got it wrong. Now that I have my Conroe setup I see that it's not the NBCC that is changing, it's only the internal latency when u hit a higher strap.

---

nbcc is dependant on fsb and strap. most likely a strap change will force different internal timings on nb, but also its very likely that strap change forces new multiplier to nb, thus changing nbcc.
just like cpu speed is multi x fsb :)
but without those intel nonpublic documents it's hard to make a conclusion..
though one could use a frequency scanner to get real nb core clock :)

Quote:

---

Originally Posted by caater

ok.. here are the results with various settings, p5wdh.
hope you can understand it :)
though i think i'm back at the beginning
only bits that indicated most likely strap, were uneditable.
if they aren't status bits there's big chance they are write once bits..

---

If we compute the Ram Frequency as:
Ram_freq=2*FSB_freq*north_multi/mem_div
i think that north_multi and mem_div are coded at the offset C00h in this way:
the first 4 bits give mem_div:
1 (0001) -> mem_div=2
2 (0010) -> mem_div=3/2
3 (0011) -> mem_div=6/5
0 (0000) -> mem_div=1 *(not tested)
the other 4 bits give north_multi:
1 (0001) -> north_multi=3 (533 strap)
2 (0010) -> north_multi=2 (800 strap)
0 (0000) -> north_multi=3/2 (1066 strap)
3 (0011) -> north_multi=6/5?(if 1333 chipset strap can be applied)
Moreover, as you caater already concluded, the north_multi seems to be present at E08h offset also.
Note that i computed the northbridge freq through the relation:
FSB_freq*north_multi

unfortunately c00h seems to be only indicator and it doesn't change anything.
well, what it does, it fools cpu-z and other programs though..
try to modify its value.. 10-4:3 20-1:1 30-4:5 40-2:3
so validated cpu-z mem screens do not mean a thing without bandwidth test :rolleyes:
also can't modify last 4 bits..

ok ive got a p5b on the way lets see how it works out.

Quote:

---

Originally Posted by caater

unfortunately c00h seems to be only indicator and it doesn't change anything.
well, what it does, it fools cpu-z and other programs though..
try to modify its value.. 10-4:3 20-1:1 30-4:5 40-2:3
so validated cpu-z mem screens do not mean a thing without bandwidth test :rolleyes:
also can't modify last 4 bits..

---

You are right, so maybe it's an indicator of north multi also, that is set up at E08h offset. The problem i don't see another register cell that is constant with mem_div.

Quote:

---

Originally Posted by astaris

You are right, so maybe it's an indicator of north multi also, that is set up at E08h offset. The problem i don't see another register cell that is constant with mem_div.

---

oh there are lots of them.
138h, 1B8h (both dword), indicates that there's something changed per channel.
208h (dword), also changes with mem ratio.
C18h changes with ratio and C1Ch too. dword.
and those registers - also intel reserved..
tbh, there was more changes, even major ones, but once i wrote down common registers, i discarded all others.

Quote:

---

Originally Posted by caater

oh there are lots of them.
138h, 1B8h (both dword), indicates that there's something changed per channel.
208h (dword), also changes with mem ratio.
C18h changes with ratio and C1Ch too. dword.
and those registers - also intel reserved..
tbh, there was more changes, even major ones, but once i wrote down common registers, i discarded all others.

---

Uhm, these locations are not costant with mem_div, but with mem_ratio, where
mem_ratio=mem_div/north_multi
I'm pretty sure that mem_div set upmem_ratio, because with a given strap, i.e. north_multi, you can have only 4 mem_ratio, so it's logical to set mem_ratio with the two variable you are free to set, i.e. north_multi and mem_div, but the only cell i can see is constant with mem_div is C00h (the higher bits).

according to The Stilt he is running at 1066 strap in this screenshot.......511MHz FSB

Quote:

---

Originally Posted by The Stilt

I have a L629A528 chip too.
Version: D63625-002
Pack Date: 09/06/2006
PCB: 35628657

There is only 425 die difference between my and kyosen´s processors.
His code is A2313, while mine is A1888 ;)

With Tuniq Tower and 1.38V the chip ran Orthos for 7 hours at 3.6GHz (until I closed it).

With semi broken VapoLS it can do 4.5GHz dual SuperPI 1M stable with 1.6V (evaporator at -36c)

With dry ice it seem to be pretty stable at 4.8G with 1.625V, but since the board must be booted with slower strap for those frequencies, it is faster to run it at 4.6GHz with 1.575V ;)

http://www.armada.fi/E6600_L629A528/...exusPifast.gif

http://www.armada.fi/E6600_L629A528/..._SuperPI1M.gif

http://www.armada.fi/E6600_L629A528/..._SuperPI8M.gif


It took four hours to make the board run at 511FSB with 1066FSB strap.
When I took the board out from the box, it did 450FSB - 470FSB with those setting when it was booted with 400FSB.

---

Quote:

---

Originally Posted by dinos22

yo stilt HOW DID YOU get the board to run at 511MHz 1066FSB strap.................is there a trick to force the strap:confused: :confused: :confused: :toast:

---

HIS ANSWER

Quote:

---

Originally Posted by The Stilt

High VMCH + Cooling.

---

anyone else able to replicate this?

Yep, this is correct :)

I tried it after I did vdimm & vmch mods. With up to 1.67vmch I managed to "clockgen" from 400x9 to 468x9 and run pifast as well. Result? Full 0.50s difference, compared to straight boot @ 468x9 :fact: After that, I kind of stopped investigating it further, but I might try again, with more vmch. But yes, it is confirmed, just a matter of how high you manage to go. Just a note, this is no-go at any other ratio than 1:1 :(

Does the 1333 strap kick in at 400 or 401mhz? Im planning to try and hit 400x9 (3.6ghz).

I would do the tests myself but im too lazy atm :p

I wanted to share my results which confirm what others are seeing.

Screen #1 - booted into Windows at 400FSB, then used SetFSB to move a little higher

Screen #2 - booted in Windows at 503FSB

http://img137.imageshack.us/img137/5303/32m4026uw3.jpg

http://img80.imageshack.us/img80/6541/32m503x8zw0.jpg

More than 30 seconds difference. 503X8 may look more impressive. But looks can be deceiving. This is one reason why I prefer to run with lower FSB and a tighter strap. By using 4:5 ratio, I get a boost from higher memory speed.

When I stay on the tighter strap, the P5B Dlx is just as fast as any 975X board, IMO.

Now of course, higher CPU speed will eventually compensate for higher latencies. But once you move to a looser strap, you are fighting an uphill battle.

Can you please compare this for me?:

7 x 400 1:1 4-4-4-12
7 x 500 1:1 4-4-4-12

I was just curious as to how my e6300es would improve with new mem.