K10 Scores starting to surface

Printable View

Show 100 post(s) from this thread on one page

09-12-2007, 09:16 AM
Movieman

Quote:

Originally Posted by [XC] Kayin

True, but still, I see no 1000 dollar CPUs in my build, and I still see more than enough power to do all I want to do and crunch WCG MUCH better thanI was before.

Hell, a regular pair of opties (at 170 each) might do me for a while, up my output, and still handle what I wanna do. Then it's just down to board choice...

Understood, the key for me was the deal that I got on them and the timing.
This was last December..Clovers didn't get released to retail till the end of January. I did the whole system,everything, for less than the cost of 2 cpu's retail and the chips I have are better than the best retail chips available even now 9 months later..X5350's..6-10 multi..Run at 100% load 24/7 at 3157 since last december..
Just the one air cooled machine will do 10 million points this year in WCG..:D
09-12-2007, 04:54 PM
JohannesRS

Unbelievable... You mentioned Asus and MSI at least three times as MBs for Dave, and he haven't said anything? :D

Just kidding, could not help on it. Dave, one thing: tere are rumors that the Barcellona Core should already be ready for DDR3. Can you give us any info in this point?
09-12-2007, 05:57 PM
dave_graham

Quote:

Originally Posted by JohannesRS

Unbelievable... You mentioned Asus and MSI at least three times as MBs for Dave, and he haven't said anything? :D

Just kidding, could not help on it. Dave, one thing: tere are rumors that the Barcellona Core should already be ready for DDR3. Can you give us any info in this point?

i strongly dislike MSI and Asus....well, not a big fan either.

cheers,

dave
09-12-2007, 06:07 PM
akaBruno

Well Dave... now you have to tell us who you do like... in mobo's.
09-12-2007, 06:22 PM
PhilDoc

Quote:

Originally Posted by akaBruno

Well Dave... now you have to tell us who you do like... in mobo's.

I'm sure Dave will answer for himself, but I'm going to say #1 Supermicro, #2 Tyan. Those are the best server boards I can think of.
09-12-2007, 06:41 PM
KTE

I'm not fond of MSI - especially customer support. I have a board with a beta BIOS they sent out to me after 15 months of crying at them, which eliminated ALL my problems.. yes you read correctly. But hold on... it also left zero options in the BIOS itself. :(
09-12-2007, 06:54 PM
PhilDoc

Quote:

Originally Posted by KTE

I'm not fond of MSI - especially customer support. I have a board with a beta BIOS they sent out to me after 15 months of crying at them, which eliminated ALL my problems.. yes you read correctly. But hold on... it also left zero options in the BIOS itself. :(

I have no fondness for MSI boards either. Never had one that I liked or one that worked all that well. I'm not supprised at all about the trouble you had.
09-12-2007, 06:54 PM
dave_graham

Quote:

Originally Posted by PhilDoc

I'm sure Dave will answer for himself, but I'm going to say #1 Supermicro, #2 Tyan. Those are the best server boards I can think of.

reverse that. tyan has helped me out from a pre-sales, post-sales and support standpoint immeasurably more than SM. :)

however, i've got one customer who only buys SM so... :)

dave
09-12-2007, 07:03 PM
kyosen

It seems that DDR3 related things are already described on the BIOS and Kernel Developer’s Guide...
http://www.amd.com/us-en/assets/cont...docs/31116.pdf
09-12-2007, 07:11 PM
PhilDoc

Interesting, I thought I read somewhere that they were not going to support DDR3 due to power consumption issues. I guess whoever wrote that is wrong.
09-12-2007, 07:57 PM
JohannesRS

And that's the most interesting question now: Is Barcellona DDR3 ready or not?
09-12-2007, 08:16 PM
KTE

Interesting... VERY. Although it'll take me a year more to read. :D

http://img503.imageshack.us/img503/7466/ddr2ddr3qa3.png

http://img205.imageshack.us/img205/9563/ddr2ddr3fn6.png

http://img240.imageshack.us/img240/2276/ddrhi9.png

http://img174.imageshack.us/img174/1395/dimmga3.png

http://img210.imageshack.us/img210/3456/tctllh5.png

4 HT links too. Hmm....
09-13-2007, 11:09 AM
Lightman

This is very interesting! Looks like Socket G(1207) is one with support for 4HT links and RDDR3 :) .

The only wired thing is limitation to 1 DIMM per channel for DDR2-1066, but I think I can live with that :D .
09-13-2007, 11:25 AM
KTE

I'm not sure if that'll be updated at all for the Budapest or Shanghai. It might well contain information referring to them. I know back in 2006 Barcelona was supposed to have a dual DDR2 and DDR3 controller, but that only one could work on the board. However, AMD said that the latest K10 doesn't support DDR3, while the guides are revealing DDR3 plans alongside DDR2. :confused:
09-13-2007, 11:29 AM
PhilDoc

I share your confusion, perhaps Dave or someone can clarify things for us.
09-13-2007, 10:37 PM
Dresdenboy

Quote:

Originally Posted by KTE

I'm not sure if that'll be updated at all for the Budapest or Shanghai. It might well contain information referring to them. I know back in 2006 Barcelona was supposed to have a dual DDR2 and DDR3 controller, but that only one could work on the board. However, AMD said that the latest K10 doesn't support DDR3, while the guides are revealing DDR3 plans alongside DDR2. :confused:

It's probably similar to dual core support in the first K8s. The SRQ had the support in it and the docs documented that. But it took 2 years until dual cores, which finally were making use of this, appeared.

So the DDR3 support seems to be there, but either the package or the programmed fuses don't allow it to work. The S940 opteron dies also supported unbuffered DIMMs, but it wasn't programmed to be enabled and the package likely used some different routing.

Maybe even the FB-DIMM support is already there (at least somewhere in the NB), because adding something rather complex later would require a redesign, while having it at least in some alpha state even makes it possible to debug it already.

Remember Hyperthreading, 64 bit support in Prescott etc... (see http://www.chip-architect.com/). All these things appear to have existed in silicon available on the market, while nobody could use them.

And the 4 HT links in Barcelona were present on die plots and die photos from day one. Unfortunately they don't make use of the 4th one yet..
09-13-2007, 11:37 PM
KTE

Barcelona on sale: http://www.staticice.com.au/cgi-bin/...q=Opteron+2350 :)

You're probably right Desdenboy. Hardware can have many capabilities disabled although etched out perfectly to implement down the line. I'm pretty sure TDP is the current problem with various hardware speeds on K10.

BTW, I noticed how Anantech and TechReport never posted CPU-Z screenies, whereas its very rare for reviewers to not do that generally.

F21 is DR-B1 : B1 step
F2A is DR-BA : BA step
F22 is DR-B2 : B2 step

I expect the B3 step will follow similar schemes.

TechwareLabs review was a B1 step core, as Dave has being saying all along: http://img206.imageshack.us/img206/4645/cpuidhn8.jpg

I suppose that'll be true for AT and TR reviews too, apart from the 2360 SE 2.5GHz part which'll most likely be a B2 step.
09-13-2007, 11:49 PM
metro.cl

Quote:

Originally Posted by KTE

I'm not sure if that'll be updated at all for the Budapest or Shanghai. It might well contain information referring to them. I know back in 2006 Barcelona was supposed to have a dual DDR2 and DDR3 controller, but that only one could work on the board. However, AMD said that the latest K10 doesn't support DDR3, while the guides are revealing DDR3 plans alongside DDR2. :confused:

Shangai and Budapest will use DDR2 only.

First one with DDR3 will be Montreal and Suzuka
09-14-2007, 12:08 AM
Motiv

Quote:

Originally Posted by KTE

I suppose that'll be true for AT and TR reviews too

Anand has said he used a B1 just for clarification
09-14-2007, 05:20 AM
dave_graham

Quote:

Originally Posted by KTE

Interesting... VERY. Although it'll take me a year more to read. :D

4 HT links too. Hmm....

there are 4 HT links in each core.

23xx series have 1 fused out.
83xx series have all enabled.

cheers,

dave
09-14-2007, 05:45 AM
Lightman

Quote:

Originally Posted by dave_graham

there are 4 HT links in each core.

23xx series have 1 fused out.
83xx series have all enabled.

cheers,

dave

That then means it is possible to build 8S system with only 1 hop to every socket.... Something I haven't been expecting before SocketF+ (G).
09-14-2007, 06:19 AM
dave_graham

Quote:

Originally Posted by Lightman

That then means it is possible to build 8S system with only 1 hop to every socket.... Something I haven't been expecting before SocketF+ (G).

some clarification.

for reference, AMD doesn't call anything F+. It's simply Socket L1 (Socket F) and Socket L1-SP (split-plane; what people are calling F+).

back to the HT links for a second.

there's still a 2 hop penalty since only 1 of the 2 intra-CPU links are coherent. the secondary link is simply used to pass traffic. As there has been no realistic testing on even the 23xx series to determine utilization of that second link (and even it's performance) it's still safe to assume that n-way configurations will need to be passed over the coherent links only and, as such, will still require two hops. I'll get confirmation of this when I can. :)

here's a quick and dirty illustration.

Quote:

mem <-> CPU0 = CPU 1 <-> mem
|| ||
mem <-> CPU2 = CPU 3 <-> mem

does that make sense? one lane of each HT pair is coherent.

cheers,

dave

EDIT: F'ing software isn't lining my pipes up correctly....
09-14-2007, 06:34 AM
JumpingJack

Quote:

Originally Posted by KTE

Barcelona on sale: http://www.staticice.com.au/cgi-bin/...q=Opteron+2350 :)

You're probably right Desdenboy. Hardware can have many capabilities disabled although etched out perfectly to implement down the line. I'm pretty sure TDP is the current problem with various hardware speeds on K10.

BTW, I noticed how Anantech and TechReport never posted CPU-Z screenies, whereas its very rare for reviewers to not do that generally.

I suppose that'll be true for AT and TR reviews too, apart from the 2360 SE 2.5GHz part which'll most likely be a B2 step.

Anand posted a CPUID of the 2.5 GHz chip:
http://www.anandtech.com/cpuchipsets...spx?i=3092&p=2
09-14-2007, 06:39 AM
Donnie27

Quote:

Originally Posted by dave_graham

HW prefetching was disabled because it can significantly impact the performance of those Intel processors on specjjbb.

dave

Sorry I missed this one, but was it turned back on for other tests?
09-14-2007, 07:41 AM
bingo13

Quote:

Originally Posted by Kjaks

The big question is; how well will it overclock on air?

Any K10 overclocking results out there?

The B2s clock nicely on air, just cannot show results yet as the L1N64 replacement is still under NDA. As for the Phenoms, it is too early to tell based on the current core release, but the RD790 does a very nice job of overclocking a 6400+. ;)
09-14-2007, 08:26 AM
dave_graham

Quote:

Originally Posted by Donnie27

Sorry I missed this one, but was it turned back on for other tests?

unknown.

dave
09-14-2007, 08:30 AM
akaBruno

Quote:

Originally Posted by bingo13

The B2s clock nicely on air, just cannot show results yet as the L1N64 replacement is still under NDA. As for the Phenoms, it is too early to tell based on the current core release, but the RD790 does a very nice job of overclocking a 6400+. ;)

Can't wait to see that. :cool:
09-14-2007, 02:03 PM
KTE

Quote:

Originally Posted by JumpingJack

Anand posted a CPUID of the 2.5 GHz chip:
http://www.anandtech.com/cpuchipsets...spx?i=3092&p=2

Thanks, forgot about that. Thats the B2 core, the code says it v.clearly. Should've been more clear - I'm wanting to see the CPUZ for the launch processors they all reviewed, which were B1s; like Coolaler forum, Daves, TechwareLabs, TechReports and Stephens.

This is the CPUZ string a B1 gives (missing the DR-B1 in the revision field, even though its Agena)

http://img256.imageshack.us/img256/5...rimeko3.th.jpg
09-14-2007, 02:46 PM
JumpingJack

Quote:

Originally Posted by KTE

Thanks, forgot about that. Thats the B2 core, the code says it v.clearly. Should've been more clear - I'm wanting to see the CPUZ for the launch processors they all reviewed, which were B1s; like Coolaler forum, Daves, TechwareLabs, TechReports and Stephens.

This is the CPUZ string a B1 gives (missing the DR-B1 in the revision field, even though its Agena)

http://img256.imageshack.us/img256/5...rimeko3.th.jpg

Yeah ... CPUID still needs a little more work to get all the info correct, but F22 is B2 I do believe.

Jack
09-14-2007, 03:43 PM
Lightman

Quote:

Originally Posted by dave_graham

some clarification.

for reference, AMD doesn't call anything F+. It's simply Socket L1 (Socket F) and Socket L1-SP (split-plane; what people are calling F+).

back to the HT links for a second.

there's still a 2 hop penalty since only 1 of the 2 intra-CPU links are coherent. the secondary link is simply used to pass traffic. As there has been no realistic testing on even the 23xx series to determine utilization of that second link (and even it's performance) it's still safe to assume that n-way configurations will need to be passed over the coherent links only and, as such, will still require two hops. I'll get confirmation of this when I can. :)

here's a quick and dirty illustration.

does that make sense? one lane of each HT pair is coherent.

cheers,

dave

EDIT: F'ing software isn't lining my pipes up correctly....

I made a mistake because 8S topology has 3 hops and 4S 2 hops :)

I through that Opties 22xx had 3 HT links with only 1 ccHT but Opties 82xx had 3 HT links with all 3 ccHT enabled.

4S fully connected with plenty of I/O using Opteron 82xx - 2 HOP

................I/O
.................|
...CPU1.--.CPU2
.....|..\........|
.....|.....\.....|
...CPU3.--.CPU4
.....|
....I/O

8S using Opteron 82xx as an example CPU8 needs 3 hops to get data from CPU7

................CPU1.--.CPU2.--.CPU3
................/.....\......|..../..........\
............../.........\....|./...............\
I/O.-.CPU7.............\/|................CPU8 - I/O
..............\....... ../...|.\............../
................\....../.....|.....\......../
...............CPU4.--.CPU5.--.CPU6

If Barcelona can use 4 ccHT links now then it's great for scaling 4S/8S systems, but I remember that this feature was on roadmaps only for 45nm HT3 enabled successor of Barcelona. Can you clarify that for me Dave?? :help:

Show 100 post(s) from this thread on one page