AMD cuts to the core with 'Bulldozer' Opterons

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Originally Posted by ajaidev

Amm Intel did delay Sandy bridge and they did it to try and implement something which SB does not have and BD does. Tough the implementation is very hard to accomplish i have been told 3-4 teams are working on it right now, one may call it the v1.1 the v1.0 of SB is all ready for the fight....

If the v1.1 works out it will get relesed in stead of the v1.0 otherwise v1.0 will be used, in tis case IB will come sooner than later.

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? which feature are they trying? ....idk, i feel as if maybe intel will be able to cripple amd again like they did before?

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Originally Posted by god_43

? which feature are they trying? ....idk, i feel as if maybe intel will be able to cripple amd again like they did before?

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If the thing they are tying does not get ready, they will use the original version of SB and in that case they will use more cores to fight BD similar to what things are with AMD and Intel right now.

AMD is using more silicon to fight Intel per cpu...

http://images.anandtech.com/reviews/.../bulldozer.jpg

Since there is only one fetch and decode units per module, are there any chance it could use all ALUs for a Single Thread ?

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Originally Posted by doompc

http://images.anandtech.com/reviews/.../bulldozer.jpg

Since there is only one fetch and decode units per module, are there any chance it could use all ALUs for a Single Thread ?

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Let's hope so...

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Originally Posted by ajaidev

If the thing they are tying does not get ready, they will use the original version of SB and in that case they will use more cores to fight BD similar to what things are with AMD and Intel right now.

AMD is using more silicon to fight Intel per cpu...

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I've no idea what you're talking about with your 'different versions of SB'. Where did you get that information from?

AMD using more silicon to fight Intel? I'm not so sure about that, I wouldn't be surprised if a BD module was smaller than a SB core.

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Originally Posted by doompc

http://images.anandtech.com/reviews/cpu/amd/FAD2009/2/bulldozer.jpg

Since there is only one fetch and decode units per module, are there any chance it could use all ALUs for a Single Thread ?

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They could theoretically do that, but I don't think they will as it is very very hard to get more instruction parallelism out of a single thread and you would hardly gain any performance (for single threaded loads) by using all 8 INT execution units for a single thread.

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Originally Posted by Helmore

I've no idea what you're talking about with your 'different versions of SB'. Where did you get that information from?

AMD using more silicon to fight Intel? I'm not so sure about that, I wouldn't be surprised if a BD module was smaller than a SB core.



They could theoretically do that, but I don't think they will as it is very very hard to get more instruction parallelism out of a single thread and you would hardly gain any performance (for single threaded loads) by using all 8 INT execution units for a single thread.

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i belive he is talking aboot the current amd cpus, and not BD. i hope that amd is releasing some info that will not help intel counter it, cause i want a strong amd... they need to have a win, otherwise intels campaign against them and everyone elsew has won.

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Originally Posted by Helmore

I've no idea what you're talking about with your 'different versions of SB'. Where did you get that information from?

AMD using more silicon to fight Intel? I'm not so sure about that, I wouldn't be surprised if a BD module was smaller than a SB core.

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From the same place i get the i7 980X...

I was talking about Intel using more silicon/cores against BD not the other way around reverse of what is happening now a days..

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Originally Posted by god_43

? which feature are they trying? ....idk, i feel as if maybe intel will be able to cripple amd again like they did before?

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The original Sandy bridge was canceled and a new project was started.

Core was designed by Intel Israel. By 2005 Core was nearing completion and the uarch guys moved on to the next big thing : Gesher, later called Sandy Bridge.
Usually a CPU design takes 4 years at Intel : 1 is uarch, 2 is implementation , 1 is validation.While Intel Israel was thinking how Gesher will look like, Intel Oregon was busy implementing Nehalem.

But something happened : Gesher is cancelled 1 year after it started and work start all over again. Same team, same project , different name : Sandy Bridge.
Why did they give up the original ? Aimed too low, too complex, wrong path, too small of an improvement over Nehalem ? Who knows. AMD was busy defining K10 at the time, I don't remember hearing of Bulldozer in 2006.

Either way, Sandy Bridge and more likely Ivy Bridge should be just as revolutionary as Core, if Intel Israel wants to live up to the reputation they've earned.

SB is beefed up Nehalem,you can clearly see this from intel's disclosed info from past IDF's.The "big" change is AVX,but unfortunately no FMA support in SB. Other poster is implying that intel is reworking current SB core to make it better for BD time...

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Originally Posted by savantu

Either way, Sandy Bridge and more likely Ivy Bridge should be just as revolutionary as Core, if Intel Israel wants to live up to the reputation they've earned.

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SB is a confirmed Intel Israel design?

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Originally Posted by informal

SB is beefed up Nehalem,you can clearly see this from intel's disclosed info from past IDF's.

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I can't see anything in IDF's disclosed info about that, so unless you know something the rest of the world except Intel doesn't that's pure speculation and probably BS.

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Originally Posted by 003

You have misunderstood what I said. Core for core, obviously you can't expect double IPC with a new microarchitecture.

The article said that two Bulldozer cores have a 1.8x increase in parallel performance over a single current generation core.

That is where I got the number of 2.0x, comparing two cores to one core.

Now if we divide that 180% boost by two, we can roughly determine the performance of a single Bulldozer core vs a current generation core. It works out to only 90% of the performance of a current generation core, or 10% slower, which happens to be exactly what the article said.

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this is what i pulled from the article as well... either they simply misunderstood everything that was told to them, or intel has the potential to smash with sandy bridge. and i was hoping for a price war....

no, intel has a prety big slide show on avx. i have it downloaded but i cant refind that link but its somewhere on idf. i dont understand why people are hyping FMA. it is backwards for performance. if you want more accuracy use fp64.

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Originally Posted by STaRGaZeR

I can't see anything in IDF's disclosed info about that, so unless you know something the rest of the world except Intel doesn't that's pure speculation and probably BS.

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Brush up on your English please. There is a whole lot of info on SB topic from last few IDFs,they even had SB class MPU demoed and running... Inform yourself before making a fool of yourself next time please :rolleyes:

So you know nothing about the uarch itself. Note the should in Anand's article. Thanks for confirming it ;)

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Originally Posted by STaRGaZeR

So you know nothing about the uarch itself. Note the should in Anand's article. Thanks for confirming it ;)

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Oh boy... There is even a diagram of uarch. straight from intel,posted in this very thread :rolleyes:. Again,read up before making a fool of yourself.

To help you out,here it is again:
http://info.nuje.de/sb.jpg

Evolution of Nehalem/Wesmere gen,nothing revolutionary(unless one considers AVX as revolutionary).

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Originally Posted by informal

Oh boy... There is even a diagram of uarch. straight from intel,posted in this very thread :rolleyes:. Again,read up before making a fool of yourself.

To help you out,here it is again:
http://info.nuje.de/sb.jpg

Evolution of Nehalem/Wesmere gen,nothing revolutionary(unless one considers AVX as revolutionary).

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sticks and stones may break his/her bones, but words will never hurt him/her.

oh...i see who are Intel fans here....

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Originally Posted by savantu

The original Sandy bridge was canceled and a new project was started.

Core was designed by Intel Israel. By 2005 Core was nearing completion and the uarch guys moved on to the next big thing : Gesher, later called Sandy Bridge.
Usually a CPU design takes 4 years at Intel : 1 is uarch, 2 is implementation , 1 is validation.While Intel Israel was thinking how Gesher will look like, Intel Oregon was busy implementing Nehalem.

But something happened : Gesher is cancelled 1 year after it started and work start all over again. Same team, same project , different name : Sandy Bridge.
Why did they give up the original ? Aimed too low, too complex, wrong path, too small of an improvement over Nehalem ? Who knows. AMD was busy defining K10 at the time, I don't remember hearing of Bulldozer in 2006.

Either way, Sandy Bridge and more likely Ivy Bridge should be just as revolutionary as Core, if Intel Israel wants to live up to the reputation they've earned.

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I don't think they think the same way as you do.
They don't live with their reputation. They just plain human who make a living in Intel.
Don't make this kind of statement that sounds like Intel Israel engineers/researchers are people who do this for glory please.
Without a lucrative benefits, the reputation is just BS

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Originally Posted by informal

Oh boy... There is even a diagram of uarch. straight from intel,posted in this very thread :rolleyes:. Again,read up before making a fool of yourself.

To help you out,here it is again:
http://info.nuje.de/sb.jpg

Evolution of Nehalem/Wesmere gen,nothing revolutionary(unless one considers AVX as revolutionary).

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Depends what you mean under word "revolutionary". If SB keeps Nehalem's macro-architecture but also will be faster then Nehalem by (lets say) 30% on the same freq, would you call it revolutionary? Or if Bulldozer having very different marchitecture then Phenom, will show very similar performance, would you call it revolutionary? And, yes, Netburst was revolutionary and that fact did not help it to gain popularity. After all the implementation decides...

30%? Let's wait and see when it comes to percentages ,Nehalem is on average ~20% over Penryn and it had a whole host of improvements (SMT,IMC,QPI,Turbo...). SB has AVX and some relatively minor uarch tweaks to accompany it,no "big" things as those that Nehalem brought. And you expect 30% over Nehalem...

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Originally Posted by informal

30%? Let's wait and see when it comes to percentages ,Nehalem is on average ~20% over Penryn and it had a whole host of improvements (SMT,IMC,QPI,Turbo...). SB has AVX and some relatively minor uarch tweaks to accompany it,no "big" things as those that Nehalem brought. And you expect 30% over Nehalem...

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I didn't say that I expect 30%. I just asked you what you mean saying "revolutionary" architecture. And no way you can predict performance basing on some macro-block-diagram. Many micro-architecture improvements just not fit/reflected by such diagrams.

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Originally Posted by kl0012

I didn't say that I expect 30%. I just asked you what you mean saying "revolutionary" architecture. And no way you can predict performance basing on some macro-block-diagram. Many micro-architecture improvements just not fit/reflected by such diagrams.

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Of course you can't accurately predict the outcome based on the diagram,but you can get a idea where intel is going(and it's going after evolution of Core design,again).Remember it was you who started to throw out the bs percantage numbers ;).
AMD on the other hand is saying farewell to Hound/Hammer and is going after throughput computing with accent on perf/watt/mm2 with the shared design methodology.I would really like to see the sizes of BD module and SB core compared side by side.

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Originally Posted by informal

BD cores get sported by HWinfo app.
Gen. 15h,code name Bulldozer. Since BD samples are in AMD's hands,it's logical they get support from some HW identification app. out there.

http://www.hwinfo.com/

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AMD Family 10h (DR-Ax/Bx, RB-Cx, BL-Cx, DA-Cx, HY-Dx, PH-Ex):
- AM2r2/AM3: Athlon/Sempron (Lima, Sargas), Athlon II/Neo (Kuma, Regor, Rana, Propus), Phenom II/Neo (Agena, Deneb, Callisto, Heka, Toliman), TWKR Black Edition
- Fr2/Fr4: Opteron (Barcelona, Shanghai, Suzuka, Budapest, Istanbul)
- G34: Opteron 61xx (Magny Cours)
- S1g3/g4: Turion II/Ultra, Athlon II, Phenom II
- ASB2: Athlon II Neo K, Turion II Neo K
AMD Family 11h (LG-Ax/Bx): S1g2: Sempron SI/NI/X2, Athlon QI/QL (Sable), Turion X2 Ultra/RM (Griffin)
AMD Family 12h (FS1)
AMD Family 15h: Bulldozer

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I've never heard about "E" stepping K10. Maybe the Thuban will come with "E" stepping. E0 or E2.

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Originally Posted by Oliverda

I've never heard about "E" stepping K10. Maybe the Thuban will come with "E" stepping. E0 or E2.

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I would rather expect Magny Cour

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Originally Posted by informal

SB is beefed up Nehalem,you can clearly see this from intel's disclosed info from past IDF's.The "big" change is AVX,but unfortunately no FMA support in SB. Other poster is implying that intel is reworking current SB core to make it better for BD time...

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+1

Thats what i mean...