if anyone needs a dump i found a good program to do it:)
http://img98.imageshack.us/img98/822...6021105ut7.png
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if anyone needs a dump i found a good program to do it:)
http://img98.imageshack.us/img98/822...6021105ut7.png
this code is from http://www.rebelshavenforum.com/sisu...;f=52;t=000050
http://www.amd.com/us-en/assets/cont...docs/32559.pdf
;---------------------------------------------------------------------------------------------------
; AMD AM2 DDR2 ROM Patcher Beta 1.0.5 06/09/2007
;---------------------------------------------------------------------------------------------------
;
; Source code writen by tictac. Updated for AM2 by Polygon of www.rebelshavenforum.com
; Website : z6.invisionfree.com/tictac
; Note : Free to be distribute/mod , Use it at your own risk
;
PHP Code:;---------------------------------------------------------------------------------------------------
;------------------------------CODE DEFINITION------------------------------------------------------
;---------------------------------------------------------------------------------------------------
use16 ; 16bit mode
address equ 0CF8h ; address port
data equ 0CFCh ; data port
dtl_add equ 08000C288h ; DRAM Timing Low address
dth_add equ 08000C28Ch ; DRAM Timing High address
dcl_add equ 08000C290h ; DRAM Configuration Low address
dch_add equ 08000C294h ; DRAM Configuration High address
dcm_add equ 08000C2A0h ; DRAM Controller Miscellaneous Data address
ROM_SIZE_IN_BLOCK = 1 ; 1 means ROM size is 1 block (512 bytes)
ROM_SIZE_IN_BYTE = ROM_SIZE_IN_BLOCK * 512
;---------------------------------------------------------------------
; DRAM Timing Low Address 08000C288h
;---------------------------------------------------------------------
; CAS Latency(dtl)
tcl equ dtl_add
tcl_data equ 0FFFFFFF8h ; CAS Latency (3bit)
tcl_3 equ 000000002h ; CAS 3
tcl_4 equ 000000003h ; CAS 4
tcl_5 equ 000000004h ; CAS 5
tcl_6 equ 000000005h ; CAS 6
; RAS to CAS Delay(dtl)
trcd equ dtl_add
trcd_data equ 0FFFFFF4Fh ; RAS to CAS Delay (2bit)
trcd_3 equ 000000000h ; 3 clock
trcd_4 equ 000000010h ; 4 clock
trcd_5 equ 000000020h ; 5 clock
trcd_6 equ 000000030h ; 6 clock
; Row Precharge Time(dtl)
trp equ dtl_add ;
trp_data equ 0FFFFFCFFh ; Row Precharge Time (2bit)
trp_3 equ 000000000h ; 3 clock
trp_4 equ 000000100h ; 4 clock
trp_5 equ 000000200h ; 5 clock
trp_6 equ 000000300h ; 6 clock
; Read Precharge Time(dtl)
trtp equ dtl_add ;
trtp_data equ 0FFFFF3FFh ; Read Precharge Time (1bit)
trtp_2 equ 000000000h ; 2/4 clock
trtp_3 equ 000000800h ; 3/5 clock
; Min. RAS active time(dtl)
tras equ dtl_add
tras_data equ 0FFFF0FFFh ; Min. RAS active time (4bit)
tras_5 equ 000002000h ; 5 clock
tras_6 equ 000003000h ; 6 clock
tras_7 equ 000004000h ; 7 clock
tras_8 equ 000005000h ; 8 clock
tras_9 equ 000006000h ; 9 clock
tras_10 equ 000007000h ; 10 clock
tras_11 equ 000008000h ; 11 clock
tras_12 equ 000009000h ; 12 clock
tras_13 equ 00000A000h ; 13 clock
tras_14 equ 00000B000h ; 14 clock
tras_15 equ 00000C000h ; 15 clock
tras_16 equ 00000D000h ; 16 clock
tras_17 equ 00000E000h ; 17 clock
tras_18 equ 00000F000h ; 18 clock
; Row Cycle Time(dtl)
trc equ dtl_add
trc_data equ 0FFF0FFFFh ; Row Cycle Time (4bit)
trc_11 equ 000000000h ; 11 clock
trc_12 equ 000010000h ; 12 clock
trc_13 equ 000020000h ; 13 clock
trc_14 equ 000030000h ; 14 clock
trc_15 equ 000040000h ; 15 clock
trc_16 equ 000050000h ; 16 clock
trc_17 equ 000060000h ; 17 clock
trc_18 equ 000070000h ; 18 clock
trc_19 equ 000080000h ; 19 clock
trc_20 equ 000090000h ; 20 clock
trc_21 equ 0000A0000h ; 21 clock
trc_22 equ 0000B0000h ; 22 clock
trc_23 equ 0000C0000h ; 23 clock
trc_24 equ 0000D0000h ; 24 clock
trc_25 equ 0000E0000h ; 25 clock
trc_26 equ 0000F0000h ; 26 clock
; Write Recovery Time(dtl)
twr equ dtl_add ;
twr_data equ 0FFCFFFFFh ; Write Recovery Time (2bit)
twr_3 equ 000000000h ; 3 clock
twr_4 equ 000100000h ; 4 clock
twr_5 equ 000200000h ; 5 clock
twr_6 equ 000300000h ; 6 clock
; RAS to RAS Delay Time(dtl)
trrd equ dtl_add ;
trrd_data equ 0FF3FFFFFh ; RAS to RAS Delay Time (2bit)
trrd_2 equ 000000000h ; 2 clock
trrd_3 equ 000400000h ; 3 clock
trrd_4 equ 000800000h ; 4 clock
trrd_5 equ 000C00000h ; 5 clock
;---------------------------------------------------------------------
; DRAM Timing High Address
;---------------------------------------------------------------------
; Write to read delay(dth)
twtr equ dth_add ;
twtr_data equ 0FFFFFCFFh ; Write to read delay (2bit)
twtr_1 equ 000000100h ; 1 clock
twtr_2 equ 000000200h ; 2 clock
twtr_3 equ 000000300h ; 3 clock
; Twrrd Delay(dth)
tWrrd equ dth_add ;
tWrrd_data equ 0FFFFF3FFh ; Twrrd Delay (2bit)
tWrrd_0 equ 000000000h ; 0 clock
tWrrd_1 equ 000000400h ; 1 clock
tWrrd_2 equ 000000800h ; 2 clock
tWrrd_3 equ 000000C00h ; 3 clock
; Twrwr Delay(dth)
twrwr equ dth_add ;
twrwr_data equ 0FFFFCFFFh ; Twrwr Delay (2bit)
twrwr_1 equ 000000000h ; 1 clock
twrwr_2 equ 000001000h ; 2 clock
twrwr_3 equ 000002000h ; 3 clock
; Trdrd Delay(dth)
trdrd equ dth_add ;
trdrd_data equ 0FFFF3FFFh ; Trdrd Delay (2bit)
trdrd_2 equ 000000000h ; 2 clock
trdrd_3 equ 000004000h ; 3 clock
trdrd_4 equ 000008000h ; 4 clock
trdrd_5 equ 00000C000h ; 5 clock
; Refresh Rate(dth)
tref equ dth_add
tref_data equ 0FFFCFFFFh ; Refresh Rate (2bit)
tref_15.6 equ 000010000h ; 15.6us
tref_7.8 equ 000020000h ; 7.8us
tref_3.9 equ 000030000h ; 3.9us
; Trfc0(dth)
trfc0 equ dch_add
trfc0_data equ 0FF8FFFFFh ; Maximum Async Latency (3bit)
trfc0_75 equ 000000000h ; 75 ns
trfc0_105 equ 000100000h ; 105 ns
trfc0_127.5 equ 000200000h ; 127.5 ns
trfc0_195 equ 000300000h ; 195 ns
trfc0_327.5 equ 000400000h ; 327.5 ns
; Trfc1(dth)
trfc1 equ dch_add
trfc1_data equ 0FC7FFFFFh ; Maximum Async Latency (3bit)
trfc1_75 equ 000000000h ; 75 ns
trfc1_105 equ 000800000h ; 105 ns
trfc1_127.5 equ 001000000h ; 127.5 ns
trfc1_195 equ 001800000h ; 195 ns
trfc1_327.5 equ 002000000h ; 327.5 ns
; Trfc2(dth)
trfc2 equ dch_add
trfc2_data equ 0E3FFFFFFh ; Maximum Async Latency (3bit)
trfc2_75 equ 000000000h ; 75 ns
trfc2_105 equ 004000000h ; 105 ns
trfc2_127.5 equ 008000000h ; 127.5 ns
trfc2_195 equ 00C000000h ; 195 ns
trfc2_327.5 equ 010000000h ; 327.5 ns
; Trfc3(dth)
trfc3 equ dch_add
trfc3_data equ 01FFFFFFFh ; Maximum Async Latency (3bit)
trfc3_75 equ 000000000h ; 75 ns
trfc3_105 equ 020000000h ; 105 ns
trfc3_127.5 equ 040000000h ; 127.5 ns
trfc3_195 equ 060000000h ; 195 ns
trfc3_327.5 equ 080000000h ; 327.5 ns
;---------------------------------------------------------------------
; DRAM Configuration Low Address
;---------------------------------------------------------------------
; Dimm Drive Strength(dcl)
dds equ dcl_add
dds_data equ 0FFFFFF7Fh ; Dimm Drive Strength (1bit)
dds_normal equ 000000000h ; NORMAL
dds_weak equ 000000080h ; WEAK
;---------------------------------------------------------------------
; DRAM Configuration High Address
;---------------------------------------------------------------------
; Memory Clock Frequency(dch)
mcf equ dch_add
mcf_data equ 0FFFFFFF8h ; Memory Clock Frequency (3bit)
mcf_200 equ 000000000h ; 400MHz
mcf_266 equ 000000001h ; 533MHz
mcf_333 equ 000000002h ; 667MHz
mcf_400 equ 000000003h ; 800MHz
; Maximum Async Latency(dch)
async equ dch_add
async_data equ 0FFFFFF0Fh ; Maximum Async Latency (4bit)
async_0 equ 000000000h ; 0 ns
async_1 equ 000000010h ; 1 ns
async_2 equ 000000020h ; 2 ns
async_3 equ 000000030h ; 3 ns
async_4 equ 000000040h ; 4 ns
async_5 equ 000000050h ; 5 ns
async_6 equ 000000060h ; 6 ns
async_7 equ 000000070h ; 7 ns
async_8 equ 000000080h ; 8 ns
async_9 equ 000000090h ; 9 ns
async_10 equ 0000000A0h ; 10ns
async_11 equ 0000000B0h ; 11ns
async_12 equ 0000000C0h ; 12ns
async_13 equ 0000000D0h ; 13ns
async_14 equ 0000000E0h ; 14ns
async_15 equ 0000000F0h ; 15ns
; Command Rate(dch)
cr equ dch_add
cr_data equ 0FFEFFFFFh ; Command Rate (1bit)
cr_1t equ 000000000h ; 1T
cr_2t equ 000100000h ; 2T
; Queue Bypass Max(dch)
qbp equ dch_add
qbp_data equ 0F0FFFFFFh ; Queue Bypass Max (4bit)
qbp_0 equ 000000000h ; 0 memclk cycles
qbp_1 equ 001000000h ; 1 memclk cycles
qbp_2 equ 002000000h ; 2 memclk cycles
qbp_3 equ 003000000h ; 3 memclk cycles
qbp_4 equ 004000000h ; 4 memclk cycles
qbp_5 equ 005000000h ; 5 memclk cycles
qbp_6 equ 006000000h ; 6 memclk cycles
qbp_7 equ 007000000h ; 7 memclk cycles
qbp_8 equ 008000000h ; 8 memclk cycles
qbp_9 equ 009000000h ; 9 memclk cycles
qbp_10 equ 00A000000h ; 10 memclk cycles
qbp_11 equ 00B000000h ; 11 memclk cycles
qbp_12 equ 00C000000h ; 12 memclk cycles
qbp_13 equ 00D000000h ; 13 memclk cycles
qbp_14 equ 00E000000h ; 14 memclk cycles
qbp_15 equ 00F000000h ; 15 memclk cycles
; Four Act Window(dch)
faw equ dch_add
faw_data equ 00FFFFFFFh ; Four Act Window (4bit)
faw_0x equ 000000000h ; No Tfaw Window Restriction
faw_8x equ 010000000h ; 8x
faw_9x equ 020000000h ; 9x
faw_10x equ 030000000h ; 10x
faw_11x equ 040000000h ; 11x
faw_12x equ 050000000h ; 12x
faw_13x equ 060000000h ; 13x
faw_14x equ 070000000h ; 14x
faw_15x equ 080000000h ; 15x
faw_16x equ 090000000h ; 16x
faw_17x equ 0A0000000h ; 17x
faw_18x equ 0B0000000h ; 18x
faw_19x equ 0C0000000h ; 19x
faw_20x equ 0D0000000h ; 20x
;---------------------------------------------------------------------
; DRAM Controller Miscellaneous Data address
;---------------------------------------------------------------------
; R/W Queue Bypass Max(dcm)
rwqbp equ dch_add
rwqbp_data equ 0FFFFFFF3h ; R/W Queue Bypass Max (2bit)
rwqbp_0 equ 000000000h ; 2 memclk cycles
rwqbp_1 equ 000000004h ; 4 memclk cycles
rwqbp_2 equ 000000008h ; 8 memclk cycles
rwqbp_3 equ 00000000Ch ; 16 memclk cycles
; Dynamic Idle Cycle Enable(dcm)
dicl equ dcm_add
dicl_data equ 0FFFFFFDFh ; Dynamic Idle Cycle Enable (1bit)
dicl_0 equ 000000000h ; Disable
dicl_0 equ 000000020h ; Enable
; Idle Cycle Limit(dcm)
icl equ dcm_add
icl_data equ 0FFFFFE3Fh ; Idle Cycle Limit (3bit)
icl_0 equ 000000000h ; 0 clock
icl_4 equ 000000040h ; 4 clock
icl_8 equ 000000080h ; 8 clock
icl_16 equ 0000000C0h ; 16clock
icl_32 equ 000000100h ; 32clock
icl_64 equ 000000140h ; 64clock
icl_128 equ 000000180h ; 128clock
icl_256 equ 0000001C0h ; 256clock
;---------------------------------------------------------------------------------------------------
;---------------------------ROM Header--------------------------------------------------------------
;---------------------------------------------------------------------------------------------------
ROMStart:
db 0x055, 0x0AA ; ROM Header 55,AA -> Bootable rom
db (ROMEnd - ROMStart)/512 ; ROM Size in 512byte
jmp MAIN
db 0 ; checksum, to be filled in later
;---------------------------------------------------------------------------------------------------
;---------------------------SUB-ROUTINE-------------------------------------------------------------
;---------------------------------------------------------------------------------------------------
macro MTT 0,1,2
{
mov eax,0 ; copy register address
mov ebx,1 ; copy register data
mov dx,address ; set port address
out dx,eax ; send address through the port
mov dx,data ; set port data
in eax,dx
and eax,2 ; set data in eax
or eax,ebx ; increase data
out dx,eax ; send data through port data
}
macro SAVE ; Save all register that will be affected by our code
{
pushfd
push eax
push ebx
push bx
push dx
push si
push ds
push bp
}
macro RETURN ; Restore register contents
{
pop bp
pop ds
pop si
pop dx
pop bx
pop ebx
pop eax
popfd
retf ; return far to system bios routine
}
;---------------------------------------------------------------------------------------------------
;---------------------------------------MAIN-ROUTINE------------------------------------------------
;---------------------------------------------------------------------------------------------------
times (256)-($-$$) db 0 ; locate Main routine at 100h
MAIN:
SAVE
;----------------------------------------------------------------------------------------------------
; Patch AM2 Memory Timing
MTT async,async_7,async_data ; Set max async latency to 7ns
;----------------------------------------------------------------------------------------------------
RETURN
times (ROM_SIZE_IN_BYTE-$) db 0
; The last byte (512th) will be the patch_byte for the checksum
; patch_byte is calculated and automagically inserted below
PREV_CHKSUM = 0
repeat $
load CHKSUM byte from %-1
CHKSUM = (PREV_CHKSUM + CHKSUM) mod 0x100
PREV_CHKSUM = CHKSUM
end repeat
store byte (0x100 - CHKSUM) at ($-1) ; store the patch_byte
ROMEnd:
;---------------------------------------CODE END-----------------------------------------------------
; How to set you memory timing?
; Just type MTT<space>timing name,timing value,timing data
; Exp : async memory to 7.0ns would be -> MTT async,async_7,async_data
; Press F9 to compile it with flat assembler
Could you run cinebench 64bit please?
I bet you can't wait for 8-core goodness:) :)
i need a new psu it cut out when trying to run the multiple cpu test:mad:
http://img484.imageshack.us/img484/7...6082841ib4.png
dual cpu would need new source code from amd... i havent have time to decode it anytime soon... sorry :(
unless you have K10 in hand.. LOL :D
my second email to asus :rolleyes: h
This email has been forwared to Engineering.
Best Regards,
Rob T.
Level 3 Support Engineer
Asus Technology
Http://usa.asus.com
Phone: (812)-282-2787
RMA: (510)739-3777 opt. 2
Thank You for using our technical support deparment. Our goal is 100% customer satisfaction from our valued customers. Please take just a moment to fill out our customer service survey. With these results we can improve our customer satisfaction and provide you with better service on your next call. Thank you for taking your time to complete this survey.
http://sip.asus.com/Survey/Questionn...063023308.aspx
---------- Original Message ----------
From : @yahoo.com
Sent : 9/3/2007 1:04:10 AM
To : "tsd@asus.com.tw"
Subject : Motherboard L1N64-SLI WS
[CASEID=WTM20070903054247048]
Apply date : 9/3/2007 12:54:24 AM
[Contact Information]
*Name : carter
*Email Address : @yahoo.com
Phone Number :
City : ny
*Country : United States
[Product Information]
*Product Type : Motherboard
*Product Model : L1N64-SLI WS
*Product S/N :
Place of Purchase : NEWEGG
*Date of Purchase : 2007/7/1
[Motherboard Specification]
*Motherboard Revision : 1.01g
*Motherboard BIOS Revision : 0505
[VGA Card Specification]
*VGA Card Vendor : ati
*VGA Card Model : aiw ve
*VGA Card Chipset : radeon
*VGA Card Driver : 6.11
[CPU Specification]
*CPU Vendor : amd
*CPU Type : fx70
*CPU Speed : 2.6
[Memory Specification]
*Memory Vendor : crucial
*Memory Model : tracer 1066
*Memory Capacity :
[HDD Specification]
HDD Vendor :
HDD Model :
HDD Capacity :
[Add-on Card Specificatio]
Add-on Card Vendor :
Add-on Card Type :
Add-on Card Model :
*Operating System : WinXP
[Problem Description]
i was wonder for the next bios ver. can you add timings to adjust drive strengths on the memory . i
use a program called memset in windows but it only changes the timings for cpu 0 and not cpu 1 also.
also can you enable cool&quiet to work with other multipliers instead of must the stock one.
these are the timings that would be most helpful changeable at the bios level\
DRAM Configuration Settings:
Memclock Tri-Stating............. - Disabled
Memory Hole Remapping............ - Enabled
Auto Optimize Bottom IO.......... - Enabled
DRAM Drive Strength.............. - Level 12
RAM Drive Weak/Normal Mode....... - Auto
CLK Enable Drive Strength........ - Auto
Chip Select Drive Strength....... - Auto
MEM Address Drive Strength....... - Auto
MEM Clock Drive Strength......... - Auto
Memory Data Drive Strength....... - Auto
Data Strobe Drive Strength....... - Auto
CS/ODT Pin Fine Delay............ - Auto
SLI-Ready Memory................. - Disable
Timing Mode...................... - Manual
Memory Clock Value/Limit......... - 400Mhz
Command Per Clock (1/2T)......... - Enable
CAS Latency Control (Tcl)........ - 003 CLK
Min RAS Active Time (Tras)....... - 005 CLK
RAS to CAS Delay................. - 004 CLK
Row Precharge Time (Trp)......... - 003 CLK
RAS to RAS Delay (Trrd).......... - 003 CLK
Row Cycle Time (Trc)............. - 011 CLK
DIMM 1 Row Refresh (Trfc0)....... - Auto
DIMM 2 Row Refresh (Trfc1)....... - 105 ns
DIMM 3 Row Refresh (Trfc2)....... - Auto
DIMM 4 Row Refresh (Trfc3)....... - 075 ns
Read Precharge Time (Trtp)....... - 003 CLK
Write Recovery Time (Twr)........ - 005 CLK
Read to Write Delay (Trwt)....... - 004 CLK
Write to Read Delay (Twtr) ...... - 003 CLK
Refresh Period (Tref)............ - 03.9 us
Max Asynch Latency............... - 006 ns
Bank Interleave.................. - Enabled
DRAM On-Die Termination.......... - 075 ohm
Read Delay From Rx FIFO.......... - 2.5 CLK
Read/Write Queue bypass.......... - 08 time
Bypass Maximum................... - 04 time
32 Byte Granularity.............. - Auto
Idle Cycle Limit................. - 04
Dynamic Counter.................. - Enable
Read DQS Skew.................... - Auto
thank you so much for your time :)
Any news on a L1N64 BIOS update to support Barcelona?
not yet but its going to be a fun winter:lsfight:
That is so wierd that it only adjusts settings of the one cpu. Good luck man, Id like to see this resolved as well for my future dual barcelona rig. Maybe more boards will come out for the 4x4 ?
Lol...if bios 0506 is any indication of what's to come, then you're not gonna be too happy as I didn't find ANY settings for timings in it.Quote:
Originally Posted by msimax
On another note, I spoke with Felix about that problem with memset a when I first got the board. He said that he would work on a fix and eventually pm'd me with one to try. I can't find the PM @ the moment, but IIRC, it was a link to the most current version of memset. You sure you're running that one?
Keep us updated on memset. Looks like it could be the only option to raise the fsb and adjust mem timings.Quote:
Originally Posted by s7e9h3n
@ OP
What BIOS options does the Asus have that can be adjusted reliably?
Thanks,
Ryan
yes i do have the latest and stumbled on the problem while running sandra, I would run the mem bandwidth get the results then change with memset and the score would go up but in the sandra info page it showed the settings took place on just one cpu while the other one remained stock. i then changed to the same settings in the bios and the scores went up further..:shrug:
but if Felix could add timings like systool which doesnt work, that would be great:up:
or if anybody can point me in the right direction using read&write utility:buddies:
have you tried using systool? i use it for changing AM2 memory timings and drive strength. it works pretty damn well, and has some options that even the dfi nf590 doesn't have ;)Quote:
Originally Posted by s7e9h3n
it doesnt recognize the mb or the cpu its says its not supported i made requestsQuote:
Originally Posted by ozzimark
emailed dumps amd pm wizzard he most be busy.
it doesn't recognize my dfi either, but it still works fine. :confused:
guess the issue lies with having to change timings for both cpus, as you said :(
can i have copy of the latest bios? i might be able to patch the timing.. gimme sometimes...
TicTac: How about patching the bios with the registers for quad core? ;)Quote:
Originally Posted by tictac
PM sent.... :yepp: :up:Quote:
Originally Posted by s7e9h3n
Ok, I just checked my system and memset 3.3 seems to work without a hitch changing the memory settings for both chipsets. Check what version you're running again.....Quote:
Originally Posted by s7e9h3n
yeah i have memset 3.3 but it doesnt change drive strengths and my d9 needs a weak driveQuote:
Originally Posted by s7e9h3n
ok i will try to preset weak drive strength for both controller... check pm :yepp:Quote:
Originally Posted by msimax
thank you TICTAC for your hard workQuote:
Originally Posted by tictac
i can now hit 1100mhz cant wait to try R9:up:
http://img485.imageshack.us/img485/4...7183549bs1.png