right, but we are only speculating, as always :) (hard time waiting some months :-) ). Interesting is too information about CPU clock 3.5 GHz+.
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right, but we are only speculating, as always :) (hard time waiting some months :-) ). Interesting is too information about CPU clock 3.5 GHz+.
~230 mm˛ is smaller. Isn't it?:DQuote:
Originally Posted by JF-AMD
It should be between 300 and 320mm^2,according to latest module size information. That's smaller than Lisbon.
1 module: ~30mm^2Quote:
Originally Posted by informal
4 modules: ~120mm^2
MC / HTT links / 8MB L3 cache: ~150mm^2 (K10.5 @ 45nm: MC / HTT links / 6MB L3 cache: 110mm^2)
~270mm^2?
if 6MB at 45nm is 110mm2, no way 8MB at 32nm is going to be that much larger, if anything i would have expected smaller.
Assuming I've done my math correctly, an 8MB cache @ 32nm would be equal to 104.13mm2 I'm assuming transistors scale linearly with size as well and that a 6MB cache @ 45nm is 110mm2.Quote:
Originally Posted by Manicdan
4-core K10 @ 45nm: 260mm^2Quote:
Originally Posted by Manicdan
6-core K10 @ 45nm: 340mm^2
So coreless K10 (MC + HTT links + 6MB L3 cache = 100-110mm^2
im just saying your 150mm2 estimate for 8MB and the rest on a smaller node sounds off. i would expect like 90-100mm2 TOPS, add in the 4 modules of ~125mm2, total i bet dosnt break 225mm2Quote:
Originally Posted by qcmadness
I think it's unlikely that the cores including L2 is smaller than the L3, since the L2 is at 4x2Mb and the L3 is at 8Mb. It would be if you included IMC and other parts in the L3-numbers.
300-320 mm˛ sound unreal for me for 4 module version or it will have 16MB L3.:)Quote:
Originally Posted by informal
4x30.9 = 123.6 mm˛ for the 4 modules
2 MB L2 = 12.62 mm˛
IMHO 2MB L3 cache needs less area than 2MB L2 but now calculate with that 12.62 mm˛/2MB.
4x12.62 mm˛ = 50.48 mm˛ for the 8MB L3
So the 4 modules and the L3 takes ~174 mm˛. I don't think that the IMC and the HT links need 126-146 mm˛.
...or it has a hidden GPU or few plus modules or anything..:)
L3 is in four 2MB slices:Quote:
Originally Posted by -Boris-
"An 8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing
An 8MB level 3 cache, composed of 4 independent 2MB subcaches, is built on a 32nm SOI process. It features column-select aliasing to improve area efficiency, supply gating and floating bitlines to reduce leakage power, and centralized redundant row and column blocks to improve yield and testability. The cache operates above 2.4GHz at 1.1V."
The photoshopped die photo suggests that there is a lot of space between modules, NB, L3 subcaches and I/O. I'd say: 300 +/-20 mm^2.
Why do they design a chip with so much empty space? It looks like lots of space just going to waste.Quote:
Originally Posted by Dresdenboy
Did you miss the "photoshopped" part? ;)Quote:
Originally Posted by -Boris-
Because of the high frequency design maybe...?Quote:
Originally Posted by -Boris-
No, I did not. Take a close look at the picture and you see that the altered dies and IMC are really lousy shoops. But the space empty between them don't show these signs.Quote:
Originally Posted by Shadov
Why would Globalfoundries put som much effort in shooping these empty spaces that they look real, when they don't care about the rest looks like :banana::banana::banana::banana:?
what about 3.5 Ghz clocks? Do u think guys, its clock without Turbo?
I would guess, according to the unchanging voltage(0.8v-1.3v), BD will NOT be a high(er) frequency design. The frequency cannot reach much higher due to the high voltage, otherwise the TDP will be out of range, by a large margin.Quote:
Originally Posted by Oliverda
What? Voltage unchanged compared to what? Frequncy cannot reach much higher than what? Compared to 45nm BD? Which chip within the same architecture are you refering to?Quote:
Originally Posted by superrugal
We don't know anything about frequencies yet.
Look at Intel CPUs on 32nm, lower voltage but same or higher frequency. When going on smaller nodes you can increase the frequency while lowering or keeping the same voltage.Quote:
Originally Posted by superrugal
superrugal:SRRY,but your meaning is "bull*hit"...Thuban is total diferent design (BD design is possible as high frequency), have 1.125-1.4V, and do u using ussually 1.5V with air for 24/7 OC...can more than 4 GHz stable. But it is not about voltage, but as said about design chip.
Not really.:)Quote:
Originally Posted by superrugal
Athlon 64 FX-60 (2600 MHz, 125W TDP, 90nm SOI, Toledo) - Vcore: 1.350V
Phenom II X4 970 (3500 MHz, 125W TDP, 45nm SOI, Deneb) - Vcore: 1.350V
Also the FX-60 is only dual core, and then there's the x6 at 3200mhz with the same 125WTDP and similar vcore ranges.Quote:
Originally Posted by Oliverda
And it's still the same base architecture. The comparsion should be more like Coppermine vs. Northwood.Quote:
Originally Posted by ryboto
I didn't say, the space is empty ;) There are several options to fill it. Another reason could still be to make the die look bigger. But where to put the HT-PHY and DDR3 pads then?Quote:
Originally Posted by -Boris-
@Oliverda:
The space is not necessary for a high frequency design. But this could be a reason for the module's sizes (more latches and so).
http://chip-architect.com/news/AMD_Bulldozer.jpg
inverse photoshopping effort...
Regards, Hans