If you have time, I am curious to see if those differences are really code or data and not some crappy byte appended by the compiler.Quote:
Originally Posted by mikeyakame
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If you have time, I am curious to see if those differences are really code or data and not some crappy byte appended by the compiler.Quote:
Originally Posted by mikeyakame
You'll need to bump your NB voltage to around 1.69 and your CPU voltage to 1.5v in order to get 480+. You will likely hit a hard wall at around 495 or so FSB.Quote:
Originally Posted by drew and not u
definitely changes in code in 1B module. I've gotta go to work shortly but here I had a quick look at both 1B of 0501 and 0601. This is just one example, seg address 00010d66, 00010d6e differ for example.Quote:
Originally Posted by Brama
in 0501, 00010d66 is 0x05h, 00010d6e is 0x1Ch.
in 0601, 00010d66 is 0x06h, 00010d6e is 0x1Dh.
this is disassembly from 0501, just a small area covering those 2 bytes.
þ
seg000:00010D60 ; ---------------------------------------------------------------------------
seg000:00010D60 or al, 1
seg000:00010D62 add dh, al
seg000:00010D64 inc esp
seg000:00010D65 push cs
seg000:00010D66 add eax, 10F44C6h
seg000:00010D6B mov byte ptr [eax+edx+1Ch], 0C6h ; 'ã'
seg000:00010D70 inc esp
seg000:00010D71 adc [edx], eax
seg000:00010D73 mov edx, es:[esi]
seg000:00010D76 dec eax
seg000:00010D77 sub cl, [ecx-75D9EDACh]
seg000:00010D7D push ss
seg000:00010D7E dec edx
seg000:00010D7F sub cl, [eax+44C71C54h]
this is 0601.
seg000:00010D60 ; ---------------------------------------------------------------------------
seg000:00010D60 or al, 1
seg000:00010D62 add dh, al
seg000:00010D64 inc esp
seg000:00010D65 push cs
seg000:00010D66 push es
seg000:00010D67 mov byte ptr [edi+ecx+1], 0C6h ; 'ã'
seg000:00010D6C inc esp
seg000:00010D6D adc ds:21144C6h, bl
seg000:00010D73 mov edx, es:[esi]
seg000:00010D76 dec eax
seg000:00010D77 sub cl, [ecx-75D9EDACh]
seg000:00010D7D push ss
seg000:00010D7E dec edx
seg000:00010D7F sub cl, [eax+44C71C54h]
Now what It means, I dont have the faintest without analysing the whole binary roM, but at 10d6d, the add instruction is replaced by push ES, which I assume pushes whatever the contents of ES register is onto the stack in 0601. My asm isn't the best though, but it's enough to make sense of things i suppose.
Anyone has an idea on how to make the system stable when using all 4 Slots of the RAM?
Im having problem with this, and i already have my NB voltage at 1.69V.
yeah take ur nb voltage down ;>Quote:
Originally Posted by TheVaLVe
its way too high. try loosening tPTP (pre to pre) to 2. I had 4 1gb sticks running for a while it wasn't an issue, just couldnt overclock them that much, try raising vdimm also, and playing with dram clock skews.
edit: oh hmm you are using 2x2 + 2x1? good god good luck :D increase tRFC to 70, tAPTRD / tAPTAD to 7 each, (all pre to ref/act)
I cant take the nb voltage down. Im able to be stable at 490 FSB with this voltage, and 1.67V if i put only 2 sticks. Vdimm is already at 2.20 V with overvoltage 0.10V.
Cheers for the tips, gonna try the timing and skew things. About the skew, should i put it into delay and whats the general good value to set as a reference.
Yea its 2x2 + 2x1. No prob running 2 sticks, the prob is, i cant stand seeing 6 gigs of my ballistix ram lying around....:( and they capable of doing 1200 just as my OCZ does.
hard to say whether you need advance or delay on a particular channel, since it will depend on the IC's used on the sticks. Micron IC's prefer 100+ps advance skew, Powerchips prefer neutral or close to neutral skews. Elpida can need delay skews.Quote:
Originally Posted by TheVaLVe
Best way to figure it out is to put one stick of each in the channel you want to use, push it up to the highest frequency you can get it to post at that gives errors in Memtest86+, then adjust skew either way step by step and see if the errors in memtest increase or decrease. Best to use is test #5. If they decrease then you are getting hotter, if they increase you are getting colder. It'll be near impossible to deskew 2 completely opposite types of IC's with the RF since there is no individual slot skews.
I managed to pull this off on a P45 P5Q deluxe as it has A1/A2/B1/B2 but I dont know how much luck you'll have with only A / B, hopefully the IC's are similar in their skewness.
Thanks! That definitely helped, I dunno why I was so hesitant to bump the NB, even now at 1.65 it only gets up to around 40c. Was able to get it to 485 FSB. CPU temps max around 62C, but hopefully my friends TRUE will perform better than the Nirvana I've been using. Either way I saved a 3.6 profile for him to use 24/7.Quote:
Originally Posted by 003
Yeah, keep in mind the NB is on a 90nm process, it could probably take 2.0v with the right cooling on VRMs and such... :D
Cheers m8, its working great now. I had to set 200PS advance in both channels, and woala rock stable at 485 FSB. I know i had to lower 5 FSB, but no biggie as long its stable now. Thanks for ur suggestion :D
Quote:
Originally Posted by mikeyakame
Thanks.Quote:
Originally Posted by mikeyakame
The code seems a double loop to store some values in a memory area. Anyway, not a lot of changes between the two BIOSes.
i'll post up the rest of the disassembled byte comparisons for the changes in 1B for 0501 / 0601 tonight. Been a bit sidetracked playing around with Windows 7 M3 build and don't have IDA pro installed yet on it.Quote:
Originally Posted by Brama
Interesting...Ultra Compare has 2 binary compare modes, one is fast, other is smart, fast picks up 50 bytes diff, while smart only picks up 46 bytes!
i wont bother including string changes since they are visible with hex editor
[ 1 ] = 0501
[ 2 ] = 0601
00002e00 [ 1 ] * 30 35 30 31 00 26 09 08 20 00 00 00 00 00 00 00 0501.&.. .......
00002e00 [ 2 ] * 30 36 30 31 00 15 10 08 20 00 00 00 00 00 00 00 0601.... .......
00002e05-07h
0501 -> seg000:00002E05 db 26h, 9, 8
0601 -> seg000:00002E05 db 15h, 10h, 8
byte declares for bios revision dmi data i think
following changes are related to ACPI tables.
0001b410 [ 1 ] * 44 0B 46 C7 44 0C 01 00 C6 44 0E 05 C6 44 0F 01 D.FÇD...ÆD..ÆD..
0001b410 [ 2 ] * 44 0B 46 C7 44 0C 01 00 C6 44 0E 06 C6 44 0F 01 D.FÇD...ÆD..ÆD..
0001b420 [ 1 ] * C6 44 10 1C C6 44 11 02 C7 44 12 4C B1 C7 44 14 ÆD..ÆD..ÇD.L±ÇD.
0001b420 [ 2 ] * C6 44 10 1D C6 44 11 02 C7 44 12 4C B1 C7 44 14 ÆD..ÆD..ÇD.L±ÇD.
0001b41b, 0001b423 differ. i've included what appears to be a function as exists directly below a return far (retf)
00051950 [ 1 ] * 54 20 26 08 00 09 4D 53 46 54 97 00 00 00 00 00 T &...MSFT—.....
00051950 [ 2 ] * 54 20 15 08 00 10 4D 53 46 54 97 00 00 00 00 00 T ....MSFT—.....
00051a50 [ 1 ] * 54 20 26 08 00 09 4D 53 46 54 97 00 00 00 00 00 T &...MSFT—.....
00051a50 [ 2 ] * 54 20 15 08 00 10 4D 53 46 54 97 00 00 00 00 00 T ....MSFT—.....
00051b50 [ 1 ] * 50 20 26 08 00 09 4D 53 46 54 97 00 00 00 00 00 P &...MSFT—.....
00051b50 [ 2 ] * 50 20 15 08 00 10 4D 53 46 54 97 00 00 00 00 00 P ....MSFT—.....
00051be0 [ 1 ] * 50 20 26 08 00 09 4D 53 46 54 97 00 00 00 00 00 P &...MSFT—.....
00051be0 [ 2 ] * 50 20 15 08 00 10 4D 53 46 54 97 00 00 00 00 00 P ....MSFT—.....
00051ce0 [ 1 ] * 43 20 26 08 00 09 4D 53 46 54 97 00 00 00 00 00 C &...MSFT—.....
00051ce0 [ 2 ] * 43 20 15 08 00 10 4D 53 46 54 97 00 00 00 00 00 C ....MSFT—.....
00051d50 [ 1 ] * 47 20 26 08 00 09 4D 53 46 54 97 00 00 00 00 00 G &...MSFT—.....
00051d50 [ 2 ] * 47 20 15 08 00 10 4D 53 46 54 97 00 00 00 00 00 G ....MSFT—.....
0005c6f0 [ 1 ] * 4D 20 26 08 00 09 4D 53 46 54 97 00 00 00 00 00 M &...MSFT—.....
0005c6f0 [ 2 ] * 4D 20 15 08 00 10 4D 53 46 54 97 00 00 00 00 00 M ....MSFT—.....
00068c00 [ 1 ] * 26 08 00 09 4D 53 46 54 97 00 00 00 00 00 00 00 &...MSFT—.......
00068c00 [ 2 ] * 15 08 00 10 4D 53 46 54 97 00 00 00 00 00 00 00 ....MSFT—.......
00068cb0 [ 1 ] * 49 43 20 26 08 00 09 4D 53 46 54 97 00 00 00 00 IC &...MSFT—....
00068cb0 [ 2 ] * 49 43 20 15 08 00 10 4D 53 46 54 97 00 00 00 00 IC ....MSFT—....
above are all changes made to ACPI table struct data member, which accounts for 18 bytes of change.
ie 00068cb3 - 00068cb6 which for 0501 is 09000826h and 0601 is 10000815h, its a 32bit unsigned int (dword).
Struct for general acpi system header looks like so:
struct acpi_table_header {
char TABLE_SIGNATURE[4]; /* name of table */
uint32_t TABLE_LENGTH; /* length in bytes 0x00000028 , size of this struct (24 bytes) + uint32_t table_offset_entry[1] (pointer to uint32_t pointer array with 1 member consisting of memory location for table offset) */
unsigned char ACPI_REVISION; /* rsdt is ACPI v1.0 table so value is 1 */
unsigned char TABLE_CHECKSUM; /* must always be 0 */
char OEM_ID[6]; /* A_M_I_ */
char OEM_TABLEID[8]; /* OEMXXXX[:space:] */
uint32_t OEM_COMPILE_REVISION; /* 0501 rev is 0x09000826, 0601 is 0x10000815. these are the 2 different bytes in each table struct*/
char CREATOR_ID[4]; /* acpi source compiler creator 4 char long id ( msft in this case )*/
uint32_t CREATOR_ASL_REVISION; /* revision of acpi source compiler ( 0x00000097 )*/
}
ie. for rsdt
struct acpi_table_rsdt {
struct acpi_table_header header;
uint32_t table_offset_entry[1]; /* mem offset ptr to push into esi register i think */
}
so most changes from what I can see account for a newer compile revision of the acpi tables!
You explained what I felt. :)Quote:
Originally Posted by mikeyakame
Very minor changes between 501 and 601.
Hi,Quote:
AI Overclock Tuner.............................. Manual
CPU Ratio Setting............................... 8.5
FSB Strap to North Bridge....................... 333MHz
FSB Frequency................................... 485MHz
PCI-E Frequency................................. 110MHz
DRAM Frequency.................................. DDR2 – 1164MHz
DRAM Command Rate............................... 2N
DRAM CMD Skew on Channel A...................... Auto
DRAM CMD Skew on Channel B...................... Auto
DRAM CLK Skew on Channel A...................... 200ps
DRAM CLK Skew on Channel B...................... 200ps
DRAM Timing Control............................. Manuel 5-5-5-15
DRAM Static Read Control........................ disabled
AI Clock Twister................................ Stronger
AI Transaction Twister.......................... Manual
Common Performance Level.................... 07
Pull-In of CHA PH1.......................... Disabled
Pull-In of CHA PH2.......................... Disabled
Pull-In of CHA PH3.......................... Disabled
Pull-In of CHA PH4.......................... Disabled
Pull-In of CHB PH1.......................... Disabled
Pull-In of CHB PH2.......................... Disabled
Pull-In of CHB PH3.......................... Disabled
Pull-In of CHB PH4.......................... Disabled
CPU Voltage..................................... 1.4V
CPU PLL Voltage................................. 1.6V
Northbridge Voltage............................. 1.65V
DRAM Voltage.................................... 1.9V
FSB Termination Voltage......................... 1.5V
South Bridge Voltage............................ 1.05V
SB 1.50V Voltage................................ 1.5V
Loadline Calibration............................ Enabled
CPU GTL Voltage REF............................. 0.63x
NB GTL Voltage REF.............................. 0.67x
DRAM Controller Voltage REF..................... DDR REF
DRAM Channel A Voltage REF...................... DDR_REF
DRAM Channel A Voltage REF........................DDR_REF
My config
Rampage formula (bios 501)
E8500 CO (4.122ghz)
Gskill pc8800 Pi (582mhz à 1.9v)
In fact my problem is that i ran OCCT 5 hours with no problems, CPu stress test for 4 hours, and ingame my pc work fine.
But when i run Prime95, its stop at the third test and said me "FATAL ERROR: Rounding was 0.5, expected less than 0.4".
I ve done 3 pass of memtest and no errors.
What is the problem, thanks
Try a little more vcore.Quote:
Originally Posted by mesmerize
Just go the Rampage Formula with bios0216. Doesnt even recognize my Q9650 and calls it an unknown CPU :rolleyes:
Which bios version is the best to use right now and which is the best way to flash the bios? I am assuming the USB drive would be easy enough!
Zucker2k,
When you've got some time would you be able to run a few scenarios for me with AI Clock Twister settings. It seems like they are giving me fixed values from what is probably a fixed table for each setting. DRAM Clock Skews need to be set to Normal on CHA/CHB and all CPL phase pull ins must be disabled. DRAM Static Read shouldn't affect the the results from what I can tell.
Values to go here.
AI Clock Twister
-Lighter -> -Stronger
Dimm1 Fine Clock Delay 5T
Dimm2 Fine Clock Delay 3T
Dimm3 Fine Clock Delay 5T
Dimm4 Fine Clock Delay 3T
Took a lot of samples at PL7/PL8 with all clock twister values and varying Phase pull-ins, and those values appear to be common.
I have a good 20 or so MCHBAR register dumps to analyze and compare for all the samples I took tonight, which will take me a good week to properly go over and over to isolate particular register values for each change from the changes to counter registers for things like Errors, Load Performance, Bus clock ticks, Transit delays, etc. Intel MCHBAR docs for all chipsets are sort of vague, and for the most part just outline the critical register values with regard to memory timings, memory segment addressing, memory performance counters, and so on.
There needs to be more people involved to give their values for certain FSBs. The xT or yT is because when I changed from 483MHz FSB to 485MHz FSB the values seemed to get more aggressive. I can't explain this.
It possibly changes some other hidden MCHBAR registers, but for time being until we can know their locations Dimm Clock Fine Delay seems to be the most useful across the board.
DRAM Clock Skew
50PS is equivalent to 1T which may be in UCLKs, differential clocks.
Advance 50PS = -1T
Delay 50PS = +1T
These can be checked with Everest Ultimate Edition under the Dimm1-4 Fine Clock Delay timings in Chipset. Normal is equivalent to the value set by the skew tables for the memory subsystem. This might vary between different Memory Dimm's. I only have 2 sets to test with unfortunately.
AI Clock Twister also effects AI Transaction Booster when set to Auto. More aggressive AI Clock Twister setting increases likelihood of Phase Pull-Ins for Common Performance level.
AI Trans Booster AUTO, 5:6 Divider with AI Clock Twister Stronger, CPL 10, Phase Pull-in PHA1
AI Trans Booster AUTO, 4:5 Divider with AI Clock Twister Stronger, CPL 9, Phase Pull-In PHA1, PHB1
AI Trans Booster AUTO, 3:4 Divider with AI Clock Twister Stronger, CPL 7, Phase Pull-in PHA1, PHA3, PHB1, PHB3
AI Trans Booster AUTO, 2:3 Divider with AI Clock Twister Stronger, CPL 6, Phase Pull-in PHA1, PHB1
AI Trans Booster AUTO, 1:1 Divider with AI Clock Twister Stronger, CPL 5, Phase Pull-in PHA1
Those are only scenarios I can recall. Its been a while but I am pretty sure thats the values the bios gives.
Phase pull-ins for Common Performance Level in AI Transaction Booster.
Number of phases is determined by combination of Internal Memory Divider and Bus BCLK Scalable frequency.
4:5 divider has 4 phases on each memory channel, and 5 phases on mch.
10:12 divider aka 5:6 has 5 phases on each memory channel and 6 phases on mch.
Order of pulling in phases:
First Phase
Second Last Phase (or last depending on phase count, for > 4 phases use second last)
Last Phase
Second Phase
Middle Phase (if using 10:12 divider)
Channel A Phases are the most aggresive, by incrementing Read Delay Phase Adjust Tck value.
This value in Everest relates to tRD transaction BUS_DRDY assert skew. Neutral/0T is Intel spec max turnaround for data to be ready on the bus for given Performance Level. This is the delay skew between DRAM burst read command assert until the MCH can issue BUS_DRDY assert and burst data transmission across the bus to destination.
The advance in skew for a given phase, is set by the number of phases. As more phases are added, each additional phase incurs a penalty of [ 2 ^ nPhase - 1 ]T clocks turnaround for transactions.
Phase 1 = tRD skew advance +1T [ 2 ^ 1 - 1 ]
Phase 2 = tRD skew advance +2T [ 2 ^ 2 - 1 ]
Phase 3 = tRD skew advance +4T [ 2 ^ 3 - 1 ]
Phase 4 = tRD skew advance +8T [ 2 ^ 4 - 1 ]
Phase 5 = tRD skew advance +16T [ 2 ^ 5 - 1 ]
Total Read Delay Phase Adjust clocks
Channel B Phases are the least aggressive, by generally only incrementing Dimm Fine Clock Delay clocks. 1T increases are the norm, and not on all phases. 1T = 50ps DRAM clock skew delay.
You need 0407 or higher (in my opinion 0407 is the one that OC RAM best, for CPU OC it doesn´t matter).Quote:
Originally Posted by GoodToGo
Use ASUS EZ Flash 2 and a USB stick (FAT16 or 32) and your system at default (no OC) to flash bios is one of the safe way.
Wow, this is a project in itself. I will find time and give you some results soon. Here are my current figures....Quote:
Originally Posted by mikeyakame
Edit: Clockskew set to normal for all channels, all phases disabled, cpl set to 8; I get the same figures for 8.5x500 fsb ie. 1-5-1-4.
PS: I'm not sure what impact ai transaction booster has on latencies, but lighter, light, and moderate, reduces Read speed about 300 MB/s and boosts Copy speed by about 1200
So by the looks you have your dimms in slots A2/B2 correct?
Ordered this board and will use it for my underutilized QX9770. I have 4GB OCZ Flex II PC2 9200 on hand and 2GB OCZ Flex XLC PC2 9600 on the way with the Rampage. I have read that before I fire this girl up, remove the NB heatsink and get rid of the TIM and reapply better stuff. I would want to know which water-block most are using as I will go with water-cooling off the bat. And what type of MOSFET coolers are people using when they remove the heatpipe?
Haven't seen too many pics in this thread. (though a little lazy to go through all 60 pages or so ... :eek::p:)
No, A1, B1 (Dimm1, Dimm3); Ai Clock Twister = Stronger; DRAM Static Read = Enabled. I cycled through Ai Clock Twister and latencies remained the same, 1-5-1-4. I'm on bios 0601.Quote:
Originally Posted by mikeyakame
Where can I get the latest BIOS? 0601 ... will need in a week or so for when the board arrives here in Alaska! :D
Bios Page
Linky
For some reason the 0407 link is not working. Got all the versions newer than that though.
I was playing with the board yesterday and it has a very organized bios options. Can someone please post relevant settings that they use to overclock their CPU?
Also where is the option to set the PCI frequency or disable it?