AMD embraces AVX making a new superset with SSE5(256bit support)

Printable View

Show 100 post(s) from this thread on one page

05-06-2009, 11:20 PM
Russian

Quote:

Originally Posted by Brother Esau

You know I get a little sick of this Bull :banana::banana::banana::banana: childish name calling and labeling that you troublemakers are oh so fond of! I see all of you with the Balls to call everybody else Fan Boys because it does not coincide with you line of think or your preference ....well tough :banana::banana::banana::banana:!

The fact all of you that are continuously spouting AMD Fan Boy .. AMD Fan Boy only goes to prove one thing that its Intel or the Highway and we are just commoners and beneath all of you because we prefer AMD ......Get Real and Grow Up :rolleyes: How is that you are not a Fan Boy and all of the other chumps that come into these AMD Threads and Purposely Derail them?:rolleyes:.....Once again...OK:rofl:

Speaking of Intel who do you have to thank for your Insight into Overclocking a CPU with a IMC ??? You guessed it the AMD Fan Boys that you all kick ond torment relentlessly ...You guys make me laugh! Self Proclaimed experts talking a Bunch of :banana::banana::banana::banana: is all you do when we were the Ones Debugging Overclocking Quad Core with IMC you were all Talking :banana::banana::banana::banana: and Making Fun of us ..... I guarantee you that for you die Hard Intel Fans here you would know nothing about not blowing up your Precious Nehalem Rigs if it wasn't for us doing all of the work for the Past Year and a Half ya'll wouldn't have a clue in hell and there sure as hell would have been allot of Toasted CPU'S and Motherboards if it weren't for all of us lowly Commoners in the AMD Sector.

Do me a favor all of you shut up and be thankful for what we have given you we are all tired of hearing your Whiny Frigging Negative dysfunctional Rhetoric so piss off or be civil and have some damn manners and respect towards your fellow man.

Strong with the cursewords are we today?
05-06-2009, 11:24 PM
Brother Esau

Well I am sick and tired of these jerks poking fun of everyone and ruining everyone else s good time because they don't posses any manners respect or civility towards others. Its not right and its just Rude!
05-06-2009, 11:33 PM
gallag

Quote:

Originally Posted by Macadamia

LOL, UBER PWNAGE. Thanks to AMD for the big clarification.

I already mentioned prior that SSE5 was a superset in general due to its implementation of FMA, but several specs did not adhere. Now add AMD being fully compliant with AVX to the previous setting, it still has FMA inside the CPU spec itself.

So AMD beats Intel to releasing their first SSE5AVX CPU? Whoa.

What an apt description of... you? :ROTF:

AMD always uber pownes, Everyone knows that, If roadmaps and future plans actually made profit they would deffo make more cash than Intel.

AMD, the "we have it sorted in two years" company.
05-06-2009, 11:35 PM
informal

Gallag can you stay on "AVX + SSE5 in Bulldozer" topic please? Thanks.
05-06-2009, 11:41 PM
Shintai

Quote:

Originally Posted by informal

So Shintai what's your comment on this new development? :p: What happened with your "superset busting"?:shrug:

You ate marketing as usual. Forgot the game and ran away with the ball.

Its still not a superset, its still not fully support. Its a partial support packed in some nice marketing words.

I think you mix AVX alike instructions with being support. They dont even support the same FMA do they? :clap:

Quote:

At some future point, we will likely adopt Intel's newer FMA definition as well

Quote:

Since we don't control the definition of AVX, all we can say for sure is that we expect our initial products to be compatible with version 5 of the specification (the most recent one, as of this writing, published in January of 2009), except for the FMA instructions, which we expect will be compatible with version 3 (published in August of 2008).

Compatible with something Intel will never release? LOL!
05-06-2009, 11:42 PM
Smartidiot89

I agree with Brother Esau :rolleyes:

Seriously, we "AMD Fanboys" always claimed that Intel had some sort of microstuttering due to their SLOW FSB bus, and the IMC in the chipset, while AMD used the much fast HyperTransport and a integrated IMC but did anyone listen? NO!

But then the Holy Grail our Messiah and Savior, i present Core i7 saw the light, and the Intel people crawled up from their mothers basements and said "Hey, those stupid AMD fanboys might've been right!", cause now, Intel had QPI(Oh sorry, was meent to say HyperTransport) and a integrated memory controller.

Now it's a more or less accepted theory in the hardware enthusiast community, that Conroe did suffer from some sort of microstuttering while AMD had "Smoother". Intel are awesome at copying AMD, hell yeah.

Stated my point flame and puts on flamesuit :cool:
05-06-2009, 11:46 PM
Hornet331

i smell a imminent lockage of this thread. :rofl:
05-06-2009, 11:47 PM
informal

Quote:

Originally Posted by Shintai

You ate marketing as usual. Forgot the game and ran away with the ball.

Its still not a superset, its still not fully support. Its a partial support packed in some nice marketing words.

I think you mix AVX alike instructions with being support. They dont even support the same FMA do they? :clap:

Compatible with something Intel will never release? LOL!

First of all you are wrong,again. Look at devcentral post again:

Quote:

Since we don't control the definition of AVX, all we can say for sure is that we expect our initial products to be compatible with version 5 of the specification (the most recent one, as of this writing, published in January of 2009), except for the FMA instructions, which we expect will be compatible with version 3 (published in August of 2008).

FMA is NOT the part of the AVX and is detected separately.Plus FMA is not even in Sandy Bridge which is only AVX(ie. 256b wide vector support with new AVX instructions). SB's successor is FMA3 compatible but i wouldn't be surprised if intel drops inferior FMA3 format by that time and goes with more powerful FMA4 that will AMD use in BD. AMD WILL support FMA3 with BD core shrink,so there will be compatibility with FMA3 too.

So to sum it up: AVX is not the same package as FMA.FMA is additional instructions that are not in the AVX set(AVX set that will be in SB cores)

Plus you fail to see that AMD's XOP,CVT16,FMA3 is additional instr. set added to AVX spec. and compatible with AVX decoding scheme.It's just an added value,not an AMD's version of AVX. So again,you failed :(.
05-06-2009, 11:59 PM
informal

FMA IS not the same as AVX version that will be in Sandy Bridge.It is detected separately and this is natural since Sandy Bridge WILL NOT have FMA at all! FMA is projected to be in SB's successor(a shrink?).

So AMD will support full AVX plus their own XOP,CVT16 and FMA4 instruction set extensions. The FMA3 support will come with Bulldozer's shrink,but FMA3 is inferior in every way to FMA4(the reason AMD will do it is just to stay compatible with Ivy Bridge as they must be-they are a smaller player here).

Quote from intel rep as a response to an user inquiry into SB and AVX without FMA:

Quote:

Originally Posted by Mr. Levicki

I have heard that Sandy Bridge won't have FMA implementation.

If that rumor is true, I would really like to know who decided that x86 developers should wait more to finally get fused multiply-add isntruction? Is it so useless in real code or the marketing department has again started doing an engineer's job?

Hereby I publicly voice my displeasure over that poor decision.

Quote:

Originally Posted by Mark Buxton

Hi Igor,

Sandy Bridge will not have FMA, it's targeted for a future processor. I apologize if there is any confusion I (or Intel) caused. In our defense, we did discuss feature timing in the last two Intel developer forums (and now to my embarrassment, I see that presentation has been removed from the IDF content catalog at http://www.intel.com/idf , we'll have it up in time for the upcoming IDF on Oct 20). And it's on a separate CPUID feature flag (separate section of the document too ) in the programming reference.

Anyway, enough for my justifications. There is no intent to 'market' here, we're just engineers: Our strategy going forward is to disclose the industry early on our directions, first to get feedback on the value (and definition) of features like wider vectors, FMA, new instructions, and secondly to get software ready as early as possible. From your perspective is this the right strategy, or are we just confusing people? (and for anyone else reading this: While I appreciate the private mails, I especially like feedback discussions to happen in public forums...). So far I have collected a lot of feedback on the definition and direction and we hope to provide some public response to it shortly.

It sounds like you are an FMA supporter - beyond the raw FLOPS improvement, do you have any sensitivity to the numerical advantages FMA can provide? There are obviously a lot of tradeoffs in the implementations we can provide, and having some data to understand how you would use it would be very helpful.

Regards,

Mark Buxton
05-07-2009, 12:53 AM
Shintai

So Informal:

Lere is the instruction set regarding AVX from Intel:
http://software.intel.com/media/js/i...?f=/file/10069

Why doesnt the one you link from AMD match it? I mean its uspposed to be a superset. Yet its not even close.

Now you got the instruction list for both. lets see your socalled superset or even support. In reality AMD got a partial support.
05-07-2009, 01:22 AM
informal

Quote:

Originally Posted by Shintai

So Informal:

Lere is the instruction set regarding AVX from Intel:
http://software.intel.com/media/js/i...?f=/file/10069

Why doesnt the one you link from AMD match it? I mean its uspposed to be a superset. Yet its not even close.

Now you got the instruction list for both. lets see your socalled superset or even support. In reality AMD got a partial support.

The one I linked is a new addition to the AVX spec.,AMD's extension. AMD doesn't need to link to any of their own AVX specs since it is not their spec.It's intel's spec and its already listed at intel's site! You have AMD's senior architect say they WILL fully be AVX compliant and additionally support their own XOP extensions in the new superset.It's really not that hard to grasp,but you failing to do so is curious:confused:

Again I quote AMD's senior fellow:

Quote:

Since we don't control the definition of AVX, all we can say for sure is that we expect our initial products to be compatible with version 5 of the specification (the most recent one, as of this writing, published in January of 2009), except for the FMA instructions, which we expect will be compatible with version 3 (published in August of 2008).

We know FMA is not even in SB so it's not an issue.AMD will have its own more powerful FMA implementation through the XOP extension. FMA3 support will come with shrank BD core.
05-07-2009, 01:26 AM
Shintai

Why do you keep posting marketing? Common show the list and comparision?

Or is it because you cant? You claim its a superset so you must be aware of all the instructions involved.
05-07-2009, 01:42 AM
informal

Ahh i give up.You are something special. Your "marketing" claim is garbage since the post is from AMD's architect,not marketing dude.The engineering fellow said they will fully support AVX and add their own extensions(XOP etc.). If you can't understand this ,please try harder. It's simple and straightforward.If you are compatible with AVX it means you support the versions listed at intel's site .The XOP IS an additional extension set as it adds FMA among other stuff. FMA IS NOT in Sandy Bridge. You can read up some comments AMD's partners made about AMD's announcement and those quotes from them clearly state AMD will fully support both AVX and their own XOP instr. sets.

I can only speculate that your gigantic phailure to understand this comes from you inability to admit that you were wrong from the start.Now you keep digging that hole deeper and deeper and you can't get out of it...

PS Again for you from Mr. Christie:

Quote:

With this duplication of functionality between SSE5 and AVX/FMA, and AVX's additional features, we felt the right thing to do was to support AVX. In our minds, a more unified instruction set is clearly what's best for developers and the x86 software industry. With our acceptance of AVX, a key aspect of this instruction set unification is the stability of the specification. Since we don't control the definition of AVX, all we can say for sure is that we expect our initial products to be compatible with version 5 of the specification (the most recent one, as of this writing, published in January of 2009), except for the FMA instructions, which we expect will be compatible with version 3 (published in August of 2008).

Again,XOP extensions is and add-on,an "extra" if you will,proof is here:

Quote:

This week, AMD is making a couple of very important announcements for developers: support of Intel's Advanced Vector Extensions (AVX) instruction set in future AMD processors, and the adaptation to the AVX framework of AMD's previous SSE5 instruction set proposal. The latter step has resulted in three new extensions: XOP (for eXtended Operations), CVT16 (half-precision floating point converts), and FMA4 (four-operand Fused Multiply/Add). In this posting I'll give an overview of the capabilities that these extensions provide, and also some insight into why we're taking this step.

As you can see,the paragraphs states in no uncertain terms that there is a full AVX support with an added extra extension that consist of SB' lacking feature named FMA(among other things).AMD's XOP ext. set is a "leftover" from SSE5,the stuff that didn't overlap with AVX but could be a valuable addition to BD cores. Simple as 1-2-3. Keep reading it until you figure it out :rolleyes:
05-07-2009, 01:48 AM
Shintai

Quote:

Originally Posted by informal

Ahh i give up.You are something special. Your "marketing" claim is garbage since the post is from AMD's architect,not marketing dude.The engineering fellow said they will fully support AVX and add their own extensions(XOP etc.). If you can't understand this ,please try harder. It's simple and straightforward.If you are compatible with AVX it means you support the versions listed at intel's site .The XOP IS an additional extension set as it adds FMA among other stuff. FMA IS NOT in Sandy Bridge. You can read up some comments AMD's partners made about AMD's announcement and those quotes from them clearly state AMD will fully support both AVX and their own XOP instr. sets.

I can only speculate that your gigantic phailure to understand this comes from you inability to admit that you were wrong from the start.Now you keep digging that hole deeper and deeper and you can't get out of it...

And Phenom was 50% faster than Core 2 also..ye...

So in short, you cant. Because you dont know. You claim its a superset. Yet you dont know.

AMD expects to support a partial portion of AVX. What AMD calls AVX is funny enough not the same as what Intel calls AVX. Plus inside AVX you also got FMA, VEX.128, VEX.256 and AVX.

There was a reason i called you a marketing tool.
05-07-2009, 02:57 AM
informal

Quote:

Originally Posted by Shintai

And Phenom was 50% faster than Core 2 also..ye...

So in short, you cant. Because you dont know. You claim its a superset. Yet you dont know.

AMD expects to support a partial portion of AVX. What AMD calls AVX is funny enough not the same as what Intel calls AVX. Plus inside AVX you also got FMA, VEX.128, VEX.256 and AVX.

There was a reason i called you a marketing tool.

Priceless comments.You calling me a marketing tool?:rofl: People don't call you Shintel for nothing. You can't grasp a simple post from AMD's engineer.
AVX in SB does NOT support FMA.Period.

AMD states in no uncertain tems that they will support AVX.The difference will be FMA4 vs FMA3 and this is not an issue at first since SB won't have it anyway.You seem to fail at realizing SB just doesnt have FMA at all. What it will have is AVX minus the FMA addition.

Learn the meaning of the word Additional.

Quote:

The fact remains that AVX does not incorporate all of SSE5's features. Since SSE5 was based on months of discussions with ISVs on what sort of capabilities they felt were needed, and had been positively reviewed by the industry when we first put out the specification, we decided to follow through with development of these additional features. To do so most effectively, we redefined them in the AVX framework, resulting in the XOP extension.

The XOP ext. set is additional set to AVX support AMD will have in BD cores..ADDITIONAL SET. BD cores WILL support version 5 of AVX and version 3 of FMA. PERIOD. I gave you a direct quote of this and you can't accept it since you are.. well shintel-an (unofficial)intel rep from Denmark.

Version 5 of AVX you can find on intel's site you linked.

Quote:

Since we don't control the definition of AVX, all we can say for sure is that we expect our initial products to be compatible with version 5 of the specification (the most recent one, as of this writing, published in January of 2009), except for the FMA instructions, which we expect will be compatible with version 3 (published in August of 2008).

What AMD did with XOP was they used the SSE5 and the elements of it that was left out of AVX and made their own smaller set that will be a BD exclusive.It may have the same faith as 3Dnow,we do not know that.But XOP is just an additional set that coexists with AVX in Bulldozer.

Proof:

Quote:

: support of Intel's Advanced Vector Extensions (AVX) instruction set in future AMD processors, and the adaptation to the AVX framework of AMD's previous SSE5 instruction set proposal. The latter step has resulted in three new extensions: XOP (for eXtended Operations), CVT16 (half-precision floating point converts), and FMA4 (four-operand Fused Multiply/Add). In this posting I'll give an overview of the capabilities that these extensions provide, and also some insight into why we're taking this step.

The latter step(the adaptation to the AVX framework of AMD's previous SSE5 instruction set proposal) IS the XOP,CVT16,FMA4.This is the additional functionality in BD,apart from AVX (version 5) support.

You need to go back and re-read this 10 more times,maybe it will sink in:rofl::ROTF:
05-07-2009, 03:11 AM
Shintai

Quote:

Originally Posted by informal

Priceless comments.You calling me a marketing tool?:rofl: People don't call you Shintel for nothing. You can't grasp a simple post from AMD's engineer.
AVX in SB does NOT support FMA.Period.

AMD states in no uncertain tems that they will support AVX.The difference will be FMA4 vs FMA3 and this is not an issue at first since SB won't have it anyway.You seem to fail at realizing SB just doesnt have FMA at all. What it will have is AVX minus the FMA addition.

Learn the meaning of the word Additional.

The XOP ext. set is additional set to AVX support AMD will have in BD cores..ADDITIONAL SET. BD cores WILL support version 5 of AVX and version 3 of FMA. PERIOD. I gave you a direct quote of this and you can't accept it since you are.. well shintel-an (unofficial)intel rep from Denmark.

Version 5 of AVX you can find on intel's site you linked.

What AMD did with XOP was they used the SSE5 and the elements of it that was left out of AVX and made their own smaller set that will be a BD exclusive.It may have the same faith as 3Dnow,we do not know that.But XOP is just an additional set that coexists with AVX in Bulldozer.

Proof:

The latter step(the adaptation to the AVX framework of AMD's previous SSE5 instruction set proposal) IS the XOP,CVT16,FMA4.This is the additional functionality in BD,apart from AVX (version 5) support.

You need to go back and re-read this 10 more times,maybe it will sink in:rofl::ROTF:

You sure talk alot. But you cant list anything? Where is the pdf etc with AMDs instructionlist?
05-07-2009, 03:15 AM
Tomasis

None knows here except employees of companies. The end.
05-07-2009, 03:17 AM
informal

Shintai,are you blind or dumb? :confused: You can read can't you. Read what the man said. The CPU is due out in 2011. By that time they will certainly make public more manuals as they usually do,prior to the launch. Before this happens you have a word from one of the engineers that designed the core that BD will support AVX version 5 and FMA version 3 PLUS an additional XOP extensions(a "leftover" from SSE5 now ported to AVX VEX decoding scheme). It's fairly simple and you failing to grasp it shows either you have reading comprehension problems or you simply can't get it even if you can read what was written.

To recap:

1)AVX and FMA are not one at the same.SandyB,as intel rep said in my link,will not support FMA,while supporting AVX.
2)AMD will support AVX version 5,FMA version 3 and add their own,additional, XOP set which is a pack of instructions from former SSE5 with AVX decoding scheme.
05-07-2009, 03:58 AM
Hornet331

Quote:

Originally Posted by Brother Esau

Well I am sick and tired of these jerks poking fun of everyone and ruining everyone else s good time because they don't posses any manners respect or civility towards others. Its not right and its just Rude!

:rofl: i have nothing more to say after your last post to that.

@ topic

its nice to see amd get FMA before intel and i also hope this time the have some big compiler devs behind them (or even better release there own compilers) to make use of this instructions.
05-07-2009, 04:01 AM
informal

Hornet please stay on topic here. The thread is very interesting and the latest development of events with AMD stating they will fully support AVX v5 is major news,even though shintai tries to ignore it with hands over ears singing nananana :p: .

Hornet,AMD started the Open64 compiler project.It's a start.More info here.
05-07-2009, 06:04 AM
Particle

I think a karma system on this forum would be absolutely hilarious for threads like these. :)

All I know is that as a programmer, I'm happy to see some instruction set unification going on.
05-07-2009, 06:42 AM
Chad Boga

Quote:

Originally Posted by Brother Esau

Speaking of Intel who do you have to thank for your Insight into Overclocking a CPU with a IMC ??? You guessed it the AMD Fan Boys that you all kick ond torment relentlessly ...You guys make me laugh! Self Proclaimed experts talking a Bunch of :banana::banana::banana::banana: is all you do when we were the Ones Debugging Overclocking Quad Core with IMC you were all Talking :banana::banana::banana::banana: and Making Fun of us ..... I guarantee you that for you die Hard Intel Fans here you would know nothing about not blowing up your Precious Nehalem Rigs if it wasn't for us doing all of the work for the Past Year and a Half ya'll wouldn't have a clue in hell and there sure as hell would have been allot of Toasted CPU'S and Motherboards if it weren't for all of us lowly Commoners in the AMD Sector.

Do me a favor all of you shut up and be thankful for what we have given you we are all tired of hearing your Whiny Frigging Negative dysfunctional Rhetoric so piss off or be civil and have some damn manners and respect towards your fellow man.

:ROTF::clap::ROTF::clap::ROTF::clap::ROTF::clap: :ROTF:
05-07-2009, 06:47 AM
Tomasis

Quote:

Originally Posted by Brother Esau

Speaking of Intel who do you have to thank for your Insight into Overclocking a CPU with a IMC ??? You guessed it the AMD Fan Boys that you all kick ond torment relentlessly ...You guys make me laugh! Self Proclaimed experts talking a Bunch of :banana::banana::banana::banana: is all you do when we were the Ones Debugging Overclocking Quad Core with IMC you were all Talking :banana::banana::banana::banana: and Making Fun of us ..... I guarantee you that for you die Hard Intel Fans here you would know nothing about not blowing up your Precious Nehalem Rigs if it wasn't for us doing all of the work for the Past Year and a Half ya'll wouldn't have a clue in hell and there sure as hell would have been allot of Toasted CPU'S and Motherboards if it weren't for all of us lowly Commoners in the AMD Sector.

Do me a favor all of you shut up and be thankful for what we have given you we are all tired of hearing your Whiny Frigging Negative dysfunctional Rhetoric so piss off or be civil and have some damn manners and respect towards your fellow man.

I dont remind to re-quote again . It is what it is. The fight between David and Goliat. Socialists should support the weaker ones :rofl:
05-07-2009, 07:15 AM
v_rr

Quote:

Originally Posted by Shintai

You sure talk alot. But you cant list anything? Where is the pdf etc with AMDs instructionlist?

Even if you have it, you go there and lost 1 entire day comparing 100++ instructions 1 by 1? Ya right :rolleyes:
05-07-2009, 08:16 AM
ajaidev

Quote:

Originally Posted by informal

Shintai,are you blind or dumb? :confused: You can read can't you. Read what the man said. The CPU is due out in 2011. By that time they will certainly make public more manuals as they usually do,prior to the launch. Before this happens you have a word from one of the engineers that designed the core that BD will support AVX version 5 and FMA version 3 PLUS an additional XOP extensions(a "leftover" from SSE5 now ported to AVX VEX decoding scheme). It's fairly simple and you failing to grasp it shows either you have reading comprehension problems or you simply can't get it even if you can read what was written.

To recap:

1)AVX and FMA are not one at the same.SandyB,as intel rep said in my link,will not support FMA,while supporting AVX.
2)AMD will support AVX version 5,FMA version 3 and add their own,additional, XOP set which is a pack of instructions from former SSE5 with AVX decoding scheme.

You are right that AVX does not include FMA in the SB but it might. AVX allready has 3 rev's that i know of. SB has a weakness tough even if it supports FMA 3 and FMA 4 and BD supports FMA 4 do you people really think developers would use FMA 3 "Just to clear it up FMA 3 is destructive and FMA 4 is not that simply means FMA 4 is superior than FMA 3, think of them as WAV and MP3."

BTW people who are worshiping the intel AVX pls read the AMD's SSE5 original outline which was months before intel even mentioned AVX.

Show 100 post(s) from this thread on one page