Socket AM2+ and AM3 details inside
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http://www.theinquirer.net/default.aspx?article=41097
Quote:
65nm, 45nm CPUs to fit into every AM2 motherboard
By Theo Valich: Friday 20 July 2007, 15:27
ONE OF THE BIGGEST mistakes AMD management did recently was the over confident and pompous slaying of the socket 754/939 processor line-up. People didn't want to upgrade, and those that had to upgrade opted for Socket 775 and Intel Core 2 offerings.
According to our sources, AMD has understood the error of its ways and future processor sockets will be interoperable, at least in the upgrade scheme of things. Owners of Socket AM2 and AM2+ motherboards should have no problems fitting not just current and future K10 quad-core and dual-core processors known as Agena (Phenom X4 GP-7000), Kuma (Phenom X2 GS/GE-6000) and Rana (Athlon X2 BE/LS-2000), but you will also be able to fit 45nm Deneb/Propus/Regor cores from the future (H2'08) that support both DDR2 and DDR3 memory.
The processors of today will not work with motherboards that feature DDR3 supporting Socket AM3, but the other way around should work like a charm. This was done by keeping identical power requirements for the motherboard makers.
We learned that for high-performing motherboards, AMD is requiring that AM2+ motherboards support 125W processors using 95A VRM (Voltage Regulation Module capable of delivering 95 Ampers), and that requirement will not change with AM3 socket. When it comes to the ainstream, cost-effective land - motherboard makers have to provide 89W using 80 Amper current (80A). So, we have three sockets from AMD - AM2, AM2+ and AM3 being physically and electrically identical.
There is also a second version of AM2 socket intended for value segment, the DTX form factor, to be more precise, and that cannot deliver more than 65W using 45 Amper current. This one will fit both 65nm and 45nm K10 processors with low-power markings, the ones around 65W.
Even though AMD is mixing'n'matching right now, judging by the amount of e-mails we have received in the past two years - this policy might prove better than Intel's. That's keeping the same socket, but changing the VRMs to point of zero backwards compatibility. µ
Interesting article on Tech ARP!
I found this article quite interesting!
It has some new technical data about Barcelona design...
Quote:
L1 Cache
Each core in the Barcelona will have a dedicated 128KB, 2-way set associative L1 cache. This is twice the size of the L1 cache available to each core in the Intel Core 2 processor. The latency for the processor to retrieve data from the L1 cache is 3 clock cycles.
L2 Cache
In the Core 2 design, Intel makes use of a large L2 cache shared between two cores. AMD, however, has chosen to use a smaller, dedicated 512KB L2 cache for each processing core. That means the quad-core Opteron processor will have four separate 512KB L2 caches. These caches are 16-way set associative, and the latency for each core to retrieve data from its L2 cache is 12 clock cycles.
L3 Cache
The Barcelona features a large, shared L3 cache that is at least 2MB in size. This L3 cache will be shared by all cores, whether it's a dual-core or quad-core processor.
This cache is 32-way set associative and is based on a non-inclusive victim cache architecture. The latency for any core to retrieve data from the L3 cache is said to be less than 38 clock cycles. Oddly enough, AMD says the actual latency depends on the clock speed of the south bridge.
:up:
Check out full article here!
http://www.eweek.com/article2/0,1895,2161022,00.asp