K10 Scores starting to surface

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Originally Posted by Donnie27

Sorry I missed this one, but was it turned back on for other tests?

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unknown.

dave

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Originally Posted by bingo13

The B2s clock nicely on air, just cannot show results yet as the L1N64 replacement is still under NDA. As for the Phenoms, it is too early to tell based on the current core release, but the RD790 does a very nice job of overclocking a 6400+. ;)

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Can't wait to see that. :cool:

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Originally Posted by JumpingJack

Anand posted a CPUID of the 2.5 GHz chip:
http://www.anandtech.com/cpuchipsets...spx?i=3092&p=2

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Thanks, forgot about that. Thats the B2 core, the code says it v.clearly. Should've been more clear - I'm wanting to see the CPUZ for the launch processors they all reviewed, which were B1s; like Coolaler forum, Daves, TechwareLabs, TechReports and Stephens.

This is the CPUZ string a B1 gives (missing the DR-B1 in the revision field, even though its Agena)

http://img256.imageshack.us/img256/5...rimeko3.th.jpg

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Originally Posted by KTE

Thanks, forgot about that. Thats the B2 core, the code says it v.clearly. Should've been more clear - I'm wanting to see the CPUZ for the launch processors they all reviewed, which were B1s; like Coolaler forum, Daves, TechwareLabs, TechReports and Stephens.

This is the CPUZ string a B1 gives (missing the DR-B1 in the revision field, even though its Agena)

http://img256.imageshack.us/img256/5...rimeko3.th.jpg

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Yeah ... CPUID still needs a little more work to get all the info correct, but F22 is B2 I do believe.

Jack

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Originally Posted by dave_graham

some clarification.

for reference, AMD doesn't call anything F+. It's simply Socket L1 (Socket F) and Socket L1-SP (split-plane; what people are calling F+).

back to the HT links for a second.

there's still a 2 hop penalty since only 1 of the 2 intra-CPU links are coherent. the secondary link is simply used to pass traffic. As there has been no realistic testing on even the 23xx series to determine utilization of that second link (and even it's performance) it's still safe to assume that n-way configurations will need to be passed over the coherent links only and, as such, will still require two hops. I'll get confirmation of this when I can. :)

here's a quick and dirty illustration.


does that make sense? one lane of each HT pair is coherent.

cheers,

dave

EDIT: F'ing software isn't lining my pipes up correctly....

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I made a mistake because 8S topology has 3 hops and 4S 2 hops :)

I through that Opties 22xx had 3 HT links with only 1 ccHT but Opties 82xx had 3 HT links with all 3 ccHT enabled.

4S fully connected with plenty of I/O using Opteron 82xx - 2 HOP

................I/O
.................|
...CPU1.--.CPU2
.....|..\........|
.....|.....\.....|
...CPU3.--.CPU4
.....|
....I/O

8S using Opteron 82xx as an example CPU8 needs 3 hops to get data from CPU7

................CPU1.--.CPU2.--.CPU3
................/.....\......|..../..........\
............../.........\....|./...............\
I/O.-.CPU7.............\/|................CPU8 - I/O
..............\....... ../...|.\............../
................\....../.....|.....\......../
...............CPU4.--.CPU5.--.CPU6


If Barcelona can use 4 ccHT links now then it's great for scaling 4S/8S systems, but I remember that this feature was on roadmaps only for 45nm HT3 enabled successor of Barcelona. Can you clarify that for me Dave?? :help: