Thats an amazing looking board, question is that molex for the sli power as they had on 680i boards and such.
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That's one impressive looking board. My only main concern is "only" six SATA ports. I've got those filled already, and my next build will likely include a couple of SSDs to park my OS on. Here's to hoping for a revision board with one of the SATA3 controllers and a couple more SATA ports on it down the road. considering EVGA has released three or 4 revisions of the X58C, I'd say it's a possibility.
http://img24.imageshack.us/img24/6631/134ncy.jpg
1: why 2 connector?
2: ugly-strange-use for?
3: graphic memory with relative clock gen?
4: graphic memory upgrade?
1) evga dose this on the other boards
2) its so wont kill the pci-e slots when they over draw from the slot or cause stability problems, dfi and other high ends have it and its needed for tri and quad gpu
3) with dual clock gens i have no clue
4) its for intel turbo memory, like in laptops
maybe here I get the answer. Is evga planing to do motherboard for amd cpus, something like classified ? Or evga is "intel only" ?
Or the iclock..
Very Nice! I like the all black color scheme. Never had an EVGA board. I was thinking of going Gigabyte for my next build, but this might have changed my mind.
i really hope this mobo will not have a high price tag :-)
wait wait wait :D
Sent them an email late yesterday afternoon to find out if they had any objections. Unfortunately, the L key on my keyboard skips sometimes and they were not amused at the proposed name. Especially seeing as I told them that their were hoardes of juvenile men who could not wait to get their greasy palms on one.. :D
With 2 seperate PLL's, period jitter and random jitter of both reference clock signals will be out of phase at the synthesizer of downstream busses (the jitter has nothing to do with clock skew per se btw). Depends how the associated sampling windows are affected by that (when the opposite clock domain has a seperate master oscillator). You might get a smaller logic sampling window as a result, at which point some form of skew might help, but you'll still be playing with narrower sampling margins if the jitter is excessive. I should add though that the associated synthesizer of each clock signal will add its own jitter to the reference clock (regardless of the reference clock source). We have no external high speed interconnect like QPI on i5, i7 and beyond is where master clock jitter is really becoming a big deal. The proof will be in the final oc limits I guess.
EVGA P55 Motherboards @ Computex 2009
http://www.youtube.com/watch?v=5MS3b...&feature=email
Co-apresentation by shamino
Man i'd like to see a mobo with Sanoy Os-Cons in cpu VRM :wasntme:
Those things last 20yrs
would you really want a p55 board in 2029? :eek: :D
think twice about what you wish for! heheh
id like to see at least 3 16x slots hooked up to the cpu :D
yeh you heard me...
why force people to 1366 to run tri sli/tri xfire? would be annoying to have to maintain 2 systems for benchers...
It doesn't bother me too much, 2nd Gen PCI-Express 8x offers the same bandwith as 1st gen PCI-E 16x and that is more then enough even for SLI/Crossfire. Unless software SLI/Crossfire is used. The thing that bothers me is the 3rd slot running at 4x which will mean you will see a slight drop in performance.
nice pics and really sexy board:up:
:shocked::shocked::shocked: SLi