Actually, if my math is right, my latency is lower, and my bandwidth is higher.
474 = 237Mhz = 4.22ns(time per clock) x 4 = 16.87ns
610 = 305Mhz = 3.27ns(time per clock) x 5 = 16.39ns
Remember, latency isnt just the clock setting you put in the bios. You have to factor in the time of each clock. Saying CL4 > CL5 is like saying a 11x multi > 10x multi... kind of meaningless unless you know the FSB of each.
I also racked up this too, 5m 42s wPrime1024:
http://i444.photobucket.com/albums/q...1024342984.jpg
So close to beating the top 9950, if i could just run for 6 minutes at 3.5ghz!
Just need to go a bit colder. Temps were around 19-21c for that run (judging by water temp, which was 6c). Its supposed to go -35c here again next week, so i should see some sub-zero core temps.
I seen that, and from what i heard, avoid it. Some how they totally screwed it up. Expecting a 2.1.6 to follow suit in the near future. Seen people posting screenshots of 9950s @ 4.2ghz @ 1.3v lolQuote:
Originally Posted by QuietIce