I am surprised that no one has talked about this more in regards to power consumption and also clocking ability. So here goes..:confused:
First how many transistors does the L3 cache account for? Anandtech has mentioned that it will be taken out of bulldozer derivatives which includes trinity, Piledriver, and all future cores because it serves no purpose. Only benefits server type workloads. Here is a link of Anandtech and VR-zone mentioning its non importance with regards to trinity and future derivatives, and techreport mentioning how it didnt provide much more bandwidth.
http://www.anandtech.com/show/4955/t...x8150-tested/2
http://vr-zone.com/articles/report-a...led/13807.html
http://techreport.com/articles.x/21813/6
But my question is how many of those 2 billion transistors are the 8mb l3 cache? Everyone knows by the die size the L3 takes up alot of space. Also how much would power consumption decrease, and clocking ability increase with the L3 cutout. I think that is how they are getting the power reductions in trinity. I am curious because not just one site and many here even say that bulldozer is a server chip just released for us also with pushed up clocks. Also most know the l3 cache serves only servers because they can always recompile programs quickly for server systems internally.
The consumer programs dont nearly get updated and recompiled as quickly as server workload programs do. Is AMD likely to have a two production lines? One low demand with L3 cache for servers, second high demand mainstream no L3 cache?